OvmfPkg/PlatformPei: Initialise RCBA (B0:D31:F0 0xf0) register

This patch initialises root complex register block BAR in order to
support TCO watchdog emulation features (e.g. reboot upon NO_REBOOT bit
not set) on QEMU.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Paulo Alcantara <pcacjr@zytor.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17601 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
index 4f59a7c0e3e0f52eedc67fb2b509bb65d3e101f0..18b34a3d4f4ecd2925f3e66f03649e2e32b70892 100644 (file)
--- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
+++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
@@ -77,6 +77,9 @@
 #define ICH9_GEN_PMCON_1          0xA0\r
 #define ICH9_GEN_PMCON_1_SMI_LOCK   BIT4\r
 \r
+#define ICH9_RCBA                 0xF0\r
+#define ICH9_RCBA_EN                BIT0\r
+\r
 //\r
 // IO ports\r
 //\r
@@ -90,4 +93,6 @@
 #define ICH9_SMI_EN_APMC_EN      BIT5\r
 #define ICH9_SMI_EN_GBL_SMI_EN   BIT0\r
 \r
+#define ICH9_ROOT_COMPLEX_BASE 0xFED1C000\r
+\r
 #endif\r

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 0e41d305c7dcf9c6e6e6e8d04edcfabf1ee57b77..1ad5bfc26a09a1d6fb09784609d7dc005bacaaa4 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -214,13 +214,18 @@ MemMapInitialization (
     // 0xFEC00000    IO-APIC                        4 KB\r
     // 0xFEC01000    gap                         1020 KB\r
     // 0xFED00000    HPET                           1 KB\r
-    // 0xFED00400    gap                         1023 KB\r
+    // 0xFED00400    gap                          111 KB\r
+    // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB\r
+    // 0xFED20000    gap                          896 KB\r
     // 0xFEE00000    LAPIC                          1 MB\r
     //\r
     AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
                          BASE_2GB : TopOfLowRam, 0xFC000000);\r
     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
+    if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+      AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
+    }\r
     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
   }\r
 }\r
@@ -292,6 +297,16 @@ MiscInitialization (
     //\r
     PciOr8 (AcpiCtlReg, AcpiEnBit);\r
   }\r
+\r
+  if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+    //\r
+    // Set Root Complex Register Block BAR\r
+    //\r
+    PciWrite32 (\r
+      POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
+      ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
+      );\r
+  }\r
 }\r
 \r
 \r