ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
- ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
- ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibPrePi.inf
- ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf
ArmPkg/Library/ArmLib/Null/NullArmLib.inf
ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf
ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
ArmPkg/Library/SemihostLib/SemihostLib.inf
ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+ ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf
+ ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
+ ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
ArmPkg/Drivers/CpuDxe/CpuDxe.inf
ArmPkg/Drivers/CpuPei/CpuPei.inf
ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
[PcdsFixedAtBuild.common]\r
# These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.\r
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
- gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003\r
gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r
\r
# Stack for CPU Cores in Secure Mode\r
\r
[LibraryClasses.common]\r
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf\r
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf\r
\r
# ARM PL390 General Interrupt Driver in Secure and Non-secure\r
[BuildOptions]\r
RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8 --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
\r
- GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+ GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a8 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
\r
XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
\r
\r
[LibraryClasses.common]\r
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf\r
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf\r
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf\r
\r
# ARM PL390 General Interrupt Driver in Secure and Non-secure\r
[BuildOptions]\r
RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A9 --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
\r
- GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
+ GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a9 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
\r
XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform\r
\r
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x43FE0000\r
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00020000\r
\r
- gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1\r
- \r
# Stacks for MPCores in Secure World\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x4B000000\r
# Stacks for MPCores in Monitor Mode\r
[LibraryClasses.common]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
ArmTrustZoneLib|ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
- gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
gArmTokenSpaceGuid.PcdVFPEnabled|1
# Stacks for MPCores in Secure World
[LibraryClasses.common]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
- gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
gArmTokenSpaceGuid.PcdVFPEnabled|1
# Stacks for MPCores in Secure World
# CPU / Architectural controllers\r
gArmTokenSpaceGuid.PcdGicDistributorBase : Base address of the Distributor of your General Interrupt Controller\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase : Base address of the Interface of your General Interrupt Controller\r
-gArmPlatformTokenSpaceGuid.PcdMPCoreSupport : Set to 1 when MP Core platforms\r
\r
# Memory Regions\r
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize : Size of the region reserve for PI & UEFI\r
**/
#include <Library/DebugAgentLib.h>
-#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
#include <Library/BaseMemoryLib.h>
-#include <Library/ArmLib.h>
#include <Library/SerialPortLib.h>
#include <Library/ArmPlatformLib.h>
#include <Library/ArmGicLib.h>
+#include <Library/ArmCpuLib.h>
#include "SecInternal.h"
// Primary CPU clears out the SCU tag RAMs, secondaries wait
if (IS_PRIMARY_CORE(MpId)) {
- if (FixedPcdGet32(PcdMPCoreSupport)) {
- ArmInvalidScu ();
+ ArmCpuSetup (MpId);
+
+ if (ArmIsMpCore()) {
+ ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT);
}
// SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
// Now we've got UART, make the check:
// - The Vector table must be 32-byte aligned
ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0);
+
+ // Enable the GIC distributor and CPU Interface
+ // - no other Interrupts are enabled, doesn't have to worry about the priority.
+ // - all the cores are in secure state, use secure SGI's
+ ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
+ ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+ } else {
+ // Enable the GIC CPU Interface
+ ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
}
// Invalidate the data cache. Doesn't have to do the Data cache clean.
// Enable Full Access to CoProcessors
ArmWriteCPACR (CPACR_CP_FULL_ACCESS);
- // Enable SWP instructions
- ArmEnableSWPInstruction ();
-
- // Enable program flow prediction, if supported.
- ArmEnableBranchPrediction ();
-
- if (FixedPcdGet32(PcdVFPEnabled)) {
+ if (FixedPcdGet32 (PcdVFPEnabled)) {
ArmEnableVFP();
}
// If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
// If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
- if (FeaturePcdGet(PcdSystemMemoryInitializeInSec)) {
+ if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
// Initialize system memory (DRAM)
ArmPlatformInitializeSystemMemory ();
}
ASSERT(PcdGet32(PcdCPUCoresSecMonStackBase) != 0);
ASSERT(PcdGet32(PcdCPUCoreSecMonStackSize) != 0);
- if (FixedPcdGet32(PcdMPCoreSupport)) {
+ if (ArmIsMpCore()) {
// Setup SMP in Non Secure world
- ArmSetupSmpNonSecure (GET_CORE_ID(MpId));
+ ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
}
// Enter Monitor Mode
if (IS_PRIMARY_CORE(MpId)) {
ArmPlatformTrustzoneInit ();
- // Wake up the secondary cores by sending a interrupt to everyone else
- // NOTE 1: The Software Generated Interrupts are always enabled on Cortex-A9
- // MPcore test chip on Versatile Express board, So the Software doesn't have to
- // enable SGI's explicitly.
- // 2: As no other Interrupts are enabled, doesn't have to worry about the priority.
- // 3: As all the cores are in secure state, use secure SGI's
- //
-
- ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
- ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
-
- // Send SGI to all Secondary core to wake them up from WFI state.
- ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
+ // Waiting for the Primary Core to have finished to initialize the Secure World
+ ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT);
} else {
// The secondary cores need to wait until the Trustzone chipsets configuration is done
// before switching to Non Secure World
- // Enabled GIC CPU Interface
- ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
-
- // Waiting for the SGI from the primary core
- ArmCallWFI();
-
- // Acknowledge the interrupt and send End of Interrupt signal.
- ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
+ // Waiting for the Primary Core to have finished to initialize the Secure World
+ ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT);
}
// Transfer the interrupt to Non-secure World
- ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
+ ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
// Write to CP15 Non-secure Access Control Register :
// - Enable CP10 and CP11 accesses in NS World
SerialPrint ("Trust Zone Configuration is disabled\n\r");
}
- // Trustzone is not enabled, just enable the Distributor and CPU interface
- if (IS_PRIMARY_CORE(MpId)) {
- ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
- }
- ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
-
// With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
// If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
// Status Register as the the current one (CPSR).
-#/** @file
-# SEC - Reset vector code that jumps to C and loads DXE core
-#
-# Copyright (c) 2011, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = ArmPlatformSec
- FILE_GUID = c536bbfe-c813-4e48-9f90-01fe1ecf9d54
- MODULE_TYPE = SEC
- VERSION_STRING = 1.0
-
-[Sources.ARM]
- Helper.asm | RVCT
- Helper.S | GCC
- Sec.c
- SecEntryPoint.S | GCC
- SecEntryPoint.asm | RVCT
- Exception.asm | RVCT
- Exception.S | GCC
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
-
-[LibraryClasses]
- ArmLib
- ArmPlatformLib
- BaseLib
- DebugLib
- DebugAgentLib
- IoLib
- ArmGicSecLib
- PrintLib
- SerialPortLib
-
-[FeaturePcd]
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec
-
-[FixedPcd]
- gArmTokenSpaceGuid.PcdVFPEnabled
- gArmPlatformTokenSpaceGuid.PcdMPCoreSupport
-
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
- gArmTokenSpaceGuid.PcdArmPrimaryCore
-
- gArmTokenSpaceGuid.PcdFvBaseAddress
-
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize
-
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
-
- gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize
+#/** @file\r
+# SEC - Reset vector code that jumps to C and loads DXE core\r
+# \r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+# \r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmPlatformSec\r
+ FILE_GUID = c536bbfe-c813-4e48-9f90-01fe1ecf9d54\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+\r
+[Sources.ARM]\r
+ Helper.asm | RVCT\r
+ Helper.S | GCC\r
+ Sec.c\r
+ SecEntryPoint.S | GCC\r
+ SecEntryPoint.asm | RVCT\r
+ Exception.asm | RVCT\r
+ Exception.S | GCC\r
+ \r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ ArmCpuLib\r
+ ArmLib\r
+ ArmPlatformLib\r
+ BaseLib\r
+ DebugLib\r
+ DebugAgentLib\r
+ IoLib\r
+ ArmGicSecLib\r
+ PrintLib\r
+ SerialPortLib\r
+ \r
+[FeaturePcd]\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec\r
+ \r
+[FixedPcd]\r
+ gArmTokenSpaceGuid.PcdVFPEnabled\r
+ \r
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore\r
+ \r
+ gArmTokenSpaceGuid.PcdFvBaseAddress\r
+ \r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize\r
+ \r
+ gArmTokenSpaceGuid.PcdGicDistributorBase\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
+ \r
+ gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize \r
\r
#include <AutoGen.h>\r
#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
+#include "SecInternal.h"\r
\r
.text\r
.align 3\r
\r
-GCC_ASM_EXPORT(_ModuleEntryPoint)\r
-\r
GCC_ASM_IMPORT(CEntryPoint)\r
GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r
GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)\r
GCC_ASM_IMPORT(ArmWriteVBar)\r
GCC_ASM_IMPORT(ArmReadMpidr)\r
GCC_ASM_IMPORT(SecVectorTable)\r
-\r
-#if (FixedPcdGet32(PcdMPCoreSupport))\r
-GCC_ASM_IMPORT(ArmIsScuEnable)\r
-#endif\r
+GCC_ASM_IMPORT(ArmCpuSynchronizeWait)\r
+GCC_ASM_EXPORT(_ModuleEntryPoint)\r
\r
StartupAddr: .word ASM_PFX(CEntryPoint)\r
-SecVectorTableAddr: .word ASM_PFX(SecVectorTable)\r
\r
ASM_PFX(_ModuleEntryPoint):\r
// First ensure all interrupts are disabled\r
// Only the primary core initialize the memory (SMC)\r
beq _InitMem\r
\r
-#if (FixedPcdGet32(PcdMPCoreSupport))\r
- // ... The secondary cores wait for SCU to be enabled\r
-_WaitForEnabledScu:\r
- bl ASM_PFX(ArmIsScuEnable)\r
- tst r1, #1\r
- beq _WaitForEnabledScu\r
+_WaitInitMem:\r
+ mov r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
+ bl ASM_PFX(ArmCpuSynchronizeWait)\r
+ // Now the Init Mem is initialized, we setup the secondary core stacks\r
b _SetupSecondaryCoreStack\r
-#endif\r
\r
_InitMem:\r
// Initialize Init Boot Memory\r
\r
// Get the base of the stack for the secondary cores\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
add r1, r1, r2\r
\r
// StackOffset = CorePos * StackSize\r
-//
-// Copyright (c) 2011, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//
-
-#include <AutoGen.h>
-#include <AsmMacroIoLib.h>
-#include <Base.h>
-#include <Library/PcdLib.h>
-#include <Library/ArmPlatformLib.h>
-
- INCLUDE AsmMacroIoLib.inc
-
- IMPORT CEntryPoint
- IMPORT ArmPlatformSecBootAction
- IMPORT ArmPlatformInitializeBootMemory
- IMPORT ArmDisableInterrupts
- IMPORT ArmDisableCachesAndMmu
- IMPORT ArmWriteVBar
- IMPORT ArmReadMpidr
- IMPORT SecVectorTable
- EXPORT _ModuleEntryPoint
-
-#if (FixedPcdGet32(PcdMPCoreSupport))
- IMPORT ArmIsScuEnable
-#endif
-
- PRESERVE8
- AREA SecEntryPoint, CODE, READONLY
-
-StartupAddr DCD CEntryPoint
-
-_ModuleEntryPoint
- // First ensure all interrupts are disabled
- blx ArmDisableInterrupts
-
- // Ensure that the MMU and caches are off
- blx ArmDisableCachesAndMmu
-
- // Jump to Platform Specific Boot Action function
- blx ArmPlatformSecBootAction
-
- // Set VBAR to the start of the exception vectors in Secure Mode
- ldr r0, =SecVectorTable
- blx ArmWriteVBar
-
-_IdentifyCpu
- // Identify CPU ID
- bl ArmReadMpidr
- // Get ID of this CPU in Multicore system
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
- and r5, r0, r1
-
- // Is it the Primary Core ?
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)
- cmp r5, r1
- // Only the primary core initialize the memory (SMC)
- beq _InitMem
-
-#if (FixedPcdGet32(PcdMPCoreSupport))
- // ... The secondary cores wait for SCU to be enabled
-_WaitForEnabledScu
- bl ArmIsScuEnable
- tst r1, #1
- beq _WaitForEnabledScu
- b _SetupSecondaryCoreStack
-#endif
-
-_InitMem
- // Initialize Init Boot Memory
- bl ArmPlatformInitializeBootMemory
-
- // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
-
-_SetupPrimaryCoreStack
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r2)
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r3)
- // Calculate the Top of the Stack
- add r2, r2, r3
- LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r3)
-
- // The reserved space for global variable must be 8-bytes aligned for pushing
- // 64-bit variable on the stack
- SetPrimaryStack (r2, r3, r1)
-
- // Set all the SEC global variables to 0
- mov r3, sp
- mov r1, #0x0
-_InitGlobals
- str r1, [r3], #4
- cmp r3, r2
- blt _InitGlobals
-
- b _PrepareArguments
-
-_SetupSecondaryCoreStack
- // Get the Core Position (ClusterId * 4) + CoreId
- GetCorePositionInStack(r0, r5, r1)
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
- add r0, r0, #1
-
- // Get the base of the stack for the secondary cores
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
- add r1, r1, r2
-
- // StackOffset = CorePos * StackSize
- mul r0, r0, r2
- // SP = StackBase + StackOffset
- add sp, r1, r0
-
-
-_PrepareArguments
- // Move sec startup address into a data register
- // Ensure we're jumping to FV version of the code (not boot remapped alias)
- ldr r3, StartupAddr
-
- // Jump to SEC C code
- // r0 = mp_id
- mov r0, r5
- blx r3
-
-_NeverReturn
- b _NeverReturn
- END
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AutoGen.h>\r
+#include <AsmMacroIoLib.h>\r
+#include "SecInternal.h"\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+ \r
+ IMPORT CEntryPoint\r
+ IMPORT ArmPlatformSecBootAction\r
+ IMPORT ArmPlatformInitializeBootMemory\r
+ IMPORT ArmDisableInterrupts\r
+ IMPORT ArmDisableCachesAndMmu\r
+ IMPORT ArmWriteVBar\r
+ IMPORT ArmReadMpidr\r
+ IMPORT SecVectorTable\r
+ IMPORT ArmCpuSynchronizeWait\r
+ EXPORT _ModuleEntryPoint\r
+\r
+ PRESERVE8\r
+ AREA SecEntryPoint, CODE, READONLY\r
+ \r
+StartupAddr DCD CEntryPoint\r
+\r
+_ModuleEntryPoint\r
+ // First ensure all interrupts are disabled\r
+ blx ArmDisableInterrupts\r
+\r
+ // Ensure that the MMU and caches are off\r
+ blx ArmDisableCachesAndMmu\r
+\r
+ // Jump to Platform Specific Boot Action function\r
+ blx ArmPlatformSecBootAction\r
+\r
+ // Set VBAR to the start of the exception vectors in Secure Mode\r
+ ldr r0, =SecVectorTable\r
+ blx ArmWriteVBar\r
+\r
+_IdentifyCpu \r
+ // Identify CPU ID\r
+ bl ArmReadMpidr\r
+ // Get ID of this CPU in Multicore system\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
+ and r5, r0, r1\r
+ \r
+ // Is it the Primary Core ?\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)\r
+ cmp r5, r1\r
+ // Only the primary core initialize the memory (SMC)\r
+ beq _InitMem\r
+ \r
+_WaitInitMem\r
+ mov r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
+ bl ArmCpuSynchronizeWait\r
+ // Now the Init Mem is initialized, we setup the secondary core stacks\r
+ b _SetupSecondaryCoreStack\r
+ \r
+_InitMem\r
+ // Initialize Init Boot Memory\r
+ bl ArmPlatformInitializeBootMemory\r
+ \r
+ // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r
+\r
+_SetupPrimaryCoreStack\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r2)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r3)\r
+ // Calculate the Top of the Stack\r
+ add r2, r2, r3\r
+ LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r3)\r
+\r
+ // The reserved space for global variable must be 8-bytes aligned for pushing\r
+ // 64-bit variable on the stack\r
+ SetPrimaryStack (r2, r3, r1)\r
+\r
+ // Set all the SEC global variables to 0\r
+ mov r3, sp\r
+ mov r1, #0x0\r
+_InitGlobals\r
+ str r1, [r3], #4\r
+ cmp r3, r2\r
+ blt _InitGlobals\r
+\r
+ b _PrepareArguments\r
+\r
+_SetupSecondaryCoreStack\r
+ // Get the Core Position (ClusterId * 4) + CoreId\r
+ GetCorePositionInStack(r0, r5, r1)\r
+ // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
+ add r0, r0, #1\r
+\r
+ // Get the base of the stack for the secondary cores\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
+ add r1, r1, r2\r
+\r
+ // StackOffset = CorePos * StackSize\r
+ mul r0, r0, r2\r
+ // SP = StackBase + StackOffset\r
+ add sp, r1, r0\r
+\r
+\r
+_PrepareArguments\r
+ // Move sec startup address into a data register\r
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ ldr r3, StartupAddr\r
+ \r
+ // Jump to SEC C code\r
+ // r0 = mp_id\r
+ mov r0, r5\r
+ blx r3\r
+ \r
+_NeverReturn\r
+ b _NeverReturn\r
+ END\r
#define __SEC_H__\r
\r
#include <Base.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/ArmCpuLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
-\r
-#include <Chipset/ArmV7.h>\r
+#include <Library/PcdLib.h>\r
\r
#define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)\r
\r
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