Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14436
6f19259b-4bc3-4df7-8a09-
765794883524
\r
ArmCleanInvalidateDataCache ();\r
ArmInvalidateInstructionCache ();\r
- ArmInvalidateTlb ();\r
\r
ArmDisableDataCache ();\r
ArmDisableInstructionCache();\r
+ // TLBs are also invalidated when calling ArmDisableMmu()\r
ArmDisableMmu ();\r
\r
// Make sure nothing sneaked into the cache\r