Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);\r
AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);\r
@endcode\r
+ @note MSR_P6_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
**/\r
#define MSR_P6_P5_MC_ADDR 0x00000000\r
\r
Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);\r
AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);\r
@endcode\r
+ @note MSR_P6_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
**/\r
#define MSR_P6_P5_MC_TYPE 0x00000001\r
\r
Msr = AsmReadMsr64 (MSR_P6_TSC);\r
AsmWriteMsr64 (MSR_P6_TSC, Msr);\r
@endcode\r
+ @note MSR_P6_TSC is defined as TSC in SDM.\r
**/\r
#define MSR_P6_TSC 0x00000010\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);\r
@endcode\r
+ @note MSR_P6_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.\r
**/\r
#define MSR_P6_IA32_PLATFORM_ID 0x00000017\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE);\r
AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64);\r
@endcode\r
+ @note MSR_P6_APIC_BASE is defined as APIC_BASE in SDM.\r
**/\r
#define MSR_P6_APIC_BASE 0x0000001B\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON);\r
AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64);\r
@endcode\r
+ @note MSR_P6_EBL_CR_POWERON is defined as EBL_CR_POWERON in SDM.\r
**/\r
#define MSR_P6_EBL_CR_POWERON 0x0000002A\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL);\r
AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64);\r
@endcode\r
+ @note MSR_P6_TEST_CTL is defined as TEST_CTL in SDM.\r
**/\r
#define MSR_P6_TEST_CTL 0x00000033\r
\r
Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG);\r
AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr);\r
@endcode\r
+ @note MSR_P6_BIOS_UPDT_TRIG is defined as BIOS_UPDT_TRIG in SDM.\r
**/\r
#define MSR_P6_BIOS_UPDT_TRIG 0x00000079\r
\r
Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);\r
AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);\r
@endcode\r
+ @note MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM.\r
+ MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM.\r
+ MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM.\r
@{\r
**/\r
#define MSR_P6_BBL_CR_D0 0x00000088\r
Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN);\r
AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr);\r
@endcode\r
+ @note MSR_P6_BIOS_SIGN is defined as BIOS_SIGN in SDM.\r
**/\r
#define MSR_P6_BIOS_SIGN 0x0000008B\r
\r
Msr = AsmReadMsr64 (MSR_P6_PERFCTR0);\r
AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr);\r
@endcode\r
+ @note MSR_P6_PERFCTR0 is defined as PERFCTR0 in SDM.\r
+ MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM.\r
@{\r
**/\r
#define MSR_P6_PERFCTR0 0x000000C1\r
Msr = AsmReadMsr64 (MSR_P6_MTRRCAP);\r
AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr);\r
@endcode\r
+ @note MSR_P6_MTRRCAP is defined as MTRRCAP in SDM.\r
**/\r
#define MSR_P6_MTRRCAP 0x000000FE\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR);\r
AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64);\r
@endcode\r
+ @note MSR_P6_BBL_CR_ADDR is defined as BBL_CR_ADDR in SDM.\r
**/\r
#define MSR_P6_BBL_CR_ADDR 0x00000116\r
\r
Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC);\r
AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr);\r
@endcode\r
+ @note MSR_P6_BBL_CR_DECC is defined as BBL_CR_DECC in SDM.\r
**/\r
#define MSR_P6_BBL_CR_DECC 0x00000118\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL);\r
AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64);\r
@endcode\r
+ @note MSR_P6_BBL_CR_CTL is defined as BBL_CR_CTL in SDM.\r
**/\r
#define MSR_P6_BBL_CR_CTL 0x00000119\r
\r
Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG);\r
AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr);\r
@endcode\r
+ @note MSR_P6_BBL_CR_TRIG is defined as BBL_CR_TRIG in SDM.\r
**/\r
#define MSR_P6_BBL_CR_TRIG 0x0000011A\r
\r
Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY);\r
AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr);\r
@endcode\r
+ @note MSR_P6_BBL_CR_BUSY is defined as BBL_CR_BUSY in SDM.\r
**/\r
#define MSR_P6_BBL_CR_BUSY 0x0000011B\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3);\r
AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64);\r
@endcode\r
+ @note MSR_P6_BBL_CR_CTL3 is defined as BBL_CR_CTL3 in SDM.\r
**/\r
#define MSR_P6_BBL_CR_CTL3 0x0000011E\r
\r
Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR);\r
AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr);\r
@endcode\r
+ @note MSR_P6_SYSENTER_CS_MSR is defined as SYSENTER_CS_MSR in SDM.\r
**/\r
#define MSR_P6_SYSENTER_CS_MSR 0x00000174\r
\r
Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR);\r
AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr);\r
@endcode\r
+ @note MSR_P6_SYSENTER_ESP_MSR is defined as SYSENTER_ESP_MSR in SDM.\r
**/\r
#define MSR_P6_SYSENTER_ESP_MSR 0x00000175\r
\r
Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR);\r
AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr);\r
@endcode\r
+ @note MSR_P6_SYSENTER_EIP_MSR is defined as SYSENTER_EIP_MSR in SDM.\r
**/\r
#define MSR_P6_SYSENTER_EIP_MSR 0x00000176\r
\r
Msr = AsmReadMsr64 (MSR_P6_MCG_CAP);\r
AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr);\r
@endcode\r
+ @note MSR_P6_MCG_CAP is defined as MCG_CAP in SDM.\r
**/\r
#define MSR_P6_MCG_CAP 0x00000179\r
\r
Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS);\r
AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr);\r
@endcode\r
+ @note MSR_P6_MCG_STATUS is defined as MCG_STATUS in SDM.\r
**/\r
#define MSR_P6_MCG_STATUS 0x0000017A\r
\r
Msr = AsmReadMsr64 (MSR_P6_MCG_CTL);\r
AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr);\r
@endcode\r
+ @note MSR_P6_MCG_CTL is defined as MCG_CTL in SDM.\r
**/\r
#define MSR_P6_MCG_CTL 0x0000017B\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0);\r
AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64);\r
@endcode\r
+ @note MSR_P6_PERFEVTSEL0 is defined as PERFEVTSEL0 in SDM.\r
+ MSR_P6_PERFEVTSEL1 is defined as PERFEVTSEL1 in SDM.\r
@{\r
**/\r
#define MSR_P6_PERFEVTSEL0 0x00000186\r
Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR);\r
AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64);\r
@endcode\r
+ @note MSR_P6_DEBUGCTLMSR is defined as DEBUGCTLMSR in SDM.\r
**/\r
#define MSR_P6_DEBUGCTLMSR 0x000001D9\r
\r
Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP);\r
AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr);\r
@endcode\r
+ @note MSR_P6_LASTBRANCHFROMIP is defined as LASTBRANCHFROMIP in SDM.\r
**/\r
#define MSR_P6_LASTBRANCHFROMIP 0x000001DB\r
\r
Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP);\r
AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr);\r
@endcode\r
+ @note MSR_P6_LASTBRANCHTOIP is defined as LASTBRANCHTOIP in SDM.\r
**/\r
#define MSR_P6_LASTBRANCHTOIP 0x000001DC\r
\r
Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP);\r
AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr);\r
@endcode\r
+ @note MSR_P6_LASTINTFROMIP is defined as LASTINTFROMIP in SDM.\r
**/\r
#define MSR_P6_LASTINTFROMIP 0x000001DD\r
\r
Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP);\r
AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr);\r
@endcode\r
+ @note MSR_P6_LASTINTTOIP is defined as LASTINTTOIP in SDM.\r
**/\r
#define MSR_P6_LASTINTTOIP 0x000001DE\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6);\r
AsmWriteMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6, Msr.Uint64);\r
@endcode\r
+ @note MSR_P6_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM.\r
**/\r
#define MSR_P6_ROB_CR_BKUPTMPDR6 0x000001E0\r
\r
Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);\r
AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);\r
@endcode\r
+ @note MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.\r
+ MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.\r
+ MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.\r
+ MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.\r
+ MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.\r
+ MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.\r
+ MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.\r
+ MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.\r
@{\r
**/\r
#define MSR_P6_MTRRPHYSBASE0 0x00000200\r
Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);\r
AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);\r
@endcode\r
+ @note MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.\r
+ MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.\r
+ MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.\r
+ MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.\r
+ MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.\r
+ MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.\r
+ MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.\r
+ MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.\r
@{\r
**/\r
#define MSR_P6_MTRRPHYSMASK0 0x00000201\r
Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000);\r
AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr);\r
@endcode\r
+ @note MSR_P6_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.\r
**/\r
#define MSR_P6_MTRRFIX64K_00000 0x00000250\r
\r
Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000);\r
AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr);\r
@endcode\r
+ @note MSR_P6_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.\r
**/\r
#define MSR_P6_MTRRFIX16K_80000 0x00000258\r
\r
Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000);\r
AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr);\r
@endcode\r
+ @note MSR_P6_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.\r
**/\r
#define MSR_P6_MTRRFIX16K_A0000 0x00000259\r
\r
Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000);\r
AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr);\r
@endcode\r
+ @note MSR_P6_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.\r
**/\r
#define MSR_P6_MTRRFIX4K_C0000 0x00000268\r
\r
Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000);\r
AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr);\r
@endcode\r
+ @note MSR_P6_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.\r
**/\r
#define MSR_P6_MTRRFIX4K_C8000 0x00000269\r
\r
Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000);\r
AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr);\r
@endcode\r
+ @note MSR_P6_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.\r
**/\r
#define MSR_P6_MTRRFIX4K_D0000 0x0000026A\r
\r
Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000);\r
AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr);\r
@endcode\r
+ @note MSR_P6_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.\r
**/\r
#define MSR_P6_MTRRFIX4K_D8000 0x0000026B\r
\r
Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000);\r
AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr);\r
@endcode\r
+ @note MSR_P6_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.\r
**/\r
#define MSR_P6_MTRRFIX4K_E0000 0x0000026C\r
\r
Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000);\r
AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr);\r
@endcode\r
+ @note MSR_P6_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.\r
**/\r
#define MSR_P6_MTRRFIX4K_E8000 0x0000026D\r
\r
Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000);\r
AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr);\r
@endcode\r
+ @note MSR_P6_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.\r
**/\r
#define MSR_P6_MTRRFIX4K_F0000 0x0000026E\r
\r
Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000);\r
AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr);\r
@endcode\r
+ @note MSR_P6_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.\r
**/\r
#define MSR_P6_MTRRFIX4K_F8000 0x0000026F\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE);\r
AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64);\r
@endcode\r
+ @note MSR_P6_MTRRDEFTYPE is defined as MTRRDEFTYPE in SDM.\r
**/\r
#define MSR_P6_MTRRDEFTYPE 0x000002FF\r
\r
Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);\r
AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);\r
@endcode\r
+ @note MSR_P6_MC0_CTL is defined as MC0_CTL in SDM.\r
+ MSR_P6_MC1_CTL is defined as MC1_CTL in SDM.\r
+ MSR_P6_MC2_CTL is defined as MC2_CTL in SDM.\r
+ MSR_P6_MC3_CTL is defined as MC3_CTL in SDM.\r
+ MSR_P6_MC4_CTL is defined as MC4_CTL in SDM.\r
@{\r
**/\r
#define MSR_P6_MC0_CTL 0x00000400\r
Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);\r
AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);\r
@endcode\r
+ @note MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM.\r
+ MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM.\r
+ MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM.\r
+ MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM.\r
+ MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM.\r
@{\r
**/\r
#define MSR_P6_MC0_STATUS 0x00000401\r
Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);\r
AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);\r
@endcode\r
+ @note MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM.\r
+ MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM.\r
+ MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM.\r
+ MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM.\r
+ MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM.\r
@{\r
**/\r
#define MSR_P6_MC0_ADDR 0x00000402\r
Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);\r
AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);\r
@endcode\r
+ @note MSR_P6_MC0_MISC is defined as MC0_MISC in SDM.\r
+ MSR_P6_MC1_MISC is defined as MC1_MISC in SDM.\r
+ MSR_P6_MC2_MISC is defined as MC2_MISC in SDM.\r
+ MSR_P6_MC3_MISC is defined as MC3_MISC in SDM.\r
+ MSR_P6_MC4_MISC is defined as MC4_MISC in SDM.\r
@{\r
**/\r
#define MSR_P6_MC0_MISC 0x00000403\r