ArmPkg/ArmGicLib: Added function ArmGicSetSecureInterrupts() to define the secure...

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13122 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
index 57ae14150e7e4734d2bb455d2b71acd8b9f32f7c..4f10e4e5129ded2c4aad6bf40be238404e15e476 100644 (file)
--- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
@@ -12,7 +12,8 @@
 *\r
 **/\r
 \r
-#include <Uefi.h>\r
+#include <Base.h>\r
+#include <Library/DebugLib.h>\r
 #include <Library/IoLib.h>\r
 #include <Library/ArmGicLib.h>\r
 \r
@@ -29,6 +30,7 @@ ArmGicSetupNonSecure (
 {\r
   UINTN InterruptId;\r
   UINTN CachedPriorityMask;\r
+  UINTN Index;\r
 \r
   CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);\r
 \r
@@ -46,14 +48,39 @@ ArmGicSetupNonSecure (
   }\r
 \r
   // Ensure all GIC interrupts are Non-Secure\r
-  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);     // IRQs  0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]\r
-  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt\r
-  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)\r
+  for (Index = 0; Index < (PcdGet32(PcdGicNumInterrupts) / 32); Index++) {\r
+    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
+  }\r
 \r
   // Ensure all interrupts can get through the priority mask\r
   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);\r
 }\r
 \r
+/*\r
+ * This function configures the interrupts set by the mask to be secure.\r
+ *\r
+ */\r
+VOID\r
+EFIAPI\r
+ArmGicSetSecureInterrupts (\r
+  IN  UINTN         GicDistributorBase,\r
+  IN  UINTN*        GicSecureInterruptMask,\r
+  IN  UINTN         GicSecureInterruptMaskSize\r
+  )\r
+{\r
+  UINTN  Index;\r
+  UINT32 InterruptStatus;\r
+\r
+  // We must not have more interrupts defined by the mask than the number of available interrupts\r
+  ASSERT(GicSecureInterruptMaskSize <= (PcdGet32(PcdGicNumInterrupts) / 32));\r
+\r
+  // Set all the interrupts defined by the mask as Secure\r
+  for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {\r
+    InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));\r
+    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));\r
+  }\r
+}\r
+\r
 VOID\r
 EFIAPI\r
 ArmGicEnableInterruptInterface (\r

diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf b/ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
index fdec5c68d3b327ba316eb4d3dead45a90ea7acc0..cf575e4cf2ab411865f49efc14e46187686f93a0 100644 (file)
--- a/ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
@@ -26,3 +26,12 @@
 [Packages]\r
   ArmPkg/ArmPkg.dec\r
   MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+  DebugLib\r
+  IoLib\r
+  PcdLib\r
+\r
+[FixedPcd.common]\r
+  gArmTokenSpaceGuid.PcdGicNumInterrupts\r
+  \r

diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h
index 78bba23ba70e087985377a94f52c522257f254b7..66e12dad59f631af97a4b89b0f88ef5aaf07cc82 100644 (file)
--- a/ArmPkg/Include/Library/ArmGicLib.h
+++ b/ArmPkg/Include/Library/ArmGicLib.h
@@ -72,7 +72,7 @@
 \r
 \r
 //\r
-// GIC SEC interfaces\r
+// GIC Secure interfaces\r
 //\r
 VOID\r
 EFIAPI\r
@@ -81,6 +81,14 @@ ArmGicSetupNonSecure (
   IN  INTN          GicInterruptInterfaceBase\r
   );\r
 \r
+VOID\r
+EFIAPI\r
+ArmGicSetSecureInterrupts (\r
+  IN  UINTN         GicDistributorBase,\r
+  IN  UINTN*        GicSecureInterruptMask,\r
+  IN  UINTN         GicSecureInterruptMaskSize\r
+  );\r
+\r
 VOID\r
 EFIAPI\r
 ArmGicEnableInterruptInterface (\r