ArmPlatformPkg/PL180MciDxe: Fixed coding style

Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13586 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c b/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c
index b79845dccb713bfcd480d96b41d867e32188891f..313f2af9fdc568b083e7346a694370c74ed900a9 100644 (file)
--- a/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c
+++ b/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c
@@ -1,7 +1,7 @@
 /** @file\r
   This file implement the MMC Host Protocol for the ARM PrimeCell PL180.\r
 \r
-  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
   \r
   This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
@@ -27,12 +27,15 @@ EFI_MMC_HOST_PROTOCOL     *gpMmcHost;
 #define MMCI0_POW2_BLOCKLEN     9\r
 #define MMCI0_TIMEOUT           1000\r
 \r
+#define SYS_MCI_CARDIN          BIT0\r
+#define SYS_MCI_WPROT           BIT1\r
+\r
 BOOLEAN\r
 MciIsPowerOn (\r
   VOID\r
   )\r
 {\r
-  return ((MmioRead32(MCI_POWER_CONTROL_REG) & 0x3) == MCI_POWER_ON);\r
+  return ((MmioRead32 (MCI_POWER_CONTROL_REG) & MCI_POWER_ON) == MCI_POWER_ON);\r
 }\r
 \r
 EFI_STATUS\r
@@ -40,7 +43,7 @@ MciInitialize (
   VOID\r
   )\r
 {\r
-  MCI_TRACE("MciInitialize()");\r
+  MCI_TRACE ("MciInitialize()");\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -49,7 +52,7 @@ MciIsCardPresent (
   IN EFI_MMC_HOST_PROTOCOL     *This\r
   )\r
 {\r
-  return (MmioRead32(FixedPcdGet32(PcdPL180SysMciRegAddress)) & 1);\r
+  return (MmioRead32 (FixedPcdGet32 (PcdPL180SysMciRegAddress)) & SYS_MCI_CARDIN);\r
 }\r
 \r
 BOOLEAN\r
@@ -57,7 +60,7 @@ MciIsReadOnly (
   IN EFI_MMC_HOST_PROTOCOL     *This\r
   )\r
 {\r
-  return (MmioRead32(FixedPcdGet32(PcdPL180SysMciRegAddress)) & 2);\r
+  return (MmioRead32 (FixedPcdGet32 (PcdPL180SysMciRegAddress)) & SYS_MCI_WPROT);\r
 }\r
 \r
 #if 0\r
@@ -92,13 +95,13 @@ MciPrepareDataPath (
   )\r
 {\r
   // Set Data Length & Data Timer\r
-  MmioWrite32 (MCI_DATA_TIMER_REG,0xFFFFFFF);\r
-  MmioWrite32 (MCI_DATA_LENGTH_REG,MMCI0_BLOCKLEN);\r
+  MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF);\r
+  MmioWrite32 (MCI_DATA_LENGTH_REG, MMCI0_BLOCKLEN);\r
 \r
 #ifndef USE_STREAM\r
-  //Note: we are using a hardcoded BlockLen (=512). If we decide to use a variable size, we could\r
-  // compute the pow2 of BlockLen with the above function GetPow2BlockLen()\r
-  MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE |  MCI_DATACTL_DMA_ENABLE | TransferDirection | (MMCI0_POW2_BLOCKLEN << 4));\r
+  //Note: we are using a hardcoded BlockLen (==512). If we decide to use a variable size, we could\r
+  // compute the pow2 of BlockLen with the above function GetPow2BlockLen ()\r
+  MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | (MMCI0_POW2_BLOCKLEN << 4));\r
 #else\r
   MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | MCI_DATACTL_STREAM_TRANS);\r
 #endif\r
@@ -111,21 +114,21 @@ MciSendCommand (
   IN UINT32                     Argument\r
   )\r
 {\r
-  UINT32 Status;\r
-  UINT32 Cmd;\r
-  UINTN  RetVal;\r
-  UINTN  CmdCtrlReg;\r
+  UINT32  Status;\r
+  UINT32  Cmd;\r
+  UINTN   RetVal;\r
+  UINTN   CmdCtrlReg;\r
 \r
   RetVal = EFI_SUCCESS;\r
 \r
   if ((MmcCmd == MMC_CMD17) || (MmcCmd == MMC_CMD11)) {\r
-    MciPrepareDataPath(MCI_DATACTL_CARD_TO_CONT);\r
+    MciPrepareDataPath (MCI_DATACTL_CARD_TO_CONT);\r
   } else if ((MmcCmd == MMC_CMD24) || (MmcCmd == MMC_CMD20)) {\r
-    MciPrepareDataPath(MCI_DATACTL_CONT_TO_CARD);\r
+    MciPrepareDataPath (MCI_DATACTL_CONT_TO_CARD);\r
   }\r
 \r
   // Create Command for PL180\r
-  Cmd = (MMC_GET_INDX(MmcCmd) & INDX_MASK)  | MCI_CPSM_ENABLED;\r
+  Cmd = (MMC_GET_INDX (MmcCmd) & INDX_MASK)  | MCI_CPSM_ENABLE;\r
   if (MmcCmd & MMC_CMD_WAIT_RESPONSE) {\r
     Cmd |= MCI_CPSM_WAIT_RESPONSE;\r
   }\r
@@ -135,29 +138,29 @@ MciSendCommand (
   }\r
 \r
   // Clear Status register static flags\r
-  MmioWrite32(MCI_CLEAR_STATUS_REG,0x7FF);\r
+  MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS);\r
 \r
-  //Write to command argument register\r
-  MmioWrite32(MCI_ARGUMENT_REG,Argument);\r
+  // Write to command argument register\r
+  MmioWrite32 (MCI_ARGUMENT_REG, Argument);\r
 \r
-  //Write to command register\r
-  MmioWrite32(MCI_COMMAND_REG,Cmd);\r
+  // Write to command register\r
+  MmioWrite32 (MCI_COMMAND_REG, Cmd);\r
 \r
   if (Cmd & MCI_CPSM_WAIT_RESPONSE) {\r
-    Status = MmioRead32(MCI_STATUS_REG);\r
+    Status = MmioRead32 (MCI_STATUS_REG);\r
     while (!(Status & (MCI_STATUS_CMD_RESPEND | MCI_STATUS_CMD_CMDCRCFAIL | MCI_STATUS_CMD_CMDTIMEOUT | MCI_STATUS_CMD_START_BIT_ERROR))) {\r
       Status = MmioRead32(MCI_STATUS_REG);\r
     }\r
 \r
     if ((Status & MCI_STATUS_CMD_START_BIT_ERROR)) {\r
-      DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status));\r
+      DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n", (Cmd & 0x3F), MmioRead32 (MCI_RESPONSE0_REG), Status));\r
       RetVal = EFI_NO_RESPONSE;\r
       goto Exit;\r
     } else if ((Status & MCI_STATUS_CMD_CMDTIMEOUT)) {\r
-      //DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status));\r
+      //DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n", (Cmd & 0x3F), MmioRead32 (MCI_RESPONSE0_REG), Status));\r
       RetVal = EFI_TIMEOUT;\r
       goto Exit;\r
-    } else if ((!(MmcCmd & MMC_CMD_NO_CRC_RESPONSE)) && (Status & MCI_STATUS_CMD_CMDCRCFAIL)) {\r
+    } else if ((! (MmcCmd & MMC_CMD_NO_CRC_RESPONSE)) && (Status & MCI_STATUS_CMD_CMDCRCFAIL)) {\r
       // The CMD1 and response type R3 do not contain CRC. We should ignore the CRC failed Status.\r
       RetVal = EFI_CRC_ERROR;\r
       goto Exit;\r
@@ -191,10 +194,10 @@ MciSendCommand (
   }\r
 \r
 Exit:\r
-       // Disable Command Path\r
-       CmdCtrlReg = MmioRead32(MCI_COMMAND_REG);\r
-       MmioWrite32(MCI_COMMAND_REG, (CmdCtrlReg & ~MCI_CPSM_ENABLED));\r
-       return RetVal;\r
+  // Disable Command Path\r
+  CmdCtrlReg = MmioRead32 (MCI_COMMAND_REG);\r
+  MmioWrite32 (MCI_COMMAND_REG, (CmdCtrlReg & ~MCI_CPSM_ENABLE));\r
+  return RetVal;\r
 }\r
 \r
 EFI_STATUS\r
@@ -208,16 +211,18 @@ MciReceiveResponse (
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
-  if ((Type == MMC_RESPONSE_TYPE_R1) || (Type == MMC_RESPONSE_TYPE_R1b) ||\r
-      (Type == MMC_RESPONSE_TYPE_R3) || (Type == MMC_RESPONSE_TYPE_R6) ||\r
-      (Type == MMC_RESPONSE_TYPE_R7))\r
+  if (   (Type == MMC_RESPONSE_TYPE_R1)\r
+      || (Type == MMC_RESPONSE_TYPE_R1b)\r
+      || (Type == MMC_RESPONSE_TYPE_R3)\r
+      || (Type == MMC_RESPONSE_TYPE_R6)\r
+      || (Type == MMC_RESPONSE_TYPE_R7))\r
   {\r
-    Buffer[0] = MmioRead32(MCI_RESPONSE3_REG);\r
+    Buffer[0] = MmioRead32 (MCI_RESPONSE3_REG);\r
   } else if (Type == MMC_RESPONSE_TYPE_R2) {\r
-    Buffer[0] = MmioRead32(MCI_RESPONSE0_REG);\r
-    Buffer[1] = MmioRead32(MCI_RESPONSE1_REG);\r
-    Buffer[2] = MmioRead32(MCI_RESPONSE2_REG);\r
-    Buffer[3] = MmioRead32(MCI_RESPONSE3_REG);\r
+    Buffer[0] = MmioRead32 (MCI_RESPONSE0_REG);\r
+    Buffer[1] = MmioRead32 (MCI_RESPONSE1_REG);\r
+    Buffer[2] = MmioRead32 (MCI_RESPONSE2_REG);\r
+    Buffer[3] = MmioRead32 (MCI_RESPONSE3_REG);\r
   }\r
 \r
   return EFI_SUCCESS;\r
@@ -244,7 +249,7 @@ MciReadBlockData (
   Finish = MMCI0_BLOCKLEN / 4;\r
   do {\r
     // Read the Status flags\r
-    Status = MmioRead32(MCI_STATUS_REG);\r
+    Status = MmioRead32 (MCI_STATUS_REG);\r
 \r
     // Do eight reads if possible else a single read\r
     if (Status & MCI_STATUS_CMD_RXFIFOHALFFULL) {\r
@@ -269,16 +274,16 @@ MciReadBlockData (
       Loop++;\r
     } else {\r
       //Check for error conditions and timeouts\r
-      if(Status & MCI_STATUS_CMD_DATATIMEOUT) {\r
-        DEBUG ((EFI_D_ERROR, "MciReadBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));\r
+      if (Status & MCI_STATUS_CMD_DATATIMEOUT) {\r
+        DEBUG ((EFI_D_ERROR, "MciReadBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));\r
         RetVal = EFI_TIMEOUT;\r
         break;\r
-      } else if(Status & MCI_STATUS_CMD_DATACRCFAIL) {\r
-        DEBUG ((EFI_D_ERROR, "MciReadBlockData(): CRC Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));\r
+      } else if (Status & MCI_STATUS_CMD_DATACRCFAIL) {\r
+        DEBUG ((EFI_D_ERROR, "MciReadBlockData(): CRC Error! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));\r
         RetVal = EFI_CRC_ERROR;\r
         break;\r
-      } else if(Status & MCI_STATUS_CMD_START_BIT_ERROR) {\r
-        DEBUG ((EFI_D_ERROR, "MciReadBlockData(): Start-bit Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));\r
+      } else if (Status & MCI_STATUS_CMD_START_BIT_ERROR) {\r
+        DEBUG ((EFI_D_ERROR, "MciReadBlockData(): Start-bit Error! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));\r
         RetVal = EFI_NO_RESPONSE;\r
         break;\r
       }\r
@@ -289,14 +294,14 @@ MciReadBlockData (
     }\r
   } while ((Loop < Finish));\r
 \r
-       //Clear Status flags\r
-       MmioWrite32(MCI_CLEAR_STATUS_REG, 0x7FF);\r
+  // Clear Status flags\r
+  MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS);\r
 \r
-       //Disable Data path\r
-       DataCtrlReg = MmioRead32(MCI_DATA_CTL_REG);\r
-       MmioWrite32(MCI_DATA_CTL_REG, (DataCtrlReg & 0xFE));\r
+  //Disable Data path\r
+  DataCtrlReg = MmioRead32 (MCI_DATA_CTL_REG);\r
+  MmioWrite32 (MCI_DATA_CTL_REG, (DataCtrlReg & MCI_DATACTL_DISABLE_MASK));\r
 \r
-       return RetVal;\r
+  return RetVal;\r
 }\r
 \r
 EFI_STATUS\r
@@ -322,7 +327,7 @@ MciWriteBlockData (
   Timer  = MMCI0_TIMEOUT * 100;\r
   do {\r
     // Read the Status flags\r
-    Status = MmioRead32(MCI_STATUS_REG);\r
+    Status = MmioRead32 (MCI_STATUS_REG);\r
 \r
     // Do eight writes if possible else a single write\r
     if (Status & MCI_STATUS_CMD_TXFIFOHALFEMPTY) {\r
@@ -346,16 +351,16 @@ MciWriteBlockData (
         MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
         Loop++;\r
     } else {\r
-      //Check for error conditions and timeouts\r
-      if(Status & MCI_STATUS_CMD_DATATIMEOUT) {\r
-        DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));\r
+      // Check for error conditions and timeouts\r
+      if (Status & MCI_STATUS_CMD_DATATIMEOUT) {\r
+        DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));\r
         RetVal = EFI_TIMEOUT;\r
         goto Exit;\r
-      } else if(Status & MCI_STATUS_CMD_DATACRCFAIL) {\r
-        DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): CRC Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));\r
+      } else if (Status & MCI_STATUS_CMD_DATACRCFAIL) {\r
+        DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): CRC Error! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));\r
         RetVal = EFI_CRC_ERROR;\r
         goto Exit;\r
-      } else if(Status & MCI_STATUS_CMD_TX_UNDERRUN) {\r
+      } else if (Status & MCI_STATUS_CMD_TX_UNDERRUN) {\r
         DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TX buffer Underrun! Response:0x%X Status:0x%x, Number of bytes written 0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status, Loop));\r
         RetVal = EFI_BUFFER_TOO_SMALL;\r
         ASSERT(0);\r
@@ -365,37 +370,37 @@ MciWriteBlockData (
   } while (Loop < Finish);\r
 \r
   // Wait for FIFO to drain\r
-  Timer = MMCI0_TIMEOUT * 60;\r
-  Status = MmioRead32(MCI_STATUS_REG);\r
+  Timer  = MMCI0_TIMEOUT * 60;\r
+  Status = MmioRead32 (MCI_STATUS_REG);\r
 #ifndef USE_STREAM\r
   // Single block\r
-  while (((Status & MCI_STATUS_CMD_TXDONE) != MCI_STATUS_CMD_TXDONE) && Timer) {\r
+  while (((Status & MCI_STATUS_TXDONE) != MCI_STATUS_TXDONE) && Timer) {\r
 #else\r
   // Stream\r
   while (((Status & MCI_STATUS_CMD_DATAEND) != MCI_STATUS_CMD_DATAEND) && Timer) {\r
 #endif\r
     NanoSecondDelay(10);\r
-    Status = MmioRead32(MCI_STATUS_REG);\r
+    Status = MmioRead32 (MCI_STATUS_REG);\r
     Timer--;\r
   }\r
 \r
-  if(Timer == 0) {\r
+  if (Timer == 0) {\r
     DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): Data End timeout Number of bytes written 0x%x\n",Loop));\r
-    ASSERT(Timer > 0);\r
+    ASSERT (Timer > 0);\r
     return EFI_TIMEOUT;\r
   }\r
 \r
-  //Clear Status flags\r
-  MmioWrite32(MCI_CLEAR_STATUS_REG, 0x7FF);\r
+  // Clear Status flags\r
+  MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS);\r
   if (Timer == 0) {\r
     RetVal = EFI_TIMEOUT;\r
   }\r
 \r
 Exit:\r
-       //Disable Data path\r
-       DataCtrlReg = MmioRead32(MCI_DATA_CTL_REG);\r
-       MmioWrite32(MCI_DATA_CTL_REG, (DataCtrlReg & 0xFE));\r
-       return RetVal;\r
+  // Disable Data path\r
+  DataCtrlReg = MmioRead32 (MCI_DATA_CTL_REG);\r
+  MmioWrite32 (MCI_DATA_CTL_REG, (DataCtrlReg & MCI_DATACTL_DISABLE_MASK));\r
+  return RetVal;\r
 }\r
 \r
 EFI_STATUS\r
@@ -406,59 +411,59 @@ MciNotifyState (
 {\r
   UINT32      Data32;\r
 \r
-  switch(State) {\r
+  switch (State) {\r
   case MmcInvalidState:\r
-    ASSERT(0);\r
+    ASSERT (0);\r
     break;\r
   case MmcHwInitializationState:\r
     // If device already turn on then restart it\r
-    Data32 = MmioRead32(MCI_POWER_CONTROL_REG);\r
+    Data32 = MmioRead32 (MCI_POWER_CONTROL_REG);\r
     if ((Data32 & 0x2) == MCI_POWER_UP) {\r
-      MCI_TRACE("MciNotifyState(MmcHwInitializationState): TurnOff MCI");\r
+      MCI_TRACE ("MciNotifyState(MmcHwInitializationState): TurnOff MCI");\r
 \r
       // Turn off\r
-      MmioWrite32(MCI_CLOCK_CONTROL_REG, 0);\r
-      MmioWrite32(MCI_POWER_CONTROL_REG, 0);\r
-      MicroSecondDelay(100);\r
+      MmioWrite32 (MCI_CLOCK_CONTROL_REG, 0);\r
+      MmioWrite32 (MCI_POWER_CONTROL_REG, 0);\r
+      MicroSecondDelay (100);\r
     }\r
 \r
-    MCI_TRACE("MciNotifyState(MmcHwInitializationState): TurnOn MCI");\r
+    MCI_TRACE ("MciNotifyState(MmcHwInitializationState): TurnOn MCI");\r
     // Setup clock\r
     //  - 0x1D = 29 => should be the clock divider to be less than 400kHz at MCLK = 24Mhz\r
-    MmioWrite32(MCI_CLOCK_CONTROL_REG,0x1D | MCI_CLOCK_ENABLE | MCI_CLOCK_POWERSAVE);\r
+    MmioWrite32 (MCI_CLOCK_CONTROL_REG, 0x1D | MCI_CLOCK_ENABLE | MCI_CLOCK_POWERSAVE);\r
     //MmioWrite32(MCI_CLOCK_CONTROL_REG,0x1D | MCI_CLOCK_ENABLE);\r
 \r
     // Set the voltage\r
-    MmioWrite32(MCI_POWER_CONTROL_REG,MCI_POWER_OPENDRAIN | (15<<2));\r
-    MmioWrite32(MCI_POWER_CONTROL_REG,MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_UP);\r
-    MicroSecondDelay(10);\r
-    MmioWrite32(MCI_POWER_CONTROL_REG,MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_ON);\r
-    MicroSecondDelay(100);\r
+    MmioWrite32 (MCI_POWER_CONTROL_REG, MCI_POWER_OPENDRAIN | (15<<2));\r
+    MmioWrite32 (MCI_POWER_CONTROL_REG, MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_UP);\r
+    MicroSecondDelay (10);\r
+    MmioWrite32 (MCI_POWER_CONTROL_REG, MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_ON);\r
+    MicroSecondDelay (100);\r
 \r
     // Set Data Length & Data Timer\r
-    MmioWrite32(MCI_DATA_TIMER_REG,0xFFFFF);\r
-    MmioWrite32(MCI_DATA_LENGTH_REG,8);\r
+    MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFF);\r
+    MmioWrite32 (MCI_DATA_LENGTH_REG, 8);\r
 \r
-    ASSERT((MmioRead32(MCI_POWER_CONTROL_REG) & 0x3) == MCI_POWER_ON);\r
+    ASSERT ((MmioRead32 (MCI_POWER_CONTROL_REG) & 0x3) == MCI_POWER_ON);\r
     break;\r
   case MmcIdleState:\r
-    MCI_TRACE("MciNotifyState(MmcIdleState)");\r
+    MCI_TRACE ("MciNotifyState(MmcIdleState)");\r
     break;\r
   case MmcReadyState:\r
-    MCI_TRACE("MciNotifyState(MmcReadyState)");\r
+    MCI_TRACE ("MciNotifyState(MmcReadyState)");\r
     break;\r
   case MmcIdentificationState:\r
-    MCI_TRACE("MciNotifyState(MmcIdentificationState)");\r
+    MCI_TRACE ("MciNotifyState (MmcIdentificationState)");\r
     break;\r
   case MmcStandByState:{\r
     volatile UINT32 PwrCtrlReg;\r
-    MCI_TRACE("MciNotifyState(MmcStandByState)");\r
+    MCI_TRACE ("MciNotifyState (MmcStandByState)");\r
 \r
     // Enable MCICMD push-pull drive\r
-    PwrCtrlReg = MmioRead32(MCI_POWER_CONTROL_REG);\r
+    PwrCtrlReg = MmioRead32 (MCI_POWER_CONTROL_REG);\r
     //Disable Open Drain output\r
-    PwrCtrlReg &=~(MCI_POWER_OPENDRAIN);\r
-    MmioWrite32(MCI_POWER_CONTROL_REG,PwrCtrlReg);\r
+    PwrCtrlReg &= ~ (MCI_POWER_OPENDRAIN);\r
+    MmioWrite32 (MCI_POWER_CONTROL_REG, PwrCtrlReg);\r
 \r
     // Set MMCI0 clock to 4MHz (24MHz may be possible with cache enabled)\r
     //\r
@@ -471,22 +476,22 @@ MciNotifyState (
     break;\r
   }\r
   case MmcTransferState:\r
-    //MCI_TRACE("MciNotifyState(MmcTransferState)");\r
+    //MCI_TRACE ("MciNotifyState(MmcTransferState)");\r
     break;\r
   case MmcSendingDataState:\r
-    MCI_TRACE("MciNotifyState(MmcSendingDataState)");\r
+    MCI_TRACE ("MciNotifyState(MmcSendingDataState)");\r
     break;\r
   case MmcReceiveDataState:\r
-    MCI_TRACE("MciNotifyState(MmcReceiveDataState)");\r
+    MCI_TRACE ("MciNotifyState(MmcReceiveDataState)");\r
     break;\r
   case MmcProgrammingState:\r
-    MCI_TRACE("MciNotifyState(MmcProgrammingState)");\r
+    MCI_TRACE ("MciNotifyState(MmcProgrammingState)");\r
     break;\r
   case MmcDisconnectState:\r
-    MCI_TRACE("MciNotifyState(MmcDisconnectState)");\r
+    MCI_TRACE ("MciNotifyState(MmcDisconnectState)");\r
     break;\r
   default:\r
-    ASSERT(0);\r
+    ASSERT (0);\r
   }\r
   return EFI_SUCCESS;\r
 }\r
@@ -501,8 +506,8 @@ MciBuildDevicePath (
 {\r
   EFI_DEVICE_PATH_PROTOCOL    *NewDevicePathNode;\r
 \r
-  NewDevicePathNode = CreateDeviceNode(HARDWARE_DEVICE_PATH,HW_VENDOR_DP,sizeof(VENDOR_DEVICE_PATH));\r
-  CopyGuid(&((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid,&mPL180MciDevicePathGuid);\r
+  NewDevicePathNode = CreateDeviceNode (HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH));\r
+  CopyGuid (& ((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid, &mPL180MciDevicePathGuid);\r
 \r
   *DevicePath = NewDevicePathNode;\r
   return EFI_SUCCESS;\r
@@ -527,9 +532,11 @@ PL180MciDxeInitialize (
   )\r
 {\r
   EFI_STATUS    Status;\r
-  EFI_HANDLE    Handle = NULL;\r
+  EFI_HANDLE    Handle;\r
+\r
+  Handle = NULL;\r
 \r
-  MCI_TRACE("PL180MciDxeInitialize()");\r
+  MCI_TRACE ("PL180MciDxeInitialize()");\r
 \r
   //Publish Component Name, BlockIO protocol interfaces\r
   Status = gBS->InstallMultipleProtocolInterfaces (\r

diff --git a/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.h b/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.h
index 43a92bf4d939bab201ef052191a2bb7007ae3575..63c567d4766dba6aeef2b7b008cb4e5d7f061566 100644 (file)
--- a/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.h
+++ b/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.h
@@ -1,7 +1,7 @@
 /** @file\r
   Header for the MMC Host Protocol implementation for the ARM PrimeCell PL180.\r
 \r
-  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
   \r
   This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
@@ -27,76 +27,108 @@
 #include <Library/TimerLib.h>\r
 #include <Library/PcdLib.h>\r
 \r
-#define PL180_MCI_DXE_VERSION   0x10\r
-\r
-#define MCI_SYSCTL  FixedPcdGet32(PcdPL180MciBaseAddress)\r
-\r
-#define MCI_POWER_CONTROL_REG           (MCI_SYSCTL+0x000)\r
-#define MCI_CLOCK_CONTROL_REG           (MCI_SYSCTL+0x004)\r
-#define MCI_ARGUMENT_REG                (MCI_SYSCTL+0x008)\r
-#define MCI_COMMAND_REG                 (MCI_SYSCTL+0x00C)\r
-#define MCI_RESPCMD_REG                 (MCI_SYSCTL+0x010)\r
-#define MCI_RESPONSE3_REG               (MCI_SYSCTL+0x014)\r
-#define MCI_RESPONSE2_REG               (MCI_SYSCTL+0x018)\r
-#define MCI_RESPONSE1_REG               (MCI_SYSCTL+0x01C)\r
-#define MCI_RESPONSE0_REG               (MCI_SYSCTL+0x020)\r
-#define MCI_DATA_TIMER_REG              (MCI_SYSCTL+0x024)\r
-#define MCI_DATA_LENGTH_REG             (MCI_SYSCTL+0x028)\r
-#define MCI_DATA_CTL_REG                (MCI_SYSCTL+0x02C)\r
-#define MCI_DATA_COUNTER                (MCI_SYSCTL+0x030)\r
-#define MCI_STATUS_REG                  (MCI_SYSCTL+0x034)\r
-#define MCI_CLEAR_STATUS_REG            (MCI_SYSCTL+0x038)\r
-#define MCI_INT0_MASK_REG               (MCI_SYSCTL+0x03C)\r
-#define MCI_INT1_MASK_REG               (MCI_SYSCTL+0x040)\r
-#define MCI_FIFOCOUNT_REG               (MCI_SYSCTL+0x048)\r
-#define MCI_FIFO_REG                    (MCI_SYSCTL+0x080)\r
-\r
-#define MCI_POWER_UP                    0x2\r
-#define MCI_POWER_ON                    0x3\r
-#define MCI_POWER_OPENDRAIN             (1 << 6)\r
-#define MCI_POWER_ROD                   (1 << 7)\r
-\r
-#define MCI_CLOCK_ENABLE                0x100\r
-#define MCI_CLOCK_POWERSAVE             0x200\r
-#define MCI_CLOCK_BYPASS                0x400\r
-\r
-#define MCI_STATUS_CMD_CMDCRCFAIL       0x1\r
-#define MCI_STATUS_CMD_DATACRCFAIL      0x2\r
-#define MCI_STATUS_CMD_CMDTIMEOUT       0x4\r
-#define MCI_STATUS_CMD_DATATIMEOUT      0x8\r
-#define MCI_STATUS_CMD_TX_UNDERRUN      0x10\r
-#define MCI_STATUS_CMD_RXOVERRUN        0x20\r
-#define MCI_STATUS_CMD_RESPEND          0x40\r
-#define MCI_STATUS_CMD_SENT             0x80\r
-#define MCI_STATUS_CMD_TXDONE           (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)\r
-#define MCI_STATUS_CMD_DATAEND          0x000100    // Command Status - Data end\r
-#define MCI_STATUS_CMD_START_BIT_ERROR  0x000200\r
-#define MCI_STATUS_CMD_DATABLOCKEND     0x000400    // Command Status - Data end\r
-#define MCI_STATUS_CMD_ACTIVE           0x800\r
-#define MCI_STATUS_CMD_RXACTIVE         (1 << 13)\r
-#define MCI_STATUS_CMD_RXFIFOHALFFULL   0x008000\r
-#define MCI_STATUS_CMD_RXFIFOEMPTY      0x080000\r
-#define MCI_STATUS_CMD_RXDATAAVAILBL    (1 << 21)\r
-#define MCI_STATUS_CMD_TXACTIVE         (1 << 12)\r
-#define MCI_STATUS_CMD_TXFIFOFULL       (1 << 16)\r
-#define MCI_STATUS_CMD_TXFIFOHALFEMPTY  (1 << 14)\r
-#define MCI_STATUS_CMD_TXFIFOEMPTY      (1 << 18)\r
-#define MCI_STATUS_CMD_TXDATAAVAILBL    (1 << 20)\r
-\r
-#define MCI_DATACTL_ENABLE              1\r
+#define PL180_MCI_DXE_VERSION           0x10\r
+\r
+#define MCI_SYSCTL  FixedPcdGet32 (PcdPL180MciBaseAddress)\r
+\r
+#define MCI_POWER_CONTROL_REG           (MCI_SYSCTL + 0x000)\r
+#define MCI_CLOCK_CONTROL_REG           (MCI_SYSCTL + 0x004)\r
+#define MCI_ARGUMENT_REG                (MCI_SYSCTL + 0x008)\r
+#define MCI_COMMAND_REG                 (MCI_SYSCTL + 0x00C)\r
+#define MCI_RESPCMD_REG                 (MCI_SYSCTL + 0x010)\r
+#define MCI_RESPONSE3_REG               (MCI_SYSCTL + 0x014)\r
+#define MCI_RESPONSE2_REG               (MCI_SYSCTL + 0x018)\r
+#define MCI_RESPONSE1_REG               (MCI_SYSCTL + 0x01C)\r
+#define MCI_RESPONSE0_REG               (MCI_SYSCTL + 0x020)\r
+#define MCI_DATA_TIMER_REG              (MCI_SYSCTL + 0x024)\r
+#define MCI_DATA_LENGTH_REG             (MCI_SYSCTL + 0x028)\r
+#define MCI_DATA_CTL_REG                (MCI_SYSCTL + 0x02C)\r
+#define MCI_DATA_COUNTER                (MCI_SYSCTL + 0x030)\r
+#define MCI_STATUS_REG                  (MCI_SYSCTL + 0x034)\r
+#define MCI_CLEAR_STATUS_REG            (MCI_SYSCTL + 0x038)\r
+#define MCI_INT0_MASK_REG               (MCI_SYSCTL + 0x03C)\r
+#define MCI_INT1_MASK_REG               (MCI_SYSCTL + 0x040)\r
+#define MCI_SELECT_REG                  (MCI_SYSCTL + 0x044)\r
+#define MCI_FIFOCOUNT_REG               (MCI_SYSCTL + 0x048)\r
+#define MCI_FIFO_REG                    (MCI_SYSCTL + 0x080)\r
+\r
+#define MCI_POWER_OFF                   0\r
+#define MCI_POWER_UP                    BIT1\r
+#define MCI_POWER_ON                    (BIT1 | BIT0)\r
+#define MCI_POWER_OPENDRAIN             BIT6\r
+#define MCI_POWER_ROD                   BIT7\r
+\r
+#define MCI_CLOCK_ENABLE                BIT8\r
+#define MCI_CLOCK_POWERSAVE             BIT9\r
+#define MCI_CLOCK_BYPASS                BIT10\r
+#define MCI_CLOCK_WIDEBUS               BIT11\r
+\r
+#define MCI_STATUS_CMD_CMDCRCFAIL       BIT0\r
+#define MCI_STATUS_CMD_DATACRCFAIL      BIT1\r
+#define MCI_STATUS_CMD_CMDTIMEOUT       BIT2\r
+#define MCI_STATUS_CMD_DATATIMEOUT      BIT3\r
+#define MCI_STATUS_CMD_TX_UNDERRUN      BIT4\r
+#define MCI_STATUS_CMD_RXOVERRUN        BIT5\r
+#define MCI_STATUS_CMD_RESPEND          BIT6\r
+#define MCI_STATUS_CMD_SENT             BIT7\r
+#define MCI_STATUS_CMD_DATAEND          BIT8\r
+#define MCI_STATUS_CMD_START_BIT_ERROR  BIT9\r
+#define MCI_STATUS_CMD_DATABLOCKEND     BIT10\r
+#define MCI_STATUS_CMD_ACTIVE           BIT11\r
+#define MCI_STATUS_CMD_TXACTIVE         BIT12\r
+#define MCI_STATUS_CMD_RXACTIVE         BIT13\r
+#define MCI_STATUS_CMD_TXFIFOHALFEMPTY  BIT14\r
+#define MCI_STATUS_CMD_RXFIFOHALFFULL   BIT15\r
+#define MCI_STATUS_CMD_TXFIFOFULL       BIT16\r
+#define MCI_STATUS_CMD_RXFIFOFULL       BIT17\r
+#define MCI_STATUS_CMD_TXFIFOEMPTY      BIT18\r
+#define MCI_STATUS_CMD_RXFIFOEMPTY      BIT19\r
+#define MCI_STATUS_CMD_TXDATAAVAILBL    BIT20\r
+#define MCI_STATUS_CMD_RXDATAAVAILBL    BIT21\r
+\r
+#define MCI_STATUS_TXDONE               (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)\r
+#define MCI_STATUS_RXDONE               (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)\r
+#define MCI_STATUS_READ_ERROR           (  MCI_STATUS_CMD_DATACRCFAIL     \\r
+                                         | MCI_STATUS_CMD_DATATIMEOUT     \\r
+                                         | MCI_STATUS_CMD_RXOVERRUN       \\r
+                                         | MCI_STATUS_CMD_START_BIT_ERROR )\r
+#define MCI_STATUS_WRITE_ERROR          (  MCI_STATUS_CMD_DATACRCFAIL \\r
+                                         | MCI_STATUS_CMD_DATATIMEOUT \\r
+                                         | MCI_STATUS_CMD_TX_UNDERRUN )\r
+#define MCI_STATUS_CMD_ERROR            (  MCI_STATUS_CMD_CMDCRCFAIL      \\r
+                                         | MCI_STATUS_CMD_CMDTIMEOUT      \\r
+                                         | MCI_STATUS_CMD_START_BIT_ERROR )\r
+\r
+#define MCI_CLR_CMD_STATUS              (  MCI_STATUS_CMD_RESPEND \\r
+                                         | MCI_STATUS_CMD_SENT    \\r
+                                         | MCI_STATUS_CMD_ERROR )\r
+\r
+#define MCI_CLR_READ_STATUS             (  MCI_STATUS_RXDONE     \\r
+                                         | MCI_STATUS_READ_ERROR )\r
+\r
+#define MCI_CLR_WRITE_STATUS            (  MCI_STATUS_TXDONE      \\r
+                                         | MCI_STATUS_WRITE_ERROR )\r
+\r
+#define MCI_CLR_ALL_STATUS              (BIT11 - 1)\r
+\r
+#define MCI_DATACTL_DISABLE_MASK        0xFE\r
+#define MCI_DATACTL_ENABLE              BIT0\r
 #define MCI_DATACTL_CONT_TO_CARD        0\r
-#define MCI_DATACTL_CARD_TO_CONT        2\r
+#define MCI_DATACTL_CARD_TO_CONT        BIT1\r
 #define MCI_DATACTL_BLOCK_TRANS         0\r
-#define MCI_DATACTL_STREAM_TRANS        4\r
-#define MCI_DATACTL_DMA_ENABLE          (1 << 3)\r
+#define MCI_DATACTL_STREAM_TRANS        BIT2\r
+#define MCI_DATACTL_DMA_DISABLED        0\r
+#define MCI_DATACTL_DMA_ENABLE          BIT3\r
 \r
 #define INDX_MASK                       0x3F\r
 \r
-#define MCI_CPSM_ENABLED                (1 << 10)\r
-#define MCI_CPSM_WAIT_RESPONSE          (1 << 6)\r
-#define MCI_CPSM_LONG_RESPONSE          (1 << 7)\r
+#define MCI_CPSM_WAIT_RESPONSE          BIT6\r
+#define MCI_CPSM_LONG_RESPONSE          BIT7\r
+#define MCI_CPSM_LONG_INTERRUPT         BIT8\r
+#define MCI_CPSM_LONG_PENDING           BIT9\r
+#define MCI_CPSM_ENABLE                 BIT10\r
 \r
-#define MCI_TRACE(txt)  DEBUG((EFI_D_BLKIO, "ARM_MCI: " txt "\n"))\r
+#define MCI_TRACE(txt)                  DEBUG ((EFI_D_BLKIO, "ARM_MCI: " txt "\n"))\r
 \r
 EFI_STATUS\r
 EFIAPI\r