--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLibV8.h>\r
+\r
+.text\r
+.align 3\r
+GCC_ASM_EXPORT (ArmMainIdCode)\r
+GCC_ASM_EXPORT (ArmCacheInfo)\r
+GCC_ASM_EXPORT (ArmGetInterruptState)\r
+GCC_ASM_EXPORT (ArmGetFiqState)\r
+GCC_ASM_EXPORT (ArmGetTTBR0BaseAddress)\r
+GCC_ASM_EXPORT (ArmSetTTBR0)\r
+GCC_ASM_EXPORT (ArmGetTCR)\r
+GCC_ASM_EXPORT (ArmSetTCR)\r
+GCC_ASM_EXPORT (ArmGetMAIR)\r
+GCC_ASM_EXPORT (ArmSetMAIR)\r
+GCC_ASM_EXPORT (ArmWriteCpacr)\r
+GCC_ASM_EXPORT (ArmWriteAuxCr)\r
+GCC_ASM_EXPORT (ArmReadAuxCr)\r
+GCC_ASM_EXPORT (ArmInvalidateTlb)\r
+GCC_ASM_EXPORT (ArmUpdateTranslationTableEntry)\r
+GCC_ASM_EXPORT (ArmWriteNsacr)\r
+GCC_ASM_EXPORT (ArmWriteScr)\r
+GCC_ASM_EXPORT (ArmWriteMVBar)\r
+GCC_ASM_EXPORT (ArmCallWFE)\r
+GCC_ASM_EXPORT (ArmCallSEV)\r
+\r
+#------------------------------------------------------------------------------\r
+\r
+.set DAIF_FIQ_BIT, (1 << 0)\r
+.set DAIF_IRQ_BIT, (1 << 1)\r
+\r
+ASM_PFX(ArmiMainIdCode):\r
+ mrs x0, midr_el1 // Read from Main ID Register (MIDR)\r
+ ret\r
+\r
+ASM_PFX(ArmCacheInfo):\r
+ mrs x0, ctr_el0 // Read from Cache Type Regiter (CTR)\r
+ ret\r
+\r
+ASM_PFX(ArmGetInterruptState):\r
+ mrs x0, daif\r
+ tst w0, #DAIF_IRQ_BIT // Check if IRQ is enabled. Enabled if 0.\r
+ mov w0, #0\r
+ mov w1, #1\r
+ csel w0, w1, w0, ne\r
+ ret\r
+\r
+ASM_PFX(ArmGetFiqState):\r
+ mrs x0, daif\r
+ tst w0, #DAIF_FIQ_BIT // Check if FIQ is enabled. Enabled if 0.\r
+ mov w0, #0\r
+ mov w1, #1\r
+ csel w0, w1, w0, ne\r
+ ret\r
+\r
+ASM_PFX(ArmWriteCpacr):\r
+ msr cpacr_el1, x0 // Coprocessor Access Control Reg (CPACR)\r
+ ret\r
+\r
+ASM_PFX(ArmWriteAuxCr):\r
+ EL1_OR_EL2(x1)\r
+1:msr actlr_el1, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
+ b 3f\r
+2:msr actlr_el2, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
+3:ret\r
+\r
+ASM_PFX(ArmReadAuxCr):\r
+ EL1_OR_EL2(x1)\r
+1:mrs x0, actlr_el1 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
+ b 3f\r
+2:mrs x0, actlr_el2 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
+3:ret\r
+\r
+ASM_PFX(ArmSetTTBR0):\r
+ EL1_OR_EL2_OR_EL3(x1)\r
+1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0)\r
+ b 4f\r
+2:msr ttbr0_el2, x0 // Translation Table Base Reg 0 (TTBR0)\r
+ b 4f\r
+3:msr ttbr0_el3, x0 // Translation Table Base Reg 0 (TTBR0)\r
+4:isb\r
+ ret\r
+\r
+ASM_PFX(ArmGetTTBR0BaseAddress):\r
+ EL1_OR_EL2(x1)\r
+1:mrs x0, ttbr0_el1\r
+ b 3f\r
+2:mrs x0, ttbr0_el2\r
+3:LoadConstantToReg(0xFFFFFFFFFFFF, x1) /* Look at bottom 48 bits */\r
+ and x0, x0, x1\r
+ isb\r
+ ret\r
+\r
+ASM_PFX(ArmGetTCR):\r
+ EL1_OR_EL2_OR_EL3(x1)\r
+1:mrs x0, tcr_el1\r
+ b 4f\r
+2:mrs x0, tcr_el2\r
+ b 4f\r
+3:mrs x0, tcr_el3\r
+4:isb\r
+ ret\r
+\r
+ASM_PFX(ArmSetTCR):\r
+ EL1_OR_EL2_OR_EL3(x1)\r
+1:msr tcr_el1, x0\r
+ b 4f\r
+2:msr tcr_el2, x0\r
+ b 4f\r
+3:msr tcr_el3, x0\r
+4:isb\r
+ ret\r
+\r
+ASM_PFX(ArmGetMAIR):\r
+ EL1_OR_EL2_OR_EL3(x1)\r
+1:mrs x0, mair_el1\r
+ b 4f\r
+2:mrs x0, mair_el2\r
+ b 4f\r
+3:mrs x0, mair_el3\r
+4:isb\r
+ ret\r
+\r
+ASM_PFX(ArmSetMAIR):\r
+ EL1_OR_EL2_OR_EL3(x1)\r
+1:msr mair_el1, x0\r
+ b 4f\r
+2:msr mair_el2, x0\r
+ b 4f\r
+3:msr mair_el3, x0\r
+4:isb\r
+ ret\r
+\r
+\r
+//\r
+//VOID\r
+//ArmUpdateTranslationTableEntry (\r
+// IN VOID *TranslationTableEntry // X0\r
+// IN VOID *MVA // X1\r
+// );\r
+ASM_PFX(ArmUpdateTranslationTableEntry):\r
+ dc civac, x0 // Clean and invalidate data line\r
+ dsb sy\r
+ EL1_OR_EL2_OR_EL3(x0)\r
+1: tlbi vaae1, x1 // TLB Invalidate VA , EL1\r
+ b 4f\r
+2: tlbi vae2, x1 // TLB Invalidate VA , EL2\r
+ b 4f\r
+3: tlbi vae3, x1 // TLB Invalidate VA , EL3\r
+4: dsb sy\r
+ isb\r
+ ret\r
+\r
+ASM_PFX(ArmInvalidateTlb):\r
+ EL1_OR_EL2_OR_EL3(x0)\r
+1: tlbi alle1\r
+ b 4f\r
+2: tlbi alle2\r
+ b 4f\r
+3: tlbi alle3\r
+4: dsb sy\r
+ isb\r
+ ret\r
+\r
+ASM_PFX(ArmWriteNsacr):\r
+ msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR)\r
+ ret // Non-Secure Access Control Reg (NSACR) in ARMv7\r
+\r
+ASM_PFX(ArmWriteScr):\r
+ msr scr_el3, x0 // Secure configuration register EL3\r
+ ret\r
+\r
+ASM_PFX(ArmWriteMVBar):\r
+ msr vbar_el3, x0 // Excpetion Vector Base address for Monitor on EL3\r
+ ret\r
+\r
+ASM_PFX(ArmCallWFE):\r
+ wfe\r
+ ret\r
+\r
+ASM_PFX(ArmCallSEV):\r
+ sev\r
+ ret\r
+\r
+dead:\r
+ b dead\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r