\r
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);\r
@endcode\r
+ @note MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
**/\r
#define MSR_SILVERMONT_PLATFORM_ID 0x00000017\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);\r
AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);\r
@endcode\r
+ @note MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
**/\r
#define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT);\r
@endcode\r
+ @note MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
**/\r
#define MSR_SILVERMONT_SMI_COUNT 0x00000034\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);\r
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);\r
@endcode\r
+ @note MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
@{\r
**/\r
#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);\r
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);\r
@endcode\r
+ @note MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
@{\r
**/\r
#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);\r
@endcode\r
+ @note MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
**/\r
#define MSR_SILVERMONT_FSB_FREQ 0x000000CD\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL);\r
AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
@endcode\r
+ @note MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE);\r
AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
@endcode\r
+ @note MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
**/\r
#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3);\r
AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64);\r
@endcode\r
+ @note MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
**/\r
#define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG);\r
AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64);\r
@endcode\r
+ @note MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
**/\r
#define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE);\r
AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64);\r
@endcode\r
+ @note MSR_SILVERMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
#define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET);\r
AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64);\r
@endcode\r
+ @note MSR_SILVERMONT_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
**/\r
#define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0);\r
AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr);\r
@endcode\r
+ @note MSR_SILVERMONT_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
**/\r
#define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1);\r
AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr);\r
@endcode\r
+ @note MSR_SILVERMONT_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
**/\r
#define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT);\r
AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64);\r
@endcode\r
+ @note MSR_SILVERMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
#define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS);\r
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr);\r
@endcode\r
+ @note MSR_SILVERMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
#define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9\r
\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP);\r
@endcode\r
+ @note MSR_SILVERMONT_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
#define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD\r
\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP);\r
@endcode\r
+ @note MSR_SILVERMONT_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
#define MSR_SILVERMONT_LER_TO_LIP 0x000001DE\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS);\r
AsmWriteMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS, Msr);\r
@endcode\r
+ @note MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.\r
**/\r
#define MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE);\r
AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64);\r
@endcode\r
+ @note MSR_SILVERMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
#define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY);\r
AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr);\r
@endcode\r
+ @note MSR_SILVERMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
**/\r
#define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY);\r
AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr);\r
@endcode\r
+ @note MSR_SILVERMONT_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
**/\r
#define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_CTL);\r
AsmWriteMsr64 (MSR_SILVERMONT_MC3_CTL, Msr);\r
@endcode\r
+ @note MSR_SILVERMONT_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
+ MSR_SILVERMONT_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
+ MSR_SILVERMONT_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
@{\r
**/\r
#define MSR_SILVERMONT_MC3_CTL 0x0000040C\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_STATUS);\r
AsmWriteMsr64 (MSR_SILVERMONT_MC3_STATUS, Msr);\r
@endcode\r
+ @note MSR_SILVERMONT_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
+ MSR_SILVERMONT_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
+ MSR_SILVERMONT_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
@{\r
**/\r
#define MSR_SILVERMONT_MC3_STATUS 0x0000040D\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_ADDR);\r
AsmWriteMsr64 (MSR_SILVERMONT_MC3_ADDR, Msr);\r
@endcode\r
+ @note MSR_SILVERMONT_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
+ MSR_SILVERMONT_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
+ MSR_SILVERMONT_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
@{\r
**/\r
#define MSR_SILVERMONT_MC3_ADDR 0x0000040E\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM);\r
@endcode\r
+ @note MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r
**/\r
#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC);\r
@endcode\r
+ @note MSR_SILVERMONT_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.\r
**/\r
#define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY);\r
AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr);\r
@endcode\r
+ @note MSR_SILVERMONT_CORE_C1_RESIDENCY is defined as MSR_CORE_C1_RESIDENCY in SDM.\r
**/\r
#define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT);\r
@endcode\r
+ @note MSR_SILVERMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
#define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT);\r
AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64);\r
@endcode\r
+ @note MSR_SILVERMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
**/\r
#define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610\r
\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS);\r
@endcode\r
+ @note MSR_SILVERMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611\r
\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS);\r
@endcode\r
+ @note MSR_SILVERMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG);\r
AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr);\r
@endcode\r
+ @note MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG is defined as MSR_CC6_DEMOTION_POLICY_CONFIG in SDM.\r
**/\r
#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG);\r
AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr);\r
@endcode\r
+ @note MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG is defined as MSR_MC6_DEMOTION_POLICY_CONFIG in SDM.\r
**/\r
#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669\r
\r
\r
Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER);\r
@endcode\r
+ @note MSR_SILVERMONT_MC6_RESIDENCY_COUNTER is defined as MSR_MC6_RESIDENCY_COUNTER in SDM.\r
**/\r
#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO);\r
@endcode\r
+ @note MSR_SILVERMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
**/\r
#define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT);\r
AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64);\r
@endcode\r
+ @note MSR_SILVERMONT_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r
**/\r
#define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638\r
\r