UINT64 Val\r
);\r
\r
+UINTN\r
+EFIAPI\r
+ArmGetPhysicalAddressBits (\r
+ VOID\r
+ );\r
+\r
#endif // __ARM_LIB__\r
3:msr sctlr_el3, x0\r
4:ret\r
\r
+ASM_FUNC(ArmGetPhysicalAddressBits)\r
+ mrs x0, id_aa64mmfr0_el1\r
+ adr x1, .LPARanges\r
+ and x0, x0, #0xf\r
+ ldrb w0, [x1, x0]\r
+ ret\r
+\r
+//\r
+// Bits 0..3 of the AA64MFR0_EL1 system register encode the size of the\r
+// physical address space support on this CPU:\r
+// 0 == 32 bits, 1 == 36 bits, etc etc\r
+// 7 and up are reserved\r
+//\r
+.LPARanges:\r
+ .byte 32, 36, 40, 42, 44, 48, 52, 0\r
+ .byte 0, 0, 0, 0, 0, 0, 0, 0\r
+\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
isb\r
bx lr\r
\r
+ASM_FUNC (ArmGetPhysicalAddressBits)\r
+ mrc p15, 0, r0, c0, c1, 4 // MMFR0\r
+ and r0, r0, #0xf // VMSA [3:0]\r
+ cmp r0, #5 // >= 5 implies LPAE support\r
+ movlt r0, #32 // 32 bits if no LPAE\r
+ movge r0, #40 // 40 bits if LPAE\r
+ bx lr\r
+\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
isb\r
bx lr\r
\r
+ RVCT_ASM_EXPORT ArmGetPhysicalAddressBits\r
+ mrc p15, 0, r0, c0, c1, 4 ; MMFR0\r
+ and r0, r0, #0xf ; VMSA [3:0]\r
+ cmp r0, #5 ; >= 5 implies LPAE support\r
+ movlt r0, #32 ; 32 bits if no LPAE\r
+ movge r0, #40 ; 40 bits if LPAE\r
+ bx lr\r
+\r
END\r