PcAtChipsetPkg: Enable timer interrupt through I/O APIC

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
Reviewed-by: Elvin Li <elvin.li@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15576 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c b/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
index b9bf080c74ea03b9b600887b9254137aef51888f..e23a2c83e4f6e4ab7f70434130e50eb7e3b4126b 100644 (file)
--- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
+++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
@@ -1,7 +1,7 @@
 /** @file\r
   Timer Architectural Protocol module using High Precesion Event Timer (HPET)\r
 \r
-  Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -594,6 +594,7 @@ TimerDriverSetTimerPeriod (
       // Program IOAPIC register with APIC ID of current BSP in case BSP has been switched\r
       //\r
       IoApicConfigureInterrupt (mTimerIrq, PcdGet8 (PcdHpetLocalApicVector), IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY, TRUE, FALSE);\r
+      IoApicEnableInterrupt (mTimerIrq, TRUE);\r
     }\r
 \r
     //\r