Introduce UefiCpuLib library class in UefiCpuPkg and add one instance of BaseUefiCpuL...
authorqhuang8 <qhuang8@6f19259b-4bc3-4df7-8a09-765794883524>
Wed, 25 Nov 2009 04:25:02 +0000 (04:25 +0000)
committerqhuang8 <qhuang8@6f19259b-4bc3-4df7-8a09-765794883524>
Wed, 25 Nov 2009 04:25:02 +0000 (04:25 +0000)
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9480 6f19259b-4bc3-4df7-8a09-765794883524

UefiCpuPkg/Include/Library/UefiCpuLib.h [new file with mode: 0644]
UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf [new file with mode: 0644]
UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S [new file with mode: 0644]
UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.asm [new file with mode: 0644]
UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.S [new file with mode: 0644]
UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.asm [new file with mode: 0644]
UefiCpuPkg/UefiCpuPkg.dec
UefiCpuPkg/UefiCpuPkg.dsc

diff --git a/UefiCpuPkg/Include/Library/UefiCpuLib.h b/UefiCpuPkg/Include/Library/UefiCpuLib.h
new file mode 100644 (file)
index 0000000..597c194
--- /dev/null
@@ -0,0 +1,38 @@
+/** @file\r
+  Public header file for UEFI CPU library class.\r
+\r
+  This library class defines some routines that are generic for IA32 family CPU\r
+  to be UEFI specification compliant.\r
+\r
+  Copyright (c) 2009, Intel Corporation\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __UEFI_CPU_LIB_H__\r
+#define __UEFI_CPU_LIB_H__\r
+\r
+\r
+\r
+/**\r
+  Initializes floating point units for requirement of UEFI specification.\r
+\r
+  This function initializes floating-point control word to 0x027F (all exceptions\r
+  masked,double-precision, round-to-nearest) and multimedia-extensions control word\r
+  (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r
+  for masked underflow).\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InitializeFloatingPointUnits (\r
+  VOID\r
+  );\r
+\r
+#endif\r
diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
new file mode 100644 (file)
index 0000000..cebb1b5
--- /dev/null
@@ -0,0 +1,44 @@
+#/** @file\r
+#  This library defines some routines that are generic for IA32 family CPU\r
+#  to be UEFI specification compliant.\r
+#\r
+#  Copyright (c) 2009, Intel Corporation. <BR>\r
+#  All rights reserved. This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution.  The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php\r
+#  \r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#  \r
+#**/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = BaseUefiCpuLib\r
+  FILE_GUID                      = 34C24FD7-7A90-45c2-89FD-946473D9CE98\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = UefiCpuLib \r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64\r
+#\r
+\r
+[Sources.IA32]\r
+  Ia32/InitializeFpu.asm\r
+  Ia32/InitializeFpu.S\r
+\r
+[Sources.X64]\r
+  X64/InitializeFpu.asm\r
+  X64/InitializeFpu.S\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  UefiCpuPkg/UefiCpuPkg.dec\r
+\r
+[LibraryClasses]\r
+  UefiCpuLib\r
+\r
diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S b/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S
new file mode 100644 (file)
index 0000000..c4a2f6f
--- /dev/null
@@ -0,0 +1,70 @@
+#------------------------------------------------------------------------------
+#*
+#*   Copyright 2009, Intel Corporation
+#*   All rights reserved. This program and the accompanying materials
+#*   are licensed and made available under the terms and conditions of the BSD License
+#*   which accompanies this distribution.  The full text of the license may be found at
+#*   http://opensource.org/licenses/bsd-license.php
+#*
+#*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#*
+#*
+#------------------------------------------------------------------------------
+
+
+
+#\r
+# Float control word initial value: \r
+# all exceptions masked, double-precision, round-to-nearest\r
+#\r
+ASM_PFX(mFpuControlWord): .word     0x027F\r
+#\r
+# Multimedia-extensions control word:\r
+# all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
+#\r
+ASM_PFX(mMmxControlWord): .long     0x01F80
+
+#
+# Initializes floating point units for requirement of UEFI specification.\r
+#\r
+# This function initializes floating-point control word to 0x027F (all exceptions\r
+# masked,double-precision, round-to-nearest) and multimedia-extensions control word\r
+# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r
+# for masked underflow).
+#
+ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
+ASM_PFX(InitializeFloatingPointUnits):
+    #\r
+    # Initialize floating point units\r
+    #\r
+    finit\r
+    fldcw   ASM_PFX(mFpuControlWord)\r
+    \r
+    #\r
+    # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
+    # whether the processor supports SSE instruction.\r
+    #\r
+    movl    $1,  %eax\r
+    cpuid\r
+    btl     $25, %edx\r
+    jnc     Done\r
+    
+    #
+    # Set OSFXSR bit 9 in CR4
+    #
+    movl    %cr4, %eax 
+    or      $200, %eax
+    movl    %eax, %cr4
+    
+    #\r
+    # The processor should support SSE instruction and we can use\r
+    # ldmxcsr instruction\r
+    #\r
+    ldmxcsr ASM_PFX(mMmxControlWord)
+
+Done:
+    ret
+
+#END
+
diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.asm b/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.asm
new file mode 100644 (file)
index 0000000..55244c7
--- /dev/null
@@ -0,0 +1,75 @@
+;------------------------------------------------------------------------------\r
+;*\r
+;*   Copyright 2009, Intel Corporation\r
+;*   All rights reserved. This program and the accompanying materials\r
+;*   are licensed and made available under the terms and conditions of the BSD License\r
+;*   which accompanies this distribution.  The full text of the license may be found at\r
+;*   http://opensource.org/licenses/bsd-license.php\r
+;*\r
+;*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+;*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;*\r
+;*    \r
+;------------------------------------------------------------------------------\r
+\r
+\r
+    .686\r
+    .model  flat,C\r
+    .const\r
+;\r
+; Float control word initial value: \r
+; all exceptions masked, double-precision, round-to-nearest\r
+;\r
+mFpuControlWord       DW      027Fh\r
+;\r
+; Multimedia-extensions control word:\r
+; all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
+;\r
+mMmxControlWord       DD      01F80h \r
+\r
+    .xmm\r
+    .code\r
+\r
+;
+; Initializes floating point units for requirement of UEFI specification.\r
+;\r
+; This function initializes floating-point control word to 0x027F (all exceptions\r
+; masked,double-precision, round-to-nearest) and multimedia-extensions control word\r
+; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r
+; for masked underflow).
+;\r
+InitializeFloatingPointUnits PROC PUBLIC\r
+    ;\r
+    ; Initialize floating point units\r
+    ;\r
+    finit\r
+    fldcw   mFpuControlWord\r
+    \r
+    ;\r
+    ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
+    ; whether the processor supports SSE instruction.\r
+    ;\r
+    mov     eax, 1\r
+    cpuid\r
+    bt      edx, 25\r
+    jnc     Done\r
+    \r
+    ;\r
+    ; Set OSFXSR bit 9 in CR4\r
+    ;\r
+    mov     eax, cr4\r
+    or      eax, BIT9\r
+    mov     cr4, eax\r
+    \r
+    ;\r
+    ; The processor should support SSE instruction and we can use\r
+    ; ldmxcsr instruction\r
+    ;\r
+    ldmxcsr mMmxControlWord\r
+Done:\r
+\r
+    ret\r
+\r
+InitializeFloatingPointUnits ENDP\r
+\r
+END\r
diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.S b/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.S
new file mode 100644 (file)
index 0000000..3d1556d
--- /dev/null
@@ -0,0 +1,54 @@
+#------------------------------------------------------------------------------
+#*
+#*   Copyright 2009, Intel Corporation
+#*   All rights reserved. This program and the accompanying materials
+#*   are licensed and made available under the terms and conditions of the BSD License
+#*   which accompanies this distribution.  The full text of the license may be found at
+#*   http://opensource.org/licenses/bsd-license.php
+#*
+#*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#*
+#*
+#------------------------------------------------------------------------------
+
+
+#\r
+# Float control word initial value: \r
+# all exceptions masked, double-precision, round-to-nearest\r
+#\r
+ASM_PFX(mFpuControlWord): .word     0x027F\r
+#\r
+# Multimedia-extensions control word:\r
+# all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
+#\r
+ASM_PFX(mMmxControlWord): .long     0x01F80\r
+
+#
+# Initializes floating point units for requirement of UEFI specification.\r
+#\r
+# This function initializes floating-point control word to 0x027F (all exceptions\r
+# masked,double-precision, round-to-nearest) and multimedia-extensions control word\r
+# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r
+# for masked underflow).
+#
+ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
+ASM_PFX(InitializeFloatingPointUnits):
+
+    #\r
+    # Initialize floating point units\r
+    #\r
+    finit\r
+    fldcw   ASM_PFX(mFpuControlWord)\r
+    
+    #
+    # Set OSFXSR bit 9 in CR4
+    #
+    movq    %cr4, %rax 
+    or      $200, %rax
+    movq    %rax, %cr4
+    
+    ldmxcsr ASM_PFX(mMmxControlWord)
+    
+    ret
+
diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.asm b/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.asm
new file mode 100644 (file)
index 0000000..34c6de6
--- /dev/null
@@ -0,0 +1,59 @@
+;------------------------------------------------------------------------------\r
+;*\r
+;*   Copyright 2009, Intel Corporation\r
+;*   All rights reserved. This program and the accompanying materials\r
+;*   are licensed and made available under the terms and conditions of the BSD License\r
+;*   which accompanies this distribution.  The full text of the license may be found at\r
+;*   http://opensource.org/licenses/bsd-license.php\r
+;*\r
+;*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+;*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;*\r
+;*\r
+;------------------------------------------------------------------------------\r
+\r
+\r
+.const\r
+;\r
+; Float control word initial value: \r
+; all exceptions masked, double-precision, round-to-nearest\r
+;\r
+mFpuControlWord       DW      027Fh\r
+;\r
+; Multimedia-extensions control word:\r
+; all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
+;\r
+mMmxControlWord       DD      01F80h \r
+\r
+.code\r
+\r
+\r
+;
+; Initializes floating point units for requirement of UEFI specification.\r
+;\r
+; This function initializes floating-point control word to 0x027F (all exceptions\r
+; masked,double-precision, round-to-nearest) and multimedia-extensions control word\r
+; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r
+; for masked underflow).
+;\r
+InitializeFloatingPointUnits PROC PUBLIC\r
+\r
+    ;\r
+    ; Initialize floating point units\r
+    ;\r
+    finit\r
+    fldcw   mFpuControlWord\r
+    \r
+    ;\r
+    ; Set OSFXSR bit 9 in CR4\r
+    ;\r
+    mov     rax, cr4\r
+    or      rax, BIT9\r
+    mov     cr4, rax\r
+\r
+    ldmxcsr mMmxControlWord\r
+    \r
+    ret\r
+InitializeFloatingPointUnits ENDP\r
+\r
+END\r
index 4a249c1..b67a9e1 100644 (file)
@@ -24,3 +24,8 @@
 [Includes.common]
   Include
 
+[LibraryClasses]
+  ##  @libraryclass  Defines some routines that are generic for IA32 family CPU
+  ##                 to be UEFI specification compliant.
+  ##
+  UefiCpuLib|Include/Library/UefiCpuLib.h
index 557f452..ab8a464 100644 (file)
@@ -50,4 +50,4 @@
 \r
 [Components.common]\r
   UefiCpuPkg/CpuIoDxe/CpuIo.inf\r
-
+  UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf\r