IntelSiliconPkg: Updated IgdOpregion.h based on latest spec

Updated IgdOpregion.h to align with latest specification
https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf

1) Updated Mailbox structures to align with latest spec
2) Added Mailbox 5 structure
3) Added defines for Signature and Mailbox support

Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>

diff --git a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
index 7f76c09baecfca260ee81d674e5b9921d4e2b059..4d5637c6ede4c55b56a627744013ec908e11f252 100644 (file)
--- a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
+++ b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
@@ -2,14 +2,7 @@
   IGD OpRegion definition from Intel Integrated Graphics Device OpRegion\r
   Specification.\r
 \r
-  https://01.org/sites/default/files/documentation/acpi_igd_opregion_spec_0.pdf\r
-\r
-  There are some mismatch between the specification and the implementation.\r
-  The definition follows the latest implementation.\r
-  1) INTEL_IGD_OPREGION_HEADER.RSV1[0xA0]\r
-  2) INTEL_IGD_OPREGION_MBOX1.RSV3[0x3C]\r
-  3) INTEL_IGD_OPREGION_MBOX3.RSV5[0x62]\r
-  4) INTEL_IGD_OPREGION_VBT.RVBT[0x1800] Size is 6KB\r
+  https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf\r
 \r
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
@@ -24,6 +17,13 @@
 #ifndef _IGD_OPREGION_H_\r
 #define _IGD_OPREGION_H_\r
 \r
+#define IGD_OPREGION_HEADER_SIGN "IntelGraphicsMem"\r
+#define IGD_OPREGION_HEADER_MBOX1 BIT0\r
+#define IGD_OPREGION_HEADER_MBOX2 BIT1\r
+#define IGD_OPREGION_HEADER_MBOX3 BIT2\r
+#define IGD_OPREGION_HEADER_MBOX4 BIT3\r
+#define IGD_OPREGION_HEADER_MBOX5 BIT4\r
+\r
 /**\r
   OpRegion structures:\r
   Sub-structures define the different parts of the OpRegion followed by the\r
@@ -49,7 +49,9 @@ typedef struct {
   UINT8  GVER[0x10];    ///< Offset 0x48 Graphic Driver Build Version\r
   UINT32 MBOX;          ///< Offset 0x58 Supported Mailboxes\r
   UINT32 DMOD;          ///< Offset 0x5C Driver Model\r
-  UINT8  RSV1[0xA0];    ///< Offset 0x60 Reserved\r
+  UINT32 PCON;          ///< Offset 0x60 Platform Configuration\r
+  CHAR16 DVER[0x10]     ///< Offset 0x64 GOP Version\r
+  UINT8  RM01[0x7C];    ///< Offset 0x84 Reserved Must be zero\r
 } IGD_OPREGION_HEADER;\r
 \r
 ///\r
@@ -60,7 +62,7 @@ typedef struct {
   UINT32 DRDY;          ///< Offset 0x100 Driver Readiness\r
   UINT32 CSTS;          ///< Offset 0x104 Status\r
   UINT32 CEVT;          ///< Offset 0x108 Current Event\r
-  UINT8  RSVD[0x14];    ///< Offset 0x10C Reserved Must be Zero\r
+  UINT8  RM11[0x14];    ///< Offset 0x10C Reserved Must be Zero\r
   UINT32 DIDL[8];       ///< Offset 0x120 Supported Display Devices ID List\r
   UINT32 CPDL[8];       ///< Offset 0x140 Currently Attached Display Devices List\r
   UINT32 CADL[8];       ///< Offset 0x160 Currently Active Display Devices List\r
@@ -74,7 +76,9 @@ typedef struct {
   UINT32 EVTS;          ///< Offset 0x1B8 Events supported by ASL\r
   UINT32 CNOT;          ///< Offset 0x1BC Current OS Notification\r
   UINT32 NRDY;          ///< Offset 0x1C0 Driver Status\r
-  UINT8  RSV3[0x3C];    ///< Offset 0x1C4 - 0x1FF Reserved\r
+  UINT8  DID2[0x1C];    ///< Offset 0x1C4 Extended Supported Devices ID List (DOD)\r
+  UINT8  CPD2[0x1C];    ///< Offset 0x1E0 Extended Attached Display Devices List\r
+  UINT8  RM12[4];       ///< Offset 0x1FC - 0x1FF Reserved Must be zero\r
 } IGD_OPREGION_MBOX1;\r
 \r
 ///\r
@@ -85,7 +89,7 @@ typedef struct {
   UINT32 SCIC;          ///< Offset 0x200 Software SCI Command / Status / Data\r
   UINT32 PARM;          ///< Offset 0x204 Software SCI Parameters\r
   UINT32 DSLP;          ///< Offset 0x208 Driver Sleep Time Out\r
-  UINT8  RSV4[0xF4];    ///< Offset 0x20C - 0x2FF Reserved\r
+  UINT8  RM21[0xF4];    ///< Offset 0x20C - 0x2FF Reserved Must be zero\r
 } IGD_OPREGION_MBOX2;\r
 \r
 ///\r
@@ -106,7 +110,13 @@ typedef struct {
   UINT8  PLUT[0x4A];    ///< Offset 0x34C Panel Look Up Table & Identifier\r
   UINT32 PFMB;          ///< Offset 0x396 PWM Frequency and Minimum Brightness\r
   UINT32 CCDV;          ///< Offset 0x39A Color Correction Default Values\r
-  UINT8  RSV5[0x62];    ///< Offset 0x39E - 0x3FF  Reserved\r
+  UINT32 PCFT;          ///< Offset 0x39E Power Conservation Features\r
+  UINT32 SROT;          ///< Offset 0x3A2 Supported Rotation Angles\r
+  UINT32 IUER;          ///< Offset 0x3A6 Intel Ultrabook(TM) Event Register\r
+  UINT64 FDSS;          ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature\r
+  UINT32 FDSP;          ///< Offset 0x3B2 Size of DSS buffer\r
+  UINT32 STAT;          ///< Offset 0x3B6 State Indicator\r
+  UINT8  RM31[0x45];    ///< Offset 0x3BA - 0x3FF  Reserved Must be zero\r
 } IGD_OPREGION_MBOX3;\r
 \r
 ///\r
@@ -117,6 +127,16 @@ typedef struct {
   UINT8  RVBT[0x1800];  ///< Offset 0x400 - 0x1BFF Raw VBT Data\r
 } IGD_OPREGION_MBOX4;\r
 \r
+///\r
+/// OpRegion Mailbox 5 - BIOS/Driver Notification - Data storage BIOS to Driver data sync\r
+/// Offset 0x1C00, Size 0x400\r
+///\r
+typedef struct {\r
+  UINT32 PHED;          ///< Offset 0x1C00 Panel Header\r
+  UINT8  BDDC[0x100];   ///< Offset 0x1C04 Panel EDID (DDC data)\r
+  UINT8  RM51[0x2FC];   ///< Offset 0x1D04 - 0x1FFF Reserved Must be zero\r
+} IGD_OPREGION_MBOX5;\r
+\r
 ///\r
 /// IGD OpRegion Structure\r
 ///\r
@@ -126,6 +146,7 @@ typedef struct {
   IGD_OPREGION_MBOX2  MBox2;  ///< Mailbox 2: Software SCI Interface (Offset 0x200, Size 0x100)\r
   IGD_OPREGION_MBOX3  MBox3;  ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100)\r
   IGD_OPREGION_MBOX4  MBox4;  ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800)\r
+  IGD_OPREGION_MBOX5  MBox5;  ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400)\r
 } IGD_OPREGION_STRUCTURE;\r
 #pragma pack()\r
 \r