+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2013, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Chipset/AArch64.h>\r
-\r
-VOID\r
-EFIAPI\r
-ArmSecArchTrustzoneInit (\r
- VOID\r
- )\r
-{\r
- // Do not trap any access to Floating Point and Advanced SIMD in EL3.\r
- ArmWriteCptr (0);\r
-}\r
+++ /dev/null
-#========================================================================================\r
-# Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http:#opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#=======================================================================================\r
-\r
-#include <AsmMacroIoLibV8.h>\r
-#include <Chipset/AArch64.h>\r
-\r
-#start of the code section\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(SwitchToNSExceptionLevel1)\r
-GCC_ASM_EXPORT(enter_monitor_mode)\r
-GCC_ASM_EXPORT(return_from_exception)\r
-GCC_ASM_EXPORT(copy_cpsr_into_spsr)\r
-GCC_ASM_EXPORT(set_non_secure_mode)\r
-\r
-// Switch from EL3 to NS-EL1\r
-ASM_PFX(SwitchToNSExceptionLevel1):\r
- // Now setup our EL1. Controlled by EL2 config on Model\r
- mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register\r
- orr x0, x0, #(1 << 31) // Set EL1 to be 64bit\r
-\r
- // Send all interrupts to their respective Exception levels for EL2\r
- and x0, x0, #~(ARM_HCR_FMO | ARM_HCR_IMO | ARM_HCR_AMO) // Disable virtual FIQ, IRQ, SError and Abort\r
- msr hcr_el2, x0 // Write back our settings\r
-\r
- msr cptr_el2, xzr // Disable copro traps to EL2\r
-\r
- msr sctlr_el2, xzr\r
-\r
- // Enable architected timer access\r
- mrs x0, cnthctl_el2\r
- orr x0, x0, #3 // Enable EL1 access to timers\r
- msr cnthctl_el2, x0\r
-\r
- mrs x0, cntkctl_el1\r
- orr x0, x0, #3 // EL0 access to counters\r
- msr cntkctl_el1, x0\r
-\r
- // Set ID regs\r
- mrs x0, midr_el1\r
- mrs x1, mpidr_el1\r
- msr vpidr_el2, x0\r
- msr vmpidr_el2, x1\r
-\r
- ret\r
-\r
-\r
-// EL3 on AArch64 is Secure/monitor so this funtion is reduced vs ARMv7\r
-// we don't need a mode switch, just setup the Arguments and jump.\r
-// x0: Monitor World EntryPoint\r
-// x1: MpId\r
-// x2: SecBootMode\r
-// x3: Secure Monitor mode stack\r
-ASM_PFX(enter_monitor_mode):\r
- mov x4, x0 // Swap EntryPoint and MpId registers\r
- mov x0, x1\r
- mov x1, x2\r
- mov x2, x3\r
- br x4\r
-\r
-// Put the address in correct ELR_ELx and do a eret.\r
-// We may need to do some config before we change to another Mode.\r
-ASM_PFX(return_from_exception):\r
- msr elr_el3, x0\r
- eret\r
-\r
-// For AArch64 we need to construct the spsr we want from individual bits and pieces.\r
-ASM_PFX(copy_cpsr_into_spsr):\r
- mrs x0, CurrentEl // Get the current exception level we are running at.\r
- mrs x1, SPSel // Which Stack are we using\r
- orr x0, x0, x1\r
- mrs x1, daif // Which interrupts are enabled\r
- orr x0, x0, x1\r
- msr spsr_el3, x0 // Write to spsr\r
- ret\r
-\r
-// Get this from platform file.\r
-ASM_PFX(set_non_secure_mode):\r
- msr spsr_el3, x0\r
- ret\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AutoGen.h>\r
-#include <AsmMacroIoLibV8.h>\r
-#include "SecInternal.h"\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_IMPORT(CEntryPoint)\r
-GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
-GCC_ASM_IMPORT(ArmPlatformGetCorePosition)\r
-GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r
-GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)\r
-GCC_ASM_IMPORT(ArmDisableInterrupts)\r
-GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r
-GCC_ASM_IMPORT(ArmReadMpidr)\r
-GCC_ASM_IMPORT(ArmCallWFE)\r
-GCC_ASM_EXPORT(_ModuleEntryPoint)\r
-\r
-StartupAddr: .8byte ASM_PFX(CEntryPoint)\r
-\r
-ASM_PFX(_ModuleEntryPoint):\r
-\r
-// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect\r
-// and configure the system accordingly. EL2 is default if possible.\r
-// If we started in EL3 we need to switch and run at EL2.\r
-// If we are running at EL2 stay in EL2\r
-// If we are starting at EL1 stay in EL1.\r
-\r
-// Sec only runs in EL3. Othewise we jump to PEI without changing anything.\r
-// If Sec runs we change to EL2 before switching to PEI.\r
-\r
-// Which EL are we running at? Every EL needs some level of setup...\r
- EL1_OR_EL2_OR_EL3(x0)\r
-1:// If we are at EL1 or EL2 leave SEC for PEI.\r
-2:b ASM_PFX(JumpToPEI)\r
- // If we are at EL3 we need to configure it and switch to EL2\r
-3:b ASM_PFX(MainEntryPoint)\r
-\r
-ASM_PFX(MainEntryPoint):\r
- // First ensure all interrupts are disabled\r
- bl ASM_PFX(ArmDisableInterrupts)\r
-\r
- // Ensure that the MMU and caches are off\r
- bl ASM_PFX(ArmDisableCachesAndMmu)\r
-\r
- // By default, we are doing a cold boot\r
- mov x10, #ARM_SEC_COLD_BOOT\r
-\r
- // Jump to Platform Specific Boot Action function\r
- bl ASM_PFX(ArmPlatformSecBootAction)\r
-\r
-_IdentifyCpu:\r
- // Identify CPU ID\r
- bl ASM_PFX(ArmReadMpidr)\r
- // Keep a copy of the MpId register value\r
- mov x5, x0\r
-\r
- // Is it the Primary Core ?\r
- bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
- cmp x0, #1\r
- // Only the primary core initialize the memory (SMC)\r
- b.eq _InitMem\r
-\r
-_WaitInitMem:\r
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
- // Otherwise we have to wait the Primary Core to finish the initialization\r
- cmp x10, #ARM_SEC_COLD_BOOT\r
- b.ne _SetupSecondaryCoreStack\r
-\r
- // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
- bl ASM_PFX(ArmCallWFE)\r
- // Now the Init Mem is initialized, we setup the secondary core stacks\r
- b _SetupSecondaryCoreStack\r
-\r
-_InitMem:\r
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
- cmp x10, #ARM_SEC_COLD_BOOT\r
- b.ne _SetupPrimaryCoreStack\r
-\r
- // Initialize Init Boot Memory\r
- bl ASM_PFX(ArmPlatformSecBootMemoryInit)\r
-\r
-_SetupPrimaryCoreStack:\r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), x1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), x2)\r
- add x1, x1, x2\r
-\r
- mov sp, x1\r
- b _PrepareArguments\r
-\r
-_SetupSecondaryCoreStack:\r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), x1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), x2)\r
- add x6, x1, x2\r
-\r
- // Get the Core Position\r
- mov x0, x5\r
- bl ASM_PFX(ArmPlatformGetCorePosition)\r
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
- add x0, x0, #1\r
-\r
- // StackOffset = CorePos * StackSize\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), x2)\r
- mul x0, x0, x2\r
- // SP = StackBase + StackOffset\r
- add sp, x6, x0\r
-\r
-_PrepareArguments:\r
- // Move sec startup address into a data register\r
- // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
- ldr x3, StartupAddr\r
-\r
- // Jump to SEC C code\r
- // r0 = mp_id\r
- // r1 = Boot Mode\r
- mov x0, x5\r
- mov x1, x10\r
- blr x3\r
-\r
- ret\r
-\r
-ASM_PFX(JumpToPEI):\r
- LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), x0)\r
- blr x0\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2013, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Chipset/ArmV7.h>\r
-\r
-VOID\r
-EFIAPI\r
-ArmSecArchTrustzoneInit (\r
- VOID\r
- )\r
-{\r
- // Write to CP15 Non-secure Access Control Register\r
- ArmWriteNsacr (PcdGet32 (PcdArmNsacr));\r
-}\r
+++ /dev/null
-#========================================================================================\r
-# Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#=======================================================================================\r
-\r
-#start of the code section\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(return_from_exception)\r
-GCC_ASM_EXPORT(enter_monitor_mode)\r
-GCC_ASM_EXPORT(copy_cpsr_into_spsr)\r
-GCC_ASM_EXPORT(set_non_secure_mode)\r
-\r
-# r0: Monitor World EntryPoint\r
-# r1: MpId\r
-# r2: SecBootMode\r
-# r3: Secure Monitor mode stack\r
-ASM_PFX(enter_monitor_mode):\r
- cmp r3, #0 @ If a Secure Monitor stack base has not been defined then use the Secure stack\r
- moveq r3, sp\r
-\r
- mrs r4, cpsr @ Save current mode (SVC) in r4\r
- bic r5, r4, #0x1f @ Clear all mode bits\r
- orr r5, r5, #0x16 @ Set bits for Monitor mode\r
- msr cpsr_cxsf, r5 @ We are now in Monitor Mode\r
-\r
- mov sp, r3 @ Set the stack of the Monitor Mode\r
-\r
- mov lr, r0 @ Use the pass entrypoint as lr\r
-\r
- msr spsr_cxsf, r4 @ Use saved mode for the MOVS jump to the kernel\r
-\r
- mov r4, r0 @ Swap EntryPoint and MpId registers\r
- mov r0, r1\r
- mov r1, r2\r
- mov r2, r3\r
-\r
- bx r4\r
-\r
-# Return-from-exception is not an interworking return, so we must do it\r
-# in two steps, in case r0 has the Thumb bit set.\r
-ASM_PFX(return_from_exception):\r
- adr lr, returned_exception\r
- movs pc, lr\r
-returned_exception: @ We are now in non-secure state\r
- bx r0\r
-\r
-# Save the current Program Status Register (PSR) into the Saved PSR\r
-ASM_PFX(copy_cpsr_into_spsr):\r
- mrs r0, cpsr\r
- msr spsr_cxsf, r0\r
- bx lr\r
-\r
-# Set the Non Secure Mode\r
-ASM_PFX(set_non_secure_mode):\r
- push { r1 }\r
- and r0, r0, #0x1f @ Keep only the mode bits\r
- mrs r1, spsr @ Read the spsr\r
- bic r1, r1, #0x1f @ Clear all mode bits\r
- orr r1, r1, r0\r
- msr spsr_cxsf, r1 @ write back spsr (may have caused a mode switch)\r
- isb\r
- pop { r1 }\r
- bx lr @ return (hopefully thumb-safe!)\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
- EXPORT return_from_exception\r
- EXPORT enter_monitor_mode\r
- EXPORT copy_cpsr_into_spsr\r
- EXPORT set_non_secure_mode\r
-\r
- AREA Helper, CODE, READONLY\r
-\r
-// r0: Monitor World EntryPoint\r
-// r1: MpId\r
-// r2: SecBootMode\r
-// r3: Secure Monitor mode stack\r
-enter_monitor_mode FUNCTION\r
- cmp r3, #0 // If a Secure Monitor stack base has not been defined then use the Secure stack\r
- moveq r3, sp\r
-\r
- mrs r4, cpsr // Save current mode (SVC) in r4\r
- bic r5, r4, #0x1f // Clear all mode bits\r
- orr r5, r5, #0x16 // Set bits for Monitor mode\r
- msr cpsr_cxsf, r5 // We are now in Monitor Mode\r
-\r
- mov sp, r3 // Set the stack of the Monitor Mode\r
-\r
- mov lr, r0 // Use the pass entrypoint as lr\r
-\r
- msr spsr_cxsf, r4 // Use saved mode for the MOVS jump to the kernel\r
-\r
- mov r4, r0 // Swap EntryPoint and MpId registers\r
- mov r0, r1\r
- mov r1, r2\r
- mov r2, r3\r
-\r
- bx r4\r
- ENDFUNC\r
-\r
-// Return-from-exception is not an interworking return, so we must do it\r
-// in two steps, in case r0 has the Thumb bit set.\r
-return_from_exception\r
- adr lr, returned_exception\r
- movs pc, lr\r
-returned_exception // We are now in non-secure state\r
- bx r0\r
-\r
-// Save the current Program Status Register (PSR) into the Saved PSR\r
-copy_cpsr_into_spsr\r
- mrs r0, cpsr\r
- msr spsr_cxsf, r0\r
- bx lr\r
-\r
-// Set the Non Secure Mode\r
-set_non_secure_mode\r
- push { r1 }\r
- and r0, r0, #0x1f // Keep only the mode bits\r
- mrs r1, spsr // Read the spsr\r
- bic r1, r1, #0x1f // Clear all mode bits\r
- orr r1, r1, r0\r
- msr spsr_cxsf, r1 // write back spsr (may have caused a mode switch)\r
- isb\r
- pop { r1 }\r
- bx lr // return (hopefully thumb-safe!)\r
-\r
-dead\r
- B dead\r
-\r
- END\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AutoGen.h>\r
-#include <AsmMacroIoLib.h>\r
-#include "SecInternal.h"\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_IMPORT(CEntryPoint)\r
-GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
-GCC_ASM_IMPORT(ArmPlatformGetCorePosition)\r
-GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r
-GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)\r
-GCC_ASM_IMPORT(ArmDisableInterrupts)\r
-GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r
-GCC_ASM_IMPORT(ArmReadMpidr)\r
-GCC_ASM_IMPORT(ArmCallWFE)\r
-GCC_ASM_EXPORT(_ModuleEntryPoint)\r
-\r
-StartupAddr: .word ASM_PFX(CEntryPoint)\r
-\r
-ASM_PFX(_ModuleEntryPoint):\r
- // First ensure all interrupts are disabled\r
- bl ASM_PFX(ArmDisableInterrupts)\r
-\r
- // Ensure that the MMU and caches are off\r
- bl ASM_PFX(ArmDisableCachesAndMmu)\r
-\r
- // By default, we are doing a cold boot\r
- mov r10, #ARM_SEC_COLD_BOOT\r
-\r
- // Jump to Platform Specific Boot Action function\r
- blx ASM_PFX(ArmPlatformSecBootAction)\r
-\r
-_IdentifyCpu:\r
- // Identify CPU ID\r
- bl ASM_PFX(ArmReadMpidr)\r
- // Keep a copy of the MpId register value\r
- mov r9, r0\r
-\r
- // Is it the Primary Core ?\r
- bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
- cmp r0, #1\r
- // Only the primary core initialize the memory (SMC)\r
- beq _InitMem\r
-\r
-_WaitInitMem:\r
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
- // Otherwise we have to wait the Primary Core to finish the initialization\r
- cmp r10, #ARM_SEC_COLD_BOOT\r
- bne _SetupSecondaryCoreStack\r
-\r
- // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
- bl ASM_PFX(ArmCallWFE)\r
- // Now the Init Mem is initialized, we setup the secondary core stacks\r
- b _SetupSecondaryCoreStack\r
-\r
-_InitMem:\r
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
- cmp r10, #ARM_SEC_COLD_BOOT\r
- bne _SetupPrimaryCoreStack\r
-\r
- // Initialize Init Boot Memory\r
- bl ASM_PFX(ArmPlatformSecBootMemoryInit)\r
-\r
-_SetupPrimaryCoreStack:\r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
- add r1, r1, r2\r
-\r
- mov sp, r1\r
- b _PrepareArguments\r
-\r
-_SetupSecondaryCoreStack:\r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
- add r6, r1, r2\r
-\r
- // Get the Core Position\r
- mov r0, r9\r
- bl ASM_PFX(ArmPlatformGetCorePosition)\r
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
- add r0, r0, #1\r
-\r
- // StackOffset = CorePos * StackSize\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
- mul r0, r0, r2\r
- // SP = StackBase + StackOffset\r
- add sp, r6, r0\r
-\r
-_PrepareArguments:\r
- // Move sec startup address into a data register\r
- // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
- ldr r3, StartupAddr\r
-\r
- // Jump to SEC C code\r
- // r0 = mp_id\r
- // r1 = Boot Mode\r
- mov r0, r9\r
- mov r1, r10\r
- blx r3\r
-\r
-_NeverReturn:\r
- b _NeverReturn\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AutoGen.h>\r
-#include <AsmMacroIoLib.h>\r
-#include "SecInternal.h"\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
- IMPORT CEntryPoint\r
- IMPORT ArmPlatformIsPrimaryCore\r
- IMPORT ArmPlatformGetCorePosition\r
- IMPORT ArmPlatformSecBootAction\r
- IMPORT ArmPlatformSecBootMemoryInit\r
- IMPORT ArmDisableInterrupts\r
- IMPORT ArmDisableCachesAndMmu\r
- IMPORT ArmReadMpidr\r
- IMPORT ArmCallWFE\r
- EXPORT _ModuleEntryPoint\r
-\r
- PRESERVE8\r
- AREA SecEntryPoint, CODE, READONLY\r
-\r
-StartupAddr DCD CEntryPoint\r
-\r
-_ModuleEntryPoint FUNCTION\r
- // First ensure all interrupts are disabled\r
- bl ArmDisableInterrupts\r
-\r
- // Ensure that the MMU and caches are off\r
- bl ArmDisableCachesAndMmu\r
-\r
- // By default, we are doing a cold boot\r
- mov r10, #ARM_SEC_COLD_BOOT\r
-\r
- // Jump to Platform Specific Boot Action function\r
- blx ArmPlatformSecBootAction\r
-\r
-_IdentifyCpu\r
- // Identify CPU ID\r
- bl ArmReadMpidr\r
- // Keep a copy of the MpId register value\r
- mov r9, r0\r
-\r
- // Is it the Primary Core ?\r
- bl ArmPlatformIsPrimaryCore\r
- cmp r0, #1\r
- // Only the primary core initialize the memory (SMC)\r
- beq _InitMem\r
-\r
-_WaitInitMem\r
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
- // Otherwise we have to wait the Primary Core to finish the initialization\r
- cmp r10, #ARM_SEC_COLD_BOOT\r
- bne _SetupSecondaryCoreStack\r
-\r
- // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
- bl ArmCallWFE\r
- // Now the Init Mem is initialized, we setup the secondary core stacks\r
- b _SetupSecondaryCoreStack\r
-\r
-_InitMem\r
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
- cmp r10, #ARM_SEC_COLD_BOOT\r
- bne _SetupPrimaryCoreStack\r
-\r
- // Initialize Init Boot Memory\r
- bl ArmPlatformSecBootMemoryInit\r
-\r
-_SetupPrimaryCoreStack\r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
- add r1, r1, r2\r
-\r
- mov sp, r1\r
- b _PrepareArguments\r
-\r
-_SetupSecondaryCoreStack\r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
- add r6, r1, r2\r
-\r
- // Get the Core Position\r
- mov r0, r9\r
- bl ArmPlatformGetCorePosition\r
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
- add r0, r0, #1\r
-\r
- // StackOffset = CorePos * StackSize\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
- mul r0, r0, r2\r
- // SP = StackBase + StackOffset\r
- add sp, r6, r0\r
-\r
-_PrepareArguments\r
- // Move sec startup address into a data register\r
- // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
- ldr r3, StartupAddr\r
-\r
- // Jump to SEC C code\r
- // r0 = mp_id\r
- // r1 = Boot Mode\r
- mov r0, r9\r
- mov r1, r10\r
- blx r3\r
- ENDFUNC\r
-\r
-_NeverReturn\r
- b _NeverReturn\r
- END\r
+++ /dev/null
-/** @file\r
-* Main file supporting the SEC Phase on ARM Platforms\r
-*\r
-* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/ArmTrustedMonitorLib.h>\r
-#include <Library/DebugAgentLib.h>\r
-#include <Library/PrintLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/SerialPortLib.h>\r
-#include <Library/ArmGicLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
-\r
-#include "SecInternal.h"\r
-\r
-#define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);\r
-\r
-VOID\r
-CEntryPoint (\r
- IN UINTN MpId,\r
- IN UINTN SecBootMode\r
- )\r
-{\r
- CHAR8 Buffer[100];\r
- UINTN CharCount;\r
- UINTN JumpAddress;\r
-\r
- // Invalidate the data cache. Doesn't have to do the Data cache clean.\r
- ArmInvalidateDataCache ();\r
-\r
- // Invalidate Instruction Cache\r
- ArmInvalidateInstructionCache ();\r
-\r
- // Invalidate I & D TLBs\r
- ArmInvalidateTlb ();\r
-\r
- // CPU specific settings\r
- ArmCpuSetup (MpId);\r
-\r
- // Enable Floating Point Coprocessor if supported by the platform\r
- if (FixedPcdGet32 (PcdVFPEnabled)) {\r
- ArmEnableVFP ();\r
- }\r
-\r
- // Initialize peripherals that must be done at the early stage\r
- // Example: Some L2 controller, interconnect, clock, DMC, etc\r
- ArmPlatformSecInitialize (MpId);\r
-\r
- // Primary CPU clears out the SCU tag RAMs, secondaries wait\r
- if (ArmPlatformIsPrimaryCore (MpId) && (SecBootMode == ARM_SEC_COLD_BOOT)) {\r
- if (ArmIsMpCore()) {\r
- // Signal for the initial memory is configured (event: BOOT_MEM_INIT)\r
- ArmCallSEV ();\r
- }\r
-\r
- // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib\r
- // In non SEC modules the init call is in autogenerated code.\r
- SerialPortInitialize ();\r
-\r
- // Start talking\r
- if (FixedPcdGetBool (PcdTrustzoneSupport)) {\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Secure firmware (version %s built at %a on %a)\n\r",\r
- (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);\r
- } else {\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Boot firmware (version %s built at %a on %a)\n\r",\r
- (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);\r
- }\r
- SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
-\r
- // Initialize the Debug Agent for Source Level Debugging\r
- InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);\r
- SaveAndSetDebugTimerInterrupt (TRUE);\r
-\r
- // Enable the GIC distributor and CPU Interface\r
- // - no other Interrupts are enabled, doesn't have to worry about the priority.\r
- // - all the cores are in secure state, use secure SGI's\r
- ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));\r
- ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));\r
- } else {\r
- // Enable the GIC CPU Interface\r
- ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));\r
- }\r
-\r
- // Enable Full Access to CoProcessors\r
- ArmWriteCpacr (CPACR_CP_FULL_ACCESS);\r
-\r
- // Test if Trustzone is supported on this platform\r
- if (FixedPcdGetBool (PcdTrustzoneSupport)) {\r
- if (ArmIsMpCore ()) {\r
- // Setup SMP in Non Secure world\r
- ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));\r
- }\r
-\r
- // Either we use the Secure Stacks for Secure Monitor (in this case (Base == 0) && (Size == 0))\r
- // Or we use separate Secure Monitor stacks (but (Base != 0) && (Size != 0))\r
- ASSERT (((PcdGet32(PcdCPUCoresSecMonStackBase) == 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) == 0)) ||\r
- ((PcdGet32(PcdCPUCoresSecMonStackBase) != 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) != 0)));\r
-\r
- // Enter Monitor Mode\r
- enter_monitor_mode (\r
- (UINTN)TrustedWorldInitialization, MpId, SecBootMode,\r
- (VOID*) (PcdGet32 (PcdCPUCoresSecMonStackBase) +\r
- (PcdGet32 (PcdCPUCoreSecMonStackSize) * (ArmPlatformGetCorePosition (MpId) + 1)))\r
- );\r
- } else {\r
- if (ArmPlatformIsPrimaryCore (MpId)) {\r
- SerialPrint ("Trust Zone Configuration is disabled\n\r");\r
- }\r
-\r
- // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().\r
- // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program\r
- // Status Register as the the current one (CPSR).\r
- copy_cpsr_into_spsr ();\r
-\r
- // Call the Platform specific function to execute additional actions if required\r
- JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
- ArmPlatformSecExtraAction (MpId, &JumpAddress);\r
-\r
- NonTrustedWorldTransition (MpId, JumpAddress);\r
- }\r
- ASSERT (0); // We must never return from the above function\r
-}\r
-\r
-VOID\r
-TrustedWorldInitialization (\r
- IN UINTN MpId,\r
- IN UINTN SecBootMode\r
- )\r
-{\r
- UINTN JumpAddress;\r
-\r
- //-------------------- Monitor Mode ---------------------\r
-\r
- // Set up Monitor World (Vector Table, etc)\r
- ArmSecureMonitorWorldInitialize ();\r
-\r
- // Transfer the interrupt to Non-secure World\r
- ArmGicSetupNonSecure (MpId, PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));\r
-\r
- // Initialize platform specific security policy\r
- ArmPlatformSecTrustzoneInit (MpId);\r
-\r
- // Setup the Trustzone Chipsets\r
- if (SecBootMode == ARM_SEC_COLD_BOOT) {\r
- if (ArmPlatformIsPrimaryCore (MpId)) {\r
- if (ArmIsMpCore()) {\r
- // Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)\r
- ArmCallSEV ();\r
- }\r
- } else {\r
- // The secondary cores need to wait until the Trustzone chipsets configuration is done\r
- // before switching to Non Secure World\r
-\r
- // Wait for the Primary Core to finish the initialization of the Secure World (event: EVENT_SECURE_INIT)\r
- ArmCallWFE ();\r
- }\r
- }\r
-\r
- // Call the Platform specific function to execute additional actions if required\r
- JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
- ArmPlatformSecExtraAction (MpId, &JumpAddress);\r
-\r
- // Initialize architecture specific security policy\r
- ArmSecArchTrustzoneInit ();\r
-\r
- // CP15 Secure Configuration Register\r
- ArmWriteScr (PcdGet32 (PcdArmScr));\r
-\r
- NonTrustedWorldTransition (MpId, JumpAddress);\r
-}\r
-\r
-VOID\r
-NonTrustedWorldTransition (\r
- IN UINTN MpId,\r
- IN UINTN JumpAddress\r
- )\r
-{\r
- // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition\r
- // By not set, the mode for Non Secure World is SVC\r
- if (PcdGet32 (PcdArmNonSecModeTransition) != 0) {\r
- set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition));\r
- }\r
-\r
- return_from_exception (JumpAddress);\r
- //-------------------- Non Secure Mode ---------------------\r
-\r
- // PEI Core should always load and never return\r
- ASSERT (FALSE);\r
-}\r
-\r
+++ /dev/null
-#/** @file\r
-# SEC - Reset vector code that jumps to C and starts the PEI phase\r
-#\r
-# (C) Copyright 2015 Hewlett-Packard Development Company, L.P.<BR>\r
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmPlatformSec\r
- FILE_GUID = c536bbfe-c813-4e48-9f90-01fe1ecf9d54\r
- MODULE_TYPE = SEC\r
- VERSION_STRING = 1.0\r
-\r
-[Sources]\r
- Sec.c\r
-\r
-[Sources.ARM]\r
- Arm/Arch.c\r
- Arm/Helper.asm | RVCT\r
- Arm/Helper.S | GCC\r
- Arm/SecEntryPoint.S | GCC\r
- Arm/SecEntryPoint.asm | RVCT\r
-\r
-[Sources.AARCH64]\r
- AArch64/Arch.c\r
- AArch64/Helper.S\r
- AArch64/SecEntryPoint.S\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
- ArmCpuLib\r
- ArmLib\r
- ArmPlatformLib\r
- ArmPlatformSecLib\r
- ArmTrustedMonitorLib\r
- BaseLib\r
- DebugLib\r
- DebugAgentLib\r
- IoLib\r
- ArmGicLib\r
- PrintLib\r
- SerialPortLib\r
-\r
-[Pcd]\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString\r
-\r
-[FixedPcd.common]\r
-\r
- gArmTokenSpaceGuid.PcdTrustzoneSupport\r
- gArmTokenSpaceGuid.PcdVFPEnabled\r
-\r
- gArmTokenSpaceGuid.PcdArmScr\r
- gArmTokenSpaceGuid.PcdArmNonSecModeTransition\r
-\r
- gArmTokenSpaceGuid.PcdSecureFvBaseAddress\r
- gArmTokenSpaceGuid.PcdSecureFvSize\r
-\r
- gArmTokenSpaceGuid.PcdFvBaseAddress\r
-\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize\r
-\r
- gArmTokenSpaceGuid.PcdGicDistributorBase\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
-\r
-[FixedPcd.ARM]\r
- gArmTokenSpaceGuid.PcdArmNsacr\r
+++ /dev/null
-/** @file\r
-* Main file supporting the SEC Phase on ARM PLatforms\r
-*\r
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef __SEC_H__\r
-#define __SEC_H__\r
-\r
-#include <Base.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/ArmCpuLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/ArmPlatformSecLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)\r
-\r
-VOID\r
-TrustedWorldInitialization (\r
- IN UINTN MpId,\r
- IN UINTN SecBootMode\r
- );\r
-\r
-VOID\r
-NonTrustedWorldTransition (\r
- IN UINTN MpId,\r
- IN UINTN JumpAddress\r
- );\r
-\r
-VOID\r
-ArmSetupGicNonSecure (\r
- IN INTN GicDistributorBase,\r
- IN INTN GicInterruptInterfaceBase\r
-);\r
-\r
-VOID\r
-enter_monitor_mode (\r
- IN UINTN MonitorEntryPoint,\r
- IN UINTN MpId,\r
- IN UINTN SecBootMode,\r
- IN VOID* MonitorStackBase\r
- );\r
-\r
-VOID\r
-return_from_exception (\r
- IN UINTN NonSecureBase\r
- );\r
-\r
-VOID\r
-copy_cpsr_into_spsr (\r
- VOID\r
- );\r
-\r
-VOID\r
-set_non_secure_mode (\r
- IN ARM_PROCESSOR_MODE Mode\r
- );\r
-\r
-VOID\r
-SecCommonExceptionEntry (\r
- IN UINT32 Entry,\r
- IN UINTN LR\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmSecArchTrustzoneInit (\r
- VOID\r
- );\r
-\r
-#endif\r
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