\r
//\r
// Bitmask of Opearation of PAL_CACHE_FLUSH.\r
-// \r
+//\r
#define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0\r
#define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0\r
#define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1\r
#define PAL_CACHE_FLUSH_NO_INTERRUPT 0\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_CACHE_FLUSH.\r
- \r
+\r
Flush the instruction or data caches. It is required by IPF.\r
The PAL procedure supports the Static Registers calling\r
convention. It could be called at virtual mode and physical\r
\r
@param Index Index of PAL_CACHE_FLUSH within the\r
list of PAL procedures.\r
- \r
+\r
@param CacheType Unsigned 64-bit integer indicating\r
which cache to flush.\r
\r
@param ProgressIndicator Unsigned 64-bit integer specifying\r
the starting position of the flush\r
operation.\r
- \r
+\r
@return R9 Unsigned 64-bit integer specifying the vector\r
number of the pending interrupt.\r
- \r
+\r
@return R10 Unsigned 64-bit integer specifying the\r
starting position of the flush operation.\r
- \r
+\r
@return R11 Unsigned 64-bit integer specifying the vector\r
number of the pending interrupt.\r
- \r
+\r
@return Status 2 - Call completed without error, but a PMI\r
was taken during the execution of this\r
procedure.\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error\r
- \r
+\r
**/\r
#define PAL_CACHE_FLUSH 1\r
\r
\r
//\r
// Attributes of PAL_CACHE_CONFIG_INFO1\r
-// \r
+//\r
#define PAL_CACHE_ATTR_WT 0\r
#define PAL_CACHE_ATTR_WB 1\r
\r
//\r
// PAL_CACHE_CONFIG_INFO1.StoreHint\r
-// \r
+//\r
#define PAL_CACHE_STORE_TEMPORAL 0\r
#define PAL_CACHE_STORE_NONE_TEMPORAL 3\r
\r
//\r
// PAL_CACHE_CONFIG_INFO1.StoreHint\r
-// \r
+//\r
#define PAL_CACHE_STORE_TEMPORAL_LVL_1 0\r
#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3\r
\r
//\r
// PAL_CACHE_CONFIG_INFO1.StoreHint\r
-// \r
+//\r
#define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0\r
#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1\r
#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3\r
//\r
// Detail the characteristics of a given processor controlled\r
// cache in the cache hierarchy.\r
-// \r
+//\r
typedef struct {\r
UINT64 IsUnified : 1;\r
UINT64 Attributes : 2;\r
//\r
// Detail the characteristics of a given processor controlled\r
// cache in the cache hierarchy.\r
-// \r
+//\r
typedef struct {\r
UINT64 CacheSize:32;\r
UINT64 AliasBoundary:8;\r
} PAL_CACHE_INFO_RETURN2;\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_CACHE_INFO.\r
- \r
+\r
Return detailed instruction or data cache information. It is\r
required by IPF. The PAL procedure supports the Static\r
Registers calling convention. It could be called at virtual\r
mode and physical mode.\r
- \r
+\r
@param Index Index of PAL_CACHE_INFO within the list of\r
PAL procedures.\r
- \r
+\r
@param CacheLevel Unsigned 64-bit integer specifying the\r
level in the cache hierarchy for which\r
information is requested. This value must\r
be between 0 and one less than the value\r
returned in the cache_levels return value\r
from PAL_CACHE_SUMMARY.\r
- \r
+\r
@param CacheType Unsigned 64-bit integer with a value of 1\r
for instruction cache and 2 for data or\r
unified cache. All other values are\r
reserved.\r
- \r
+\r
@param Reserved Should be 0.\r
- \r
- \r
+\r
+\r
@return R9 Detail the characteristics of a given\r
processor controlled cache in the cache\r
hierarchy. See PAL_CACHE_INFO_RETURN1.\r
- \r
+\r
@return R10 Detail the characteristics of a given\r
processor controlled cache in the cache\r
hierarchy. See PAL_CACHE_INFO_RETURN2.\r
- \r
+\r
@return R11 Reserved with 0.\r
- \r
- \r
+\r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error\r
- \r
+\r
**/\r
#define PAL_CACHE_INFO 2\r
\r
\r
//\r
// Level of PAL_CACHE_INIT.\r
-// \r
+//\r
#define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL\r
\r
//\r
-// CacheType \r
+// CacheType\r
//\r
#define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1\r
#define PAL_CACHE_INIT_TYPE_DATA 0x2\r
\r
//\r
// Restrict of PAL_CACHE_INIT.\r
-// \r
+//\r
#define PAL_CACHE_INIT_NO_RESTRICT 0\r
#define PAL_CACHE_INIT_RESTRICTED 1\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_CACHE_INIT.\r
- \r
+\r
Initialize the instruction or data caches. It is required by\r
IPF. The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_CACHE_INIT within the list of PAL\r
procedures.\r
- \r
+\r
@param Level Unsigned 64-bit integer containing the level of\r
cache to initialize. If the cache level can be\r
initialized independently, only that level will\r
be initialized. Otherwise\r
implementation-dependent side-effects will\r
occur.\r
- \r
+\r
@param CacheType Unsigned 64-bit integer with a value of 1 to\r
initialize the instruction cache, 2 to\r
initialize the data cache, or 3 to\r
level and cache_type of the cache would\r
cause side-effects, PAL_CACHE_INIT will\r
return -4 instead of initializing the cache.\r
- \r
- \r
+\r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -4 - Call could not initialize the specified\r
level and cache_type of the cache without\r
- side-effects and restrict was 1. \r
- \r
+ side-effects and restrict was 1.\r
+\r
**/\r
-#define PAL_CACHE_INIT 3 \r
+#define PAL_CACHE_INIT 3\r
\r
\r
//\r
// PAL_CACHE_PROTECTION.Method.\r
-// \r
+//\r
#define PAL_CACHE_PROTECTION_NONE_PROTECT 0\r
#define PAL_CACHE_PROTECTION_ODD_PROTECT 1\r
#define PAL_CACHE_PROTECTION_EVEN_PROTECT 2\r
\r
//\r
// PAL_CACHE_PROTECTION.TagOrData.\r
-// \r
+//\r
#define PAL_CACHE_PROTECTION_PROTECT_DATA 0\r
#define PAL_CACHE_PROTECTION_PROTECT_TAG 1\r
#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2\r
\r
//\r
// 32-bit protection information structures.\r
-// \r
+//\r
typedef struct {\r
UINT32 DataBits:8;\r
UINT32 TagProtLsb:6;\r
} PAL_CACHE_PROTECTION;\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_CACHE_PROT_INFO.\r
- \r
+\r
Return instruction or data cache protection information. It is\r
required by IPF. The PAL procedure supports the Static\r
Registers calling convention. It could be called at physical\r
for instruction cache and 2 for data or\r
unified cache. All other values are\r
reserved.\r
- \r
+\r
@return R9 Detail the characteristics of a given\r
processor controlled cache in the cache\r
hierarchy. See PAL_CACHE_PROTECTION[0..1].\r
- \r
+\r
@return R10 Detail the characteristics of a given\r
processor controlled cache in the cache\r
hierarchy. See PAL_CACHE_PROTECTION[2..3].\r
- \r
+\r
@return R11 Detail the characteristics of a given\r
processor controlled cache in the cache\r
hierarchy. See PAL_CACHE_PROTECTION[4..5].\r
- \r
- \r
+\r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_CACHE_PROT_INFO 38\r
\r
/**\r
- \r
+\r
@param ThreadId The thread identifier of the logical\r
processor for which information is being\r
returned. This value will be unique on a per\r
} PAL_PCOC_N_CACHE_INFO1;\r
\r
/**\r
- \r
+\r
@param LogicalAddress Logical address: geographical address\r
of the logical processor for which\r
information is being returned. This is\r
} PAL_PCOC_N_CACHE_INFO2;\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_CACHE_SHARED_INFO.\r
- \r
+\r
Returns information on which logical processors share caches.\r
It is optional. The PAL procedure supports the Static\r
Registers calling convention. It could be called at physical\r
mode and Virtual mode.\r
- \r
+\r
@param Index Index of PAL_CACHE_SHARED_INFO within the list\r
of PAL procedures.\r
- \r
+\r
@param CacheLevel Unsigned 64-bit integer specifying the\r
level in the cache hierarchy for which\r
information is requested. This value must\r
be between 0 and one less than the value\r
returned in the cache_levels return value\r
from PAL_CACHE_SUMMARY.\r
- \r
+\r
@param CacheType Unsigned 64-bit integer with a value of 1\r
for instruction cache and 2 for data or\r
unified cache. All other values are\r
reserved.\r
- \r
+\r
@param ProcNumber Unsigned 64-bit integer that specifies for\r
which logical processor information is\r
being requested. This input argument must\r
one less than the number of logical\r
processors sharing this cache, which is\r
returned by the num_shared return value.\r
- \r
+\r
@return R9 Unsigned integer that returns the number of\r
logical processors that share the processor\r
cache level and type, for which information was\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_CACHE_SHARED_INFO 43\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_CACHE_SUMMARY.\r
- \r
+\r
Return a summary of the cache hierarchy. It is required by\r
IPF. The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and Virtual\r
mode.\r
- \r
+\r
@param Index Index of PAL_CACHE_SUMMARY within the list of\r
PAL procedures.\r
\r
- \r
+\r
@return R9 CacheLevels Unsigned 64-bit integer denoting the\r
number of levels of cache\r
implemented by the processor.\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_CACHE_SUMMARY 4\r
\r
\r
//\r
-// Virtual Memory Attributes implemented by processor. \r
-// \r
+// Virtual Memory Attributes implemented by processor.\r
+//\r
#define PAL_MEMORY_ATTR_WB 0\r
#define PAL_MEMORY_ATTR_WC 6\r
#define PAL_MEMORY_ATTR_UC 4\r
#define PAL_MEMORY_ATTR_NATPAGE 7\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_MEM_ATTRIB.\r
- \r
+\r
Return a list of supported memory attributes.. It is required\r
by IPF. The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and Virtual\r
mode.\r
- \r
+\r
@param Index Index of PAL_MEM_ATTRIB within the list of PAL\r
procedures.\r
\r
- \r
+\r
@return R9 Attributes 8-bit vector of memory attributes\r
implemented by processor. See Virtual\r
Memory Attributes above.\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
\r
#define PAL_MEM_ATTRIB 5\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_PREFETCH_VISIBILITY.\r
- \r
+\r
Used in architected sequence to transition pages from a\r
cacheable, speculative attribute to an uncacheable attribute.\r
It is required by IPF. The PAL procedure supports the Static\r
Registers calling convention. It could be called at physical\r
mode and Virtual mode.\r
- \r
+\r
@param Index Index of PAL_PREFETCH_VISIBILITY within the list\r
of PAL procedures.\r
\r
@param TransitionType Unsigned integer specifying the type\r
of memory attribute transition that is\r
being performed.\r
- \r
+\r
@return Status 1 Call completed without error; this\r
call is not necessary on remote\r
processors.\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_PREFETCH_VISIBILITY 41\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_PTCE_INFO.\r
- \r
+\r
Return information needed for ptc.e instruction to purge\r
entire TC. It is required by IPF. The PAL procedure supports\r
the Static Registers calling convention. It could be called at\r
physical mode and Virtual mode.\r
- \r
+\r
@param Index Index of PAL_PTCE_INFO within the list\r
of PAL procedures.\r
\r
@return R9 Unsigned 64-bit integer denoting the beginning\r
address to be used by the first PTCE instruction\r
in the purge loop.\r
- \r
+\r
@return R10 Two unsigned 32-bit integers denoting the loop\r
counts of the outer (loop 1) and inner (loop 2)\r
purge loops. count1 (loop 1) is contained in bits\r
63:32 of the parameter, and count2 (loop 2) is\r
contained in bits 31:0 of the parameter.\r
- \r
+\r
@return R11 Two unsigned 32-bit integers denoting the loop\r
strides of the outer (loop 1) and inner (loop 2)\r
purge loops. stride1 (loop 1) is contained in bits\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_PTCE_INFO 6\r
\r
\r
\r
/**\r
- \r
+\r
@param NumberSets Unsigned 8-bit integer denoting the number\r
of hash sets for the specified level\r
(1=fully associative)\r
} PAL_TC_INFO;\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_VM_INFO.\r
- \r
+\r
Return detailed information about virtual memory features\r
supported in the processor. It is required by IPF. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and Virtual mode.\r
- \r
+\r
@param Index Index of PAL_VM_INFO within the list\r
of PAL procedures.\r
- \r
+\r
@param TcLevel Unsigned 64-bit integer specifying the level\r
in the TLB hierarchy for which information is\r
required. This value must be between 0 and one\r
less than the value returned in the\r
vm_info_1.num_tc_levels return value from\r
PAL_VM_SUMMARY.\r
- \r
+\r
@param TcType Unsigned 64-bit integer with a value of 1 for\r
instruction translation cache and 2 for data\r
or unified translation cache. All other values\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_VM_INFO 7\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_VM_PAGE_SIZE.\r
- \r
+\r
Return virtual memory TC and hardware walker page sizes\r
supported in the processor. It is required by IPF. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and Virtual mode.\r
- \r
+\r
@param Index Index of PAL_VM_PAGE_SIZE within the list\r
of PAL procedures.\r
- \r
+\r
\r
@return R9 64-bit vector containing a bit for each\r
architected page size that is supported for\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_VM_PAGE_SIZE 34\r
\r
/**\r
- \r
+\r
@param WalkerPresent 1-bit flag indicating whether a hardware\r
TLB walker is implemented (1 = walker\r
present).\r
} PAL_VM_INFO1;\r
\r
/**\r
- \r
+\r
@param WidthOfVirtualAddress Unsigned 8-bit integer denoting\r
is the total number of virtual\r
address bits - 1.\r
} PAL_VM_INFO2;\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_VM_SUMMARY.\r
- \r
+\r
Return summary information about virtual memory features\r
supported in the processor. It is required by IPF. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and Virtual mode.\r
- \r
+\r
@param Index Index of PAL_VM_SUMMARY within the list\r
of PAL procedures.\r
- \r
+\r
\r
@return R9 8-byte formatted value returning global virtual\r
memory information. See PAL_VM_INFO1 above.\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_VM_SUMMARY 8\r
\r
\r
//\r
// Bit mask of TR_valid flag.\r
-// \r
+//\r
#define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0\r
#define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1\r
#define PAL_TR_DIRTY_IS_VALID BIT2\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_VM_TR_READ.\r
- \r
+\r
Read contents of a translation register. It is required by\r
IPF. The PAL procedure supports the Stacked Register calling\r
convention. It could be called at physical mode.\r
- \r
+\r
@param Index Index of PAL_VM_TR_READ within the list\r
of PAL procedures.\r
\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
-#define PAL_VM_TR_READ 261 \r
+#define PAL_VM_TR_READ 261\r
\r
\r
\r
\r
//\r
// Bit Mask of Processor Bus Fesatures .\r
-// \r
+//\r
\r
/**\r
- \r
+\r
When 0, bus data errors are detected and single bit errors are\r
corrected. When 1, no error detection or correction is done.\r
\r
\r
\r
/**\r
- \r
+\r
When 0, bus address errors are signalled on the bus. When 1,\r
no bus errors are signalled on the bus. If Disable Bus Address\r
Error Checking is 1, this bit is ignored.\r
\r
\r
/**\r
- \r
+\r
When 0, bus errors are detected, single bit errors are\r
corrected., and a CMCI or MCA is generated internally to the\r
processor. When 1, no bus address errors are detected or\r
\r
\r
/**\r
- \r
+\r
When 0, bus protocol errors (BINIT#) are signaled by the\r
processor on the bus. When 1, bus protocol errors (BINIT#) are\r
not signaled on the bus. If Disable Bus Initialization Event\r
\r
\r
/**\r
- \r
+\r
When 0, bus protocol errors (BINIT#) are detected and sampled\r
and an MCA is generated internally to the processor. When 1,\r
the processor will ignore bus protocol error conditions\r
\r
\r
/**\r
- \r
+\r
When 0, BERR# is signalled if a bus error is detected. When 1,\r
bus errors are not signalled on the bus.\r
\r
\r
\r
/**\r
- \r
+\r
When 0, BERR# is signalled when internal processor requestor\r
initiated bus errors are detected. When 1, internal requester\r
bus errors are not signalled on the bus.\r
- \r
+\r
**/\r
#define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57\r
\r
\r
/**\r
- \r
+\r
When 0, the processor takes an MCA if BERR# is asserted. When\r
1, the processor ignores the BERR# signal.\r
\r
\r
\r
/**\r
- \r
+\r
When 0, the processor asserts BINIT# if it detects a parity\r
error on the signals which identify the transactions to which\r
this is a response. When 1, the processor ignores parity on\r
these signals.\r
- \r
+\r
**/\r
#define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55\r
\r
\r
/**\r
- \r
+\r
When 0, the in-order transaction queue is limited only by the\r
number of hardware entries. When 1, the processor's in-order\r
transactions queue is limited to one entry.\r
#define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54\r
\r
/**\r
- \r
+\r
Enable a bus cache line replacement transaction when a cache\r
line in the exclusive state is replaced from the highest level\r
processor cache and is not present in the lower level processor\r
\r
\r
/**\r
- \r
+\r
Enable a bus cache line replacement transaction when a cache\r
line in the shared or exclusive state is replaced from the\r
highest level processor cache and is not present in the lower\r
#define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52\r
\r
\r
- \r
+\r
/**\r
- \r
+\r
When 0, the data bus is configured at the 2x data transfer\r
rate.When 1, the data bus is configured at the 1x data\r
transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the\r
#define PAL_BUS_ENABLE_HALF_TRANSFER BIT30\r
\r
/**\r
- \r
+\r
When 0, the processor will deassert bus request when finished\r
with each transaction. When 1, the processor will continue to\r
assert bus request after it has finished, if it was the last\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_BUS_GET_FEATURES.\r
- \r
+\r
Return configurable processor bus interface features and their\r
current settings. It is required by IPF. The PAL procedure\r
supports the Stacked Register calling convention. It could be\r
called at physical mode.\r
- \r
+\r
@param Index Index of PAL_BUS_GET_FEATURES within the list\r
of PAL procedures.\r
\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_BUS_GET_FEATURES 9\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_BUS_SET_FEATURES.\r
- \r
+\r
Enable or disable configurable features in processor bus\r
interface. It is required by IPF. It is required by IPF. The PAL procedure\r
supports the Static Registers calling convention. It could be\r
called at physical mode.\r
- \r
+\r
@param Index Index of PAL_BUS_SET_FEATURES within the list\r
of PAL procedures.\r
- \r
+\r
@param FeatureSelect 64-bit vector denoting desired state of\r
each feature (1=select, 0=non-select).\r
\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_BUS_SET_FEATURES 10\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_DEBUG_INFO.\r
- \r
+\r
Return the number of instruction and data breakpoint\r
registers. It is required by IPF. It is required by IPF. The\r
PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and virtual\r
mode.\r
- \r
+\r
@param Index Index of PAL_DEBUG_INFO within the list of PAL\r
procedures.\r
- \r
+\r
@return R9 Unsigned 64-bit integer denoting the number of\r
pairs of instruction debug registers implemented\r
- by the processor. \r
- \r
+ by the processor.\r
+\r
@return R10 Unsigned 64-bit integer denoting the number of\r
pairs of data debug registers implemented by the\r
processor.\r
- \r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_DEBUG_INFO 11\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_FIXED_ADDR.\r
- \r
+\r
Return the fixed component of a processor¡¯s directed address.\r
It is required by IPF. It is required by IPF. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
- \r
+\r
@param Index Index of PAL_FIXED_ADDR within the list of PAL\r
procedures.\r
- \r
- @return R9 Fixed geographical address of this processor. \r
- \r
- \r
+\r
+ @return R9 Fixed geographical address of this processor.\r
+\r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_FIXED_ADDR 12\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_FREQ_BASE.\r
- \r
+\r
Return the frequency of the output clock for use by the\r
platform, if generated by the processor. It is optinal. The\r
PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and virtual\r
mode.\r
- \r
+\r
@param Index Index of PAL_FREQ_BASE within the list of PAL\r
procedures.\r
- \r
+\r
@return R9 Base frequency of the platform if generated by the\r
processor chip.\r
- \r
- \r
+\r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -1 - Unimplemented procedure\r
\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_FREQ_BASE 13\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_FREQ_RATIOS.\r
- \r
+\r
Return ratio of processor, bus, and interval time counter to\r
processor input clock or output clock for platform use, if\r
generated by the processor. It is required by IPF. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
- \r
+\r
@param Index Index of PAL_FREQ_RATIOS within the list of PAL\r
procedures.\r
- \r
+\r
@return R9 Ratio of the processor frequency to the input\r
clock of the processor, if the platform clock is\r
generated externally or to the output clock to the\r
platform, if the platform clock is generated by\r
the processor.\r
- \r
+\r
@return R10 Ratio of the bus frequency to the input clock of\r
the processor, if the platform clock is generated\r
externally or to the output clock to the platform,\r
if the platform clock is generated by the\r
processor.\r
- \r
+\r
@return R11 Ratio of the interval timer counter rate to input\r
clock of the processor, if the platform clock is\r
generated externally or to the output clock to the\r
platform, if the platform clock is generated by\r
the processor.\r
- \r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_FREQ_RATIOS 14\r
\r
/**\r
- \r
+\r
@param NumberOfLogicalProcessors Total number of logical\r
processors on this physical\r
processor package that are\r
} PAL_LOGICAL_PROCESSPR_OVERVIEW;\r
\r
/**\r
- \r
+\r
@param ThreadId The thread identifier of the logical\r
processor for which information is being\r
returned. This value will be unique on a per\r
\r
\r
/**\r
- \r
+\r
@param LogicalAddress Geographical address of the logical\r
processor for which information is being\r
returned. This is the same value that is\r
} PAL_LOGICAL_PROCESSORN_INFO2;\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.\r
- \r
+\r
Return information on which logical processors map to a\r
physical processor die. It is optinal. The PAL procedure\r
supports the Static Registers calling convention. It could be\r
called at physical mode and virtual mode.\r
- \r
+\r
@param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL\r
procedures.\r
- \r
+\r
@param ProcessorNumber Signed 64-bit integer that specifies\r
for which logical processor\r
information is being requested. When\r
the number of logical processors\r
returned by num_log in the\r
log_overview return value.\r
- \r
- \r
+\r
+\r
@return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.\r
- \r
+\r
@return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.\r
- \r
+\r
@return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.\r
- \r
- \r
+\r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_LOGICAL_TO_PHYSICAL 42\r
\r
\r
/**\r
- \r
+\r
@param NumberOfPmcPairs Unsigned 8-bit number defining the\r
number of generic PMC/PMD pairs.\r
\r
} PAL_PERFORMANCE_INFO;\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_PERF_MON_INFO.\r
- \r
+\r
Return the number and type of performance monitors. It is\r
required by IPF. The PAL procedure supports the Static\r
Registers calling convention. It could be called at physical\r
mode and virtual mode.\r
- \r
+\r
@param Index Index of PAL_PERF_MON_INFO within the list of\r
PAL procedures.\r
- \r
+\r
@param PerformanceBuffer An address to an 8-byte aligned\r
128-byte memory buffer.\r
- \r
- \r
+\r
+\r
@return R9 Information about the performance monitors\r
implemented. See PAL_PERFORMANCE_INFO;\r
- \r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_PERF_MON_INFO 15\r
\r
#define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN 0x1\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_PLATFORM_ADDR.\r
- \r
+\r
Specify processor interrupt block address and I/O port space\r
address. It is required by IPF. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode and virtual mode.\r
- \r
+\r
@param Index Index of PAL_PLATFORM_ADDR within the list of\r
PAL procedures.\r
- \r
+\r
@param Type Unsigned 64-bit integer specifying the type of\r
block. 0 indicates that the processor interrupt\r
block pointer should be initialized. 1 indicates\r
that the processor I/O block pointer should be\r
initialized.\r
- \r
+\r
@param Address Unsigned 64-bit integer specifying the address\r
to which the processor I/O block or interrupt\r
block shall be set. The address must specify\r
an implemented physical address on the\r
processor model, bit 63 is ignored.\r
- \r
- \r
+\r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -1 - Unimplemented procedure.\r
- \r
+\r
@return Status -2 - Invalid argument\r
\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_PLATFORM_ADDR 16\r
\r
\r
/**\r
- \r
+\r
@param EnableBerrPromotion Bit63. Enable BERR promotion. When\r
1, the Bus Error (BERR) signal is\r
promoted to the Bus Initialization\r
has no effect if BINIT signalling\r
is disabled. (See\r
PAL_BUS_GET/SET_FEATURES)\r
- \r
+\r
@param EnableMcaPromotion Bit62, Enable MCA promotion. When\r
1, machine check aborts (MCAs) are\r
promoted to the Bus Error signal,\r
} PAL_PROCESSOR_FEATURES;\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_PROC_GET_FEATURES.\r
- \r
+\r
Return configurable processor features and their current\r
setting. It is required by IPF. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode and virtual mode.\r
- \r
+\r
@param Index Index of PAL_PROC_GET_FEATURES within the list of\r
PAL procedures.\r
- \r
+\r
@param Reserved Reserved parameter.\r
- \r
+\r
@param FeatureSet Feature set information is being requested\r
for.\r
- \r
- \r
+\r
+\r
@return R9 64-bit vector of features implemented. See\r
PAL_PROCESSOR_FEATURES.\r
- \r
+\r
@return R10 64-bit vector of current feature settings. See\r
PAL_PROCESSOR_FEATURES.\r
- \r
+\r
@return R11 64-bit vector of features controllable by\r
software.\r
- \r
+\r
@return Status 1 - Call completed without error; The\r
feature_set passed is not supported but a\r
feature_set of a larger value is supported.\r
- \r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -8 - feature_set passed is beyond the maximum\r
feature_set supported\r
- \r
+\r
**/\r
#define PAL_PROC_GET_FEATURES 17\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_PROC_SET_FEATURES.\r
- \r
+\r
Enable or disable configurable processor features. It is\r
required by IPF. The PAL procedure supports the Static\r
Registers calling convention. It could be called at physical\r
mode.\r
- \r
+\r
@param Index Index of PAL_PROC_SET_FEATURES within the list of\r
PAL procedures.\r
- \r
+\r
@param FeatureSelect 64-bit vector denoting desired state of\r
each feature (1=select, 0=non-select).\r
\r
@param FeatureSet Feature set to apply changes to. See\r
PAL_PROC_GET_FEATURES for more information\r
on feature sets.\r
- \r
- \r
- \r
+\r
+\r
+\r
@return Status 1 - Call completed without error; The\r
feature_set passed is not supported but a\r
feature_set of a larger value is supported\r
- \r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -8 - feature_set passed is beyond the maximum\r
feature_set supported\r
- \r
+\r
**/\r
#define PAL_PROC_SET_FEATURES 18\r
\r
\r
//\r
// Value of PAL_REGISTER_INFO.InfoRequest.\r
-// \r
+//\r
#define PAL_APPLICATION_REGISTER_IMPLEMENTED 0\r
#define PAL_APPLICATION_REGISTER_READABLE 1\r
#define PAL_CONTROL_REGISTER_IMPLEMENTED 2\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_REGISTER_INFO.\r
- \r
+\r
Return AR and CR register information. It is required by IPF.\r
The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and virtual\r
mode.\r
- \r
+\r
@param Index Index of PAL_REGISTER_INFO within the list of\r
PAL procedures.\r
- \r
+\r
@param InfoRequest Unsigned 64-bit integer denoting what\r
register information is requested. See\r
PAL_REGISTER_INFO.InfoRequest above.\r
- \r
+\r
@return R9 64-bit vector denoting information for registers\r
0-63. Bit 0 is register 0, bit 63 is register 63.\r
- \r
+\r
@return R10 64-bit vector denoting information for registers\r
64-127. Bit 0 is register 64, bit 63 is register\r
127.\r
- \r
- \r
+\r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
- \r
+\r
+\r
**/\r
-#define PAL_REGISTER_INFO 39 \r
+#define PAL_REGISTER_INFO 39\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_RSE_INFO.\r
- \r
+\r
Return RSE information. It is required by IPF. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
- \r
+\r
@param Index Index of PAL_RSE_INFO within the list of\r
PAL procedures.\r
- \r
+\r
@param InfoRequest Unsigned 64-bit integer denoting what\r
register information is requested. See\r
PAL_REGISTER_INFO.InfoRequest above.\r
- \r
+\r
@return R9 Number of physical stacked general registers.\r
\r
@return R10 RSE hints supported by processor.\r
- \r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
- \r
+\r
+\r
**/\r
#define PAL_RSE_INFO 19\r
\r
/**\r
- \r
+\r
@param VersionOfPalB Is a 16-bit binary coded decimal (BCD)\r
number that provides identification\r
information about the PAL_B firmware.\r
} PAL_VERSION_INFO;\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_VERSION.\r
- \r
+\r
Return version of PAL code. It is required by IPF. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
- \r
+\r
@param Index Index of PAL_VERSION within the list of\r
PAL procedures.\r
- \r
+\r
@param InfoRequest Unsigned 64-bit integer denoting what\r
register information is requested. See\r
PAL_REGISTER_INFO.InfoRequest above.\r
- \r
+\r
@return R9 8-byte formatted value returning the minimum PAL\r
version needed for proper operation of the\r
processor. See PAL_VERSION_INFO above.\r
- \r
+\r
@return R10 8-byte formatted value returning the current PAL\r
version running on the processor. See\r
PAL_VERSION_INFO above.\r
- \r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
- \r
+\r
+\r
**/\r
#define PAL_VERSION 20\r
\r
\r
//\r
// Vectors of PAL_MC_CLEAR_LOG.pending\r
-// \r
+//\r
#define PAL_MC_PENDING BIT0\r
#define PAL_INIT_PENDING BIT1\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_MC_CLEAR_LOG.\r
- \r
+\r
Clear all error information from processor error logging\r
registers. It is required by IPF. The PAL procedure supports\r
the Static Registers calling convention. It could be called at\r
physical mode and virtual mode.\r
- \r
+\r
@param Index Index of PAL_MC_CLEAR_LOG within the list of\r
PAL procedures.\r
- \r
- \r
+\r
+\r
@return R9 64-bit vector denoting whether an event is\r
pending. See PAL_MC_CLEAR_LOG.pending above.\r
- \r
- \r
+\r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
- \r
+\r
+\r
**/\r
-#define PAL_MC_CLEAR_LOG 21 \r
+#define PAL_MC_CLEAR_LOG 21\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_MC_DRAIN.\r
- \r
+\r
Ensure that all operations that could cause an MCA have\r
completed. It is required by IPF. The PAL procedure supports\r
the Static Registers calling convention. It could be called at\r
physical mode and virtual mode.\r
- \r
+\r
@param Index Index of PAL_MC_DRAIN within the list of PAL\r
procedures.\r
- \r
- \r
+\r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
- \r
+\r
+\r
**/\r
#define PAL_MC_DRAIN 22\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_MC_DYNAMIC_STATE.\r
- \r
+\r
Return Processor Dynamic State for logging by SAL. It is\r
optional. The PAL procedure supports the Static Registers\r
calling convention. It could be called at physical mode.\r
- \r
+\r
@param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL\r
procedures.\r
- \r
+\r
@param Offset Offset of the next 8 bytes of Dynamic Processor\r
State to return. (multiple of 8).\r
- \r
+\r
@return R9 Unsigned 64-bit integer denoting bytes of Dynamic\r
Processor State returned.\r
- \r
+\r
@return R10 Next 8 bytes of Dynamic Processor State.\r
- \r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -1 - Unimplemented procedure.\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
- \r
+\r
+\r
**/\r
-#define PAL_MC_DYNAMIC_STATE 24 \r
+#define PAL_MC_DYNAMIC_STATE 24\r
\r
\r
\r
//\r
// Values of PAL_MC_ERROR_INFO.InfoIndex.\r
-// \r
+//\r
#define PAL_PROCESSOR_ERROR_MAP 0\r
#define PAL_PROCESSOR_STATE_PARAM 1\r
#define PAL_STRUCTURE_SPECIFIC_ERROR 2\r
\r
/**\r
- \r
+\r
@param CoreId Bit3:0, Processor core ID (default is 0 for\r
processors with a single core)\r
\r
@param ThreadId Bit7:4, Logical thread ID (default is 0 for\r
- processors that execute a single thread) \r
+ processors that execute a single thread)\r
\r
@param InfoOfInsCache Bit11:8, Error information is\r
available for 1st, 2nd, 3rd, and 4th\r
\r
//\r
// Value of PAL_MC_ERROR_INFO.ErrorTypeIndex\r
-// \r
+//\r
#define PAL_ERR_INFO_BY_LEVEL_INDEX 0\r
#define PAL_ERR_INFO_TARGET_ADDRESS 1\r
#define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2\r
prefetch (both hardware and software) 5 -\r
snoop (coherency check) 6 - cast out\r
(explicit or implicit write-back of a cache\r
- line) 7 - move in (cache line fill) \r
+ line) 7 - move in (cache line fill)\r
\r
@param FailedCacheLevel Bit5:4 Level of cache where the\r
error occurred. A value of 0\r
@param MultipleBitsError Bit23, A multiple-bit error was\r
detected, and data was poisoned for\r
the corresponding cache line during\r
- castout. \r
+ castout.\r
\r
@param IndexOfCacheLineError Bit51:32, Index of the cache\r
line where the error occurred.\r
} PAL_CACHE_CHECK_INFO;\r
\r
/**\r
- \r
+\r
@param FailedSlot Bit7:0, Slot number of the translation\r
register where the failure occurred.\r
\r
\r
@param TlbLevel Bit11:10, The level of the TLB where the\r
error occurred. A value of 0 indicates the\r
- first level of TLB \r
+ first level of TLB\r
\r
@param FailedInDataTr Bit16, Error occurred in the data\r
translation registers.\r
} PAL_TLB_CHECK_INFO;\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_MC_ERROR_INFO.\r
- \r
+\r
Return Processor Machine Check Information and Processor\r
Static State for logging by SAL. It is required by IPF. The\r
PAL procedure supports the Static Registers calling\r
convention. It could be called at physical and virtual mode.\r
- \r
+\r
@param Index Index of PAL_MC_ERROR_INFO within the list of PAL\r
procedures.\r
- \r
+\r
@param InfoIndex Unsigned 64-bit integer identifying the\r
error information that is being requested.\r
See PAL_MC_ERROR_INFO.InfoIndex.\r
- \r
+\r
@param LevelIndex 8-byte formatted value identifying the\r
structure to return error information\r
on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.\r
- \r
+\r
@param ErrorTypeIndex Unsigned 64-bit integer denoting the\r
type of error information that is\r
being requested for the structure\r
identified in LevelIndex.\r
- \r
- \r
+\r
+\r
@return R9 Error information returned. The format of this\r
value is dependant on the input values passed.\r
- \r
+\r
@return R10 If this value is zero, all the error information\r
specified by err_type_index has been returned. If\r
this value is one, more structure-specific error\r
information is available and the caller needs to\r
make this procedure call again with level_index\r
unchanged and err_type_index, incremented.\r
- \r
- \r
+\r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -6 - Argument was valid, but no error\r
information was available\r
- \r
- \r
+\r
+\r
**/\r
#define PAL_MC_ERROR_INFO 25\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_MC_EXPECTED.\r
- \r
+\r
Set/Reset Expected Machine Check Indicator. It is required by\r
IPF. The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode.\r
- \r
+\r
@param Index Index of PAL_MC_EXPECTED within the list of PAL\r
procedures.\r
- \r
+\r
@param Expected Unsigned integer with a value of 0 or 1 to\r
set or reset the hardware resource\r
PALE_CHECK examines for expected machine\r
checks.\r
- \r
+\r
\r
@return R9 Unsigned integer denoting whether a machine check\r
was previously expected.\r
- \r
+\r
\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
**/\r
-#define PAL_MC_EXPECTED 23 \r
+#define PAL_MC_EXPECTED 23\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_MC_REGISTER_MEM.\r
- \r
+\r
Register min-state save area with PAL for machine checks and\r
inits. It is required by IPF. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode.\r
- \r
+\r
@param Index Index of PAL_MC_REGISTER_MEM within the list of PAL\r
procedures.\r
- \r
+\r
@param Address Physical address of the buffer to be\r
registered with PAL.\r
- \r
\r
- \r
+\r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
**/\r
-#define PAL_MC_REGISTER_MEM 27 \r
+#define PAL_MC_REGISTER_MEM 27\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_MC_RESUME.\r
- \r
+\r
Restore minimal architected state and return to interrupted\r
process. It is required by IPF. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode.\r
- \r
+\r
@param Index Index of PAL_MC_RESUME within the list of PAL\r
procedures.\r
- \r
+\r
@param SetCmci Unsigned 64 bit integer denoting whether to\r
set the CMC interrupt. A value of 0 indicates\r
not to set the interrupt, a value of 1\r
returning to the interrupted context, a\r
value of 1 indicates that the caller is\r
returning to a new context.\r
- \r
\r
- \r
+\r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
**/\r
-#define PAL_MC_RESUME 26 \r
+#define PAL_MC_RESUME 26\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_HALT.\r
- \r
+\r
Enter the low-power HALT state or an implementation-dependent\r
low-power state. It is optinal. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode.\r
- \r
+\r
@param Index Index of PAL_HALT within the list of PAL\r
procedures.\r
- \r
+\r
@param HaltState Unsigned 64-bit integer denoting low power\r
state requested.\r
\r
@return R9 Value returned if a load instruction is requested\r
in the io_detail_ptr\r
\r
- \r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -1 - Unimplemented procedure\r
\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
**/\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_HALT_INFO.\r
- \r
+\r
Return the low power capabilities of the processor. It is\r
required by IPF. The PAL procedure supports the\r
Stacked Registers calling convention. It could be called at\r
physical and virtual mode.\r
- \r
+\r
@param Index Index of PAL_HALT_INFO within the list of PAL\r
procedures.\r
- \r
+\r
@param PowerBuffer 64-bit pointer to a 64-byte buffer aligned\r
on an 8-byte boundary.\r
\r
\r
- \r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
**/\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_HALT_LIGHT.\r
- \r
+\r
Enter the low power LIGHT HALT state. It is required by\r
IPF. The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical and virtual mode.\r
- \r
+\r
@param Index Index of PAL_HALT_LIGHT within the list of PAL\r
procedures.\r
- \r
- \r
+\r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
**/\r
-#define PAL_HALT_LIGHT 29 \r
+#define PAL_HALT_LIGHT 29\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_CACHE_LINE_INIT.\r
- \r
+\r
Initialize tags and data of a cache line for processor\r
testing. It is required by IPF. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical and virtual mode.\r
- \r
+\r
@param Index Index of PAL_CACHE_LINE_INIT within the list of PAL\r
procedures.\r
- \r
+\r
@param Address Unsigned 64-bit integer value denoting the\r
physical address from which the physical page\r
number is to be generated. The address must be\r
an implemented physical address, bit 63 must\r
be zero.\r
- \r
+\r
@param DataValue 64-bit data value which is used to\r
initialize the cache line.\r
- \r
- \r
+\r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
**/\r
#define PAL_CACHE_LINE_INIT 31\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_CACHE_READ.\r
- \r
+\r
Read tag and data of a cache line for diagnostic testing. It\r
is optional. The PAL procedure supports the\r
Satcked Registers calling convention. It could be called at\r
physical mode.\r
- \r
+\r
@param Index Index of PAL_CACHE_READ within the list of PAL\r
procedures.\r
- \r
+\r
@param LineId 8-byte formatted value describing where in the\r
cache to read the data.\r
\r
@return R11 The status of the cache line.\r
\r
\r
- \r
+\r
@return Status 1 - The word at address was found in the\r
cache, but the line was invalid.\r
\r
@return Status 0 - Call completed without error\r
\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
@return Status -5 - The word at address was not found in the\r
cache.\r
- \r
+\r
@return Status -7 - The operation requested is not supported\r
for this cache_type and level.\r
\r
**/\r
-#define PAL_CACHE_READ 259 \r
+#define PAL_CACHE_READ 259\r
\r
\r
/**\r
- \r
+\r
Write tag and data of a cache for diagnostic testing. It is\r
optional. The PAL procedure supports the Satcked Registers\r
calling convention. It could be called at physical mode.\r
- \r
+\r
@param Index Index of PAL_CACHE_WRITE within the list of PAL\r
procedures.\r
- \r
+\r
@param LineId 8-byte formatted value describing where in the\r
cache to write the data.\r
\r
@param Data Unsigned 64-bit integer value to write into\r
the specified part of the cache.\r
\r
- \r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
- \r
+\r
@return Status -7 - The operation requested is not supported\r
for this cache_type and level.\r
\r
#define PAL_CACHE_WRITE 260\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_TEST_INFO.\r
- \r
+\r
Returns alignment and size requirements needed for the memory\r
buffer passed to the PAL_TEST_PROC procedure as well as\r
information on self-test control words for the processor self\r
tests. It is required by IPF. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode.\r
- \r
+\r
@param Index Index of PAL_TEST_INFO within the list of PAL\r
procedures.\r
- \r
+\r
@param TestPhase Unsigned integer that specifies which phase\r
of the processor self-test information is\r
being requested on. A value of 0 indicates\r
a value of 1 indicates phase one of the\r
processor self-test. All other values are\r
reserved.\r
- \r
+\r
@return R9 Unsigned 64-bit integer denoting the number of\r
bytes of main memory needed to perform the second\r
phase of processor self-test.\r
- \r
+\r
@return R10 Unsigned 64-bit integer denoting the alignment\r
required for the memory buffer.\r
- \r
+\r
@return R11 48-bit wide bit-field indicating if control of\r
the processor self-tests is supported and which\r
bits of the test_control field are defined for\r
use.\r
\r
- \r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
\r
} PAL_TEST_INFO_INFO;\r
\r
/**\r
- \r
+\r
@param TestControl This is an ordered implementation-specific\r
control word that allows the user control\r
over the length and runtime of the\r
} PAL_SELF_TEST_CONTROL;\r
\r
/**\r
- \r
+\r
@param Attributes Specifies the memory attributes that are\r
allowed to be used with the memory buffer\r
passed to this procedure. The attributes\r
} PAL_TEST_CONTROL;\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_TEST_PROC.\r
- \r
+\r
Perform late processor self test. It is required by IPF. The\r
PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode.\r
- \r
+\r
@param Index Index of PAL_TEST_PROC within the list of PAL\r
procedures.\r
- \r
+\r
@param TestAddress 64-bit physical address of main memory\r
area to be used by processor self-test.\r
The memory region passed must be\r
control word and the allowable memory\r
attributes that can be used with the memory\r
buffer. See PAL_TEST_CONTROL.\r
- \r
+\r
@return R9 Formatted 8-byte value denoting the state of the\r
processor after self-test\r
- \r
- \r
- \r
+\r
+\r
+\r
@return Status 1 - Call completed without error, but hardware\r
failures occurred during self-test.\r
- \r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
\r
#define PAL_TEST_PROC 258\r
\r
/**\r
- \r
+\r
@param NumberOfInterruptControllers Number of interrupt\r
controllers currently\r
enabled on the system.\r
} PAL_PLATFORM_INFO;\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_COPY_INFO.\r
- \r
+\r
Return information needed to relocate PAL procedures and PAL\r
PMI code to memory. It is required by IPF. The PAL procedure\r
supports the Static Registers calling convention. It could be\r
called at physical mode.\r
- \r
+\r
@param Index Index of PAL_COPY_INFO within the list of PAL\r
procedures.\r
- \r
+\r
@param CopyType Unsigned integer denoting type of procedures\r
for which copy information is requested.\r
\r
processor.\r
\r
\r
- \r
+\r
@return R9 Unsigned integer denoting the number of bytes of\r
PAL information that must be copied to main\r
memory.\r
\r
@return R10 Unsigned integer denoting the starting alignment\r
of the data to be copied.\r
- \r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
\r
#define PAL_COPY_INFO 30\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_COPY_PAL.\r
- \r
+\r
Relocate PAL procedures and PAL PMI code to memory. It is\r
required by IPF. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at physical\r
mode.\r
- \r
+\r
@param Index Index of PAL_COPY_PAL within the list of PAL\r
procedures.\r
- \r
+\r
@param TargetAddress Physical address of a memory buffer to\r
copy relocatable PAL procedures and PAL\r
PMI code.\r
should be copied from firmware address\r
space to main memory.\r
\r
- \r
+\r
@return R9 Unsigned integer denoting the offset of PAL_PROC\r
in the relocatable segment copied.\r
- \r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
\r
#define PAL_COPY_PAL 256\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_ENTER_IA_32_ENV.\r
- \r
+\r
Enter IA-32 System environment. It is optional. The PAL\r
procedure supports the Static Registers calling convention.\r
It could be called at physical mode.\r
- \r
+\r
Note: Since this is a special call, it does not follow the PAL\r
- static register calling convention. GR28 contains the index of \r
- PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other \r
- input arguments including GR29-GR31 are setup by SAL to values \r
- as required by the IA-32 operating system defined in Table \r
- 11-67. The registers that are designated as preserved, scratch, \r
- input arguments and procedure return values by the static \r
- procedure calling convention are not followed by this call. For \r
- instance, GR5 and GR6 need not be preserved since these are \r
- regarded as scratch by the IA-32 operating system. Note: In an \r
- MP system, this call must be COMPLETED on the first CPU to enter \r
- the IA-32 System Environment (may or may not be the BSP) prior \r
- to being called on the remaining processors in the MP system. \r
- \r
+ static register calling convention. GR28 contains the index of\r
+ PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other\r
+ input arguments including GR29-GR31 are setup by SAL to values\r
+ as required by the IA-32 operating system defined in Table\r
+ 11-67. The registers that are designated as preserved, scratch,\r
+ input arguments and procedure return values by the static\r
+ procedure calling convention are not followed by this call. For\r
+ instance, GR5 and GR6 need not be preserved since these are\r
+ regarded as scratch by the IA-32 operating system. Note: In an\r
+ MP system, this call must be COMPLETED on the first CPU to enter\r
+ the IA-32 System Environment (may or may not be the BSP) prior\r
+ to being called on the remaining processors in the MP system.\r
+\r
@param Index GR28 contains the index of the\r
PAL_ENTER_IA_32_ENV call within the list of PAL\r
procedures.\r
- \r
- \r
+\r
+\r
@return Status The status is returned in GR4.\r
-1 - Un-implemented procedure 0 JMPE detected\r
at privilege level\r
- \r
+\r
0 - 1 SAL allocated buffer for IA-32 System\r
Environment operation is too small\r
- \r
+\r
2 - IA-32 Firmware Checksum Error\r
- \r
+\r
3 - SAL allocated buffer for IA-32 System\r
Environment operation is not properly aligned\r
- \r
+\r
4 - Error in SAL MP Info Table\r
- \r
+\r
5 - Error in SAL Memory Descriptor Table\r
- \r
+\r
6 - Error in SAL System Table\r
- \r
+\r
7 - Inconsistent IA-32 state\r
- \r
+\r
8 - IA-32 Firmware Internal Error\r
- \r
+\r
9 - IA-32 Soft Reset (Note: remaining register\r
state is undefined for this termination\r
reason)\r
- \r
+\r
10 - Machine Check Error\r
- \r
- 11 - Error in SAL I/O Intercept Table \r
- \r
+\r
+ 11 - Error in SAL I/O Intercept Table\r
+\r
12 - Processor exit due to other processor in\r
MP system terminating the IA32 system\r
environment. (Note: remaining register state\r
is undefined for this termination reason.)\r
- \r
+\r
13 - Itanium architecture-based state\r
corruption by either SAL PMI handler or I/O\r
Intercept callback function.\r
#define PAL_ENTER_IA_32_ENV 33\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_PMI_ENTRYPOINT.\r
- \r
+\r
Register PMI memory entrypoints with processor. It is required\r
by IPF. The PAL procedure supports the Stacked Registers\r
calling convention. It could be called at physical mode.\r
- \r
+\r
@param Index Index of PAL_PMI_ENTRYPOINT within the list of\r
PAL procedures.\r
- \r
+\r
@param SalPmiEntry 256-byte aligned physical address of SAL\r
PMI entrypoint in memory.\r
\r
- \r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
\r
\r
\r
/**\r
- \r
+\r
The ASCII brand identification string will be copied to the\r
address specified in the address input argument. The processor\r
brand identification string is defined to be a maximum of 128\r
return argument.\r
\r
**/\r
-#define PAL_BRAND_INFO_ID_REQUEST 0 \r
+#define PAL_BRAND_INFO_ID_REQUEST 0\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_BRAND_INFO.\r
- \r
+\r
Provides processor branding information. It is optional by\r
IPF. The PAL procedure supports the Stacked Registers calling\r
convention. It could be called at physical and Virtual mode.\r
\r
@param Index Index of PAL_BRAND_INFO within the list of PAL\r
procedures.\r
- \r
+\r
@param InfoRequest Unsigned 64-bit integer specifying the\r
information that is being requested. (See\r
PAL_BRAND_INFO_ID_REQUEST)\r
@reture R9 Brand information returned. The format of this\r
value is dependent on the input values passed.\r
\r
- \r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
@return Status -6 - Input argument is not implemented.\r
- \r
+\r
**/\r
#define PAL_BRAND_INFO 274\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_GET_HW_POLICY.\r
- \r
+\r
Returns the current hardware resource sharing policy of the\r
processor. It is optional by IPF. The PAL procedure supports\r
the Static Registers calling convention. It could be called at\r
\r
@param Index Index of PAL_GET_HW_POLICY within the list of PAL\r
procedures.\r
- \r
+\r
@param ProcessorNumber Unsigned 64-bit integer that specifies\r
for which logical processor\r
information is being requested. This\r
\r
@reture R9 Unsigned 64-bit integer representing the current\r
hardware resource sharing policy.\r
- \r
+\r
@return R10 Unsigned 64-bit integer that returns the number\r
of logical processors impacted by the policy\r
input argument.\r
- \r
+\r
@return R11 Unsigned 64-bit integer containing the logical\r
address of one of the logical processors\r
- impacted by policy modification. \r
- \r
- \r
+ impacted by policy modification.\r
+\r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
@return Status -9 - Call requires PAL memory buffer.\r
- \r
+\r
**/\r
#define PAL_GET_HW_POLICY 48\r
\r
\r
//\r
// Value of PAL_SET_HW_POLICY.Policy\r
-// \r
+//\r
#define PAL_SET_HW_POLICY_PERFORMANCE 0\r
#define PAL_SET_HW_POLICY_FAIRNESS 1\r
#define PAL_SET_HW_POLICY_HIGH_PRIORITY 2\r
#define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_SET_HW_POLICY.\r
- \r
+\r
Sets the current hardware resource sharing policy of the\r
processor. It is optional by IPF. The PAL procedure supports\r
the Static Registers calling convention. It could be called at\r
\r
@param Index Index of PAL_SET_HW_POLICY within the list of PAL\r
procedures.\r
- \r
+\r
@param Policy Unsigned 64-bit integer specifying the hardware\r
resource sharing policy the caller is setting.\r
See Value of PAL_SET_HW_POLICY.Policy above.\r
\r
- \r
+\r
@return Status 1 - Call completed successfully but could not\r
change the hardware policy since a\r
competing logical processor is set in\r
@return Status 0 - Call completed without error\r
\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
\r
@return Status -9 - Call requires PAL memory buffer.\r
- \r
+\r
**/\r
#define PAL_SET_HW_POLICY 49\r
\r
} PAL_MC_ERROR_TYPE_INFO;\r
\r
/**\r
- \r
+\r
@param StructInfoIsValid Bit0 When 1, indicates that the\r
structure information fields\r
(c_t,cl_p,cl_id) are valid and\r
(corrected error) when this bit\r
is set.\r
\r
- \r
+\r
@param TrigerInfoIsValid Bit32 When 1, indicates that the\r
trigger information fields (trigger,\r
trigger_pl) are valid and should be\r
} PAL_MC_ERROR_STRUCT_INFO;\r
\r
/**\r
- \r
+\r
Buffer Pointed to by err_data_buffer ¨C TLB\r
- \r
+\r
**/\r
typedef struct {\r
UINT64 TrigerAddress;\r
} PAL_MC_ERROR_DATA_BUFFER_TLB;\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_MC_ERROR_INJECT.\r
- \r
+\r
Injects the requested processor error or returns information\r
on the supported injection capabilities for this particular\r
processor implementation. It is optional by IPF. The PAL\r
\r
@param Index Index of PAL_MC_ERROR_INJECT within the list of PAL\r
procedures.\r
- \r
+\r
@param ErrorTypeInfo Unsigned 64-bit integer specifying the\r
first level error information which\r
identifies the error structure and\r
providing additional parameters for\r
the requested error. The address of\r
this buffer must be 8-byte aligned.\r
- \r
+\r
@return R9 64-bit vector specifying the supported error\r
injection capabilities for the input argument\r
combination of struct_hier, err_struct and\r
err_sev fields in ErrorTypeInfo.\r
- \r
+\r
@return R10 64-bit vector specifying the architectural\r
resources that are used by the procedure.\r
- \r
- \r
+\r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -4 - Call completed with error; the requested\r
error could not be injected due to failure in\r
locating the target location in the specified\r
structure.\r
- \r
+\r
@return Status -5 - Argument was valid, but requested error\r
injection capability is not supported.\r
\r
\r
//\r
// Types of PAL_GET_PSTATE.Type\r
-// \r
+//\r
#define PAL_GET_PSTATE_RECENT 0\r
#define PAL_GET_PSTATE_AVERAGE_NEW_START 1\r
#define PAL_GET_PSTATE_AVERAGE 2\r
#define PAL_GET_PSTATE_NOW 3\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_GET_PSTATE.\r
- \r
+\r
Returns the performance index of the processor. It is optional\r
by IPF. The PAL procedure supports the Stacked Registers\r
calling convention. It could be called at physical and Virtual\r
\r
@param Index Index of PAL_GET_PSTATE within the list of PAL\r
procedures.\r
- \r
+\r
@param Type Type of performance_index value to be returned\r
by this procedure.See PAL_GET_PSTATE.Type above.\r
\r
- \r
+\r
@return R9 Unsigned integer denoting the processor\r
performance for the time duration since the last\r
PAL_GET_PSTATE procedure call was made. The\r
value returned is between 0 and 100, and is\r
relative to the performance index of the highest\r
available P-state.\r
- \r
+\r
@return Status 1 - Call completed without error, but accuracy\r
of performance index has been impacted by a\r
thermal throttling event, or a\r
hardware-initiated event.\r
- \r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -9 - Call requires PAL memory buffer.\r
- \r
+\r
**/\r
#define PAL_GET_PSTATE 262\r
\r
/**\r
- \r
+\r
Layout of PAL_PSTATE_INFO.PStateBuffer\r
- \r
+\r
**/\r
typedef struct {\r
UINT32 PerformanceIndex:7;\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_PSTATE_INFO.\r
- \r
+\r
Returns information about the P-states supported by the\r
processor. It is optional by IPF. The PAL procedure supports\r
the Static Registers calling convention. It could be called\r
\r
@param Index Index of PAL_PSTATE_INFO within the list of PAL\r
procedures.\r
- \r
+\r
@param PStateBuffer 64-bit pointer to a 256-byte buffer\r
aligned on an 8-byte boundary. See\r
PAL_PSTATE_INFO_BUFFER above.\r
\r
- \r
+\r
@return R9 Unsigned integer denoting the number of P-states\r
supported. The maximum value of this field is 16.\r
\r
@return R10 Dependency domain information\r
\r
- \r
+\r
@return Status 0 - Call completed without error\r
\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
**/\r
#define PAL_PSTATE_INFO 44\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_SET_PSTATE.\r
- \r
+\r
To request a processor transition to a given P-state. It is\r
optional by IPF. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at physical\r
\r
@param Index Index of PAL_SET_PSTATE within the list of PAL\r
procedures.\r
- \r
+\r
@param PState Unsigned integer denoting the processor\r
P-state being requested.\r
- \r
+\r
@param ForcePState Unsigned integer denoting whether the\r
P-state change should be forced for the\r
logical processor.\r
\r
\r
\r
- \r
- \r
+\r
+\r
@return Status 1 - Call completed without error, but\r
transition request was not accepted\r
- \r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -9 - Call requires PAL memory buffer.\r
- \r
+\r
**/\r
#define PAL_SET_PSTATE 263\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_SHUTDOWN.\r
- \r
+\r
Put the logical processor into a low power state which can be\r
exited only by a reset event. It is optional by IPF. The PAL\r
procedure supports the Static Registers calling convention. It\r
\r
@param Index Index of PAL_SHUTDOWN within the list of PAL\r
procedures.\r
- \r
+\r
@param NotifyPlatform 8-byte aligned physical address\r
pointer providing details on how to\r
optionally notify the platform that\r
the processor is entering a shutdown\r
state.\r
- \r
+\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -9 - Call requires PAL memory buffer.\r
- \r
+\r
**/\r
#define PAL_SHUTDOWN 45\r
\r
/**\r
\r
Layout of PAL_MEMORY_BUFFER.ControlWord\r
- \r
+\r
**/\r
typedef struct {\r
UINT64 Registration:1;\r
} PAL_MEMORY_CONTROL_WORD;\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_MEMORY_BUFFER.\r
- \r
+\r
Provides cacheable memory to PAL for exclusive use during\r
runtime. It is optional by IPF. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
\r
@param Index Index of PAL_MEMORY_BUFFER within the list of PAL\r
procedures.\r
- \r
+\r
@param BaseAddress Physical address of the memory buffer\r
allocated for PAL use.\r
- \r
+\r
@param AllocSize Unsigned integer denoting the size of the\r
memory buffer.\r
- \r
+\r
@param ControlWord Formatted bit vector that provides control\r
options for this procedure. See\r
PAL_MEMORY_CONTROL_WORD above.\r
- \r
+\r
@return R9 Returns the minimum size of the memory buffer\r
required if the alloc_size input argument was\r
not large enough.\r
- \r
+\r
@return Status 1 - Call has not completed a buffer relocation\r
due to a pending interrupt\r
- \r
+\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -9 - Call requires PAL memory buffer.\r
- \r
+\r
**/\r
#define PAL_MEMORY_BUFFER 277\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_VP_CREATE.\r
- \r
+\r
Initializes a new vpd for the operation of a new virtual\r
processor in the virtual environment. It is optional by IPF.\r
The PAL procedure supports the Stacked Registers calling\r
\r
@param Index Index of PAL_VP_CREATE within the list of PAL\r
procedures.\r
- \r
+\r
@param Vpd 64-bit host virtual pointer to the Virtual\r
Processor Descriptor (VPD).\r
\r
@param OptionalHandler 64-bit non-zero host-virtual pointer\r
to an optional handler for\r
virtualization intercepts.\r
- \r
+\r
\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -9 - Call requires PAL memory buffer.\r
- \r
+\r
**/\r
#define PAL_VP_CREATE 265\r
\r
/**\r
- \r
- Virtual Environment Information Parameter \r
- \r
+\r
+ Virtual Environment Information Parameter\r
+\r
**/\r
typedef struct {\r
UINT64 Reserved1:8;\r
} PAL_VP_ENV_INFO_RETURN;\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_VP_ENV_INFO.\r
- \r
+\r
Returns the parameters needed to enter a virtual environment.\r
It is optional by IPF. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at Virtual\r
\r
@param Index Index of PAL_VP_ENV_INFO within the list of PAL\r
procedures.\r
- \r
+\r
@param Vpd 64-bit host virtual pointer to the Virtual\r
Processor Descriptor (VPD).\r
\r
@return R9 Unsigned integer denoting the number of bytes\r
required by the PAL virtual environment buffer\r
during PAL_VP_INIT_ENV\r
- \r
+\r
@return R10 64-bit vector of virtual environment\r
information. See PAL_VP_ENV_INFO_RETURN.\r
- \r
+\r
\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -9 - Call requires PAL memory buffer.\r
- \r
+\r
**/\r
#define PAL_VP_ENV_INFO 266\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_VP_EXIT_ENV.\r
- \r
- Allows a logical processor to exit a virtual environment. \r
+\r
+ Allows a logical processor to exit a virtual environment.\r
It is optional by IPF. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at Virtual\r
mode.\r
\r
@param Index Index of PAL_VP_EXIT_ENV within the list of PAL\r
procedures.\r
- \r
+\r
@param Iva Optional 64-bit host virtual pointer to the IVT\r
when this procedure is done\r
\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -9 - Call requires PAL memory buffer.\r
- \r
+\r
**/\r
#define PAL_VP_EXIT_ENV 267\r
\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_VP_INIT_ENV.\r
- \r
+\r
Allows a logical processor to enter a virtual environment. It\r
is optional by IPF. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at Virtual\r
\r
@param Index Index of PAL_VP_INIT_ENV within the list of PAL\r
procedures.\r
- \r
+\r
@param ConfigOptions 64-bit vector of global configuration\r
settings.\r
\r
the virtual base address of the PAL\r
virtualization services in this virtual\r
environment.\r
- \r
+\r
\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -9 - Call requires PAL memory buffer.\r
- \r
+\r
**/\r
#define PAL_VP_INIT_ENV 268\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_VP_REGISTER.\r
- \r
+\r
Register a different host IVT and/or a different optional\r
virtualization intercept handler for the virtual processor\r
specified by vpd. It is optional by IPF. The PAL procedure\r
\r
@param Index Index of PAL_VP_REGISTER within the list of PAL\r
procedures.\r
- \r
+\r
@param Vpd 64-bit host virtual pointer to the Virtual\r
Processor Descriptor (VPD) host_iva 64-bit host\r
virtual pointer to the host IVT for the virtual\r
\r
\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -9 - Call requires PAL memory buffer.\r
- \r
+\r
**/\r
#define PAL_VP_REGISTER 269\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_VP_RESTORE.\r
- \r
+\r
Restores virtual processor state for the specified vpd on the\r
logical processor. It is optional by IPF. The PAL procedure\r
supports the Stacked Registers calling convention. It could be\r
\r
@param Index Index of PAL_VP_RESTORE within the list of PAL\r
procedures.\r
- \r
+\r
@param Vpd 64-bit host virtual pointer to the Virtual\r
Processor Descriptor (VPD) host_iva 64-bit host\r
virtual pointer to the host IVT for the virtual\r
\r
\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -9 - Call requires PAL memory buffer.\r
- \r
+\r
**/\r
#define PAL_VP_RESTORE 270\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_VP_SAVE.\r
- \r
+\r
Saves virtual processor state for the specified vpd on the\r
logical processor. It is optional by IPF. The PAL procedure\r
supports the Stacked Registers calling convention. It could be\r
\r
@param Index Index of PAL_VP_SAVE within the list of PAL\r
procedures.\r
- \r
+\r
@param Vpd 64-bit host virtual pointer to the Virtual\r
Processor Descriptor (VPD) host_iva 64-bit host\r
virtual pointer to the host IVT for the virtual\r
\r
\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -9 - Call requires PAL memory buffer.\r
- \r
+\r
**/\r
#define PAL_VP_SAVE 271\r
\r
\r
/**\r
- \r
+\r
PAL Procedure - PAL_VP_TERMINATE.\r
- \r
+\r
Terminates operation for the specified virtual processor. It\r
is optional by IPF. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at Virtual\r
\r
@param Index Index of PAL_VP_TERMINATE within the list of PAL\r
procedures.\r
- \r
+\r
@param Vpd 64-bit host virtual pointer to the Virtual\r
Processor Descriptor (VPD)\r
- \r
+\r
@param Iva Optional 64-bit host virtual pointer to the IVT\r
when this procedure is done.\r
\r
@return Status 0 - Call completed without error\r
- \r
+\r
@return Status -1 - Unimplemented procedure\r
- \r
+\r
@return Status -2 - Invalid argument\r
- \r
+\r
@return Status -3 - Call completed with error.\r
- \r
+\r
@return Status -9 - Call requires PAL memory buffer.\r
- \r
+\r
**/\r
#define PAL_VP_TERMINATE 272\r
\r
+\r
+\r
+/**\r
+\r
+ PAL Procedure - PAL_ROUTE_CONFIG.\r
+\r
+ Set allowable requested Route configuration bits in all\r
+ Ports[11:0] specified in the port_map.\r
+\r
+\r
+ @param Index Index of PAL_ROUTE_CONFIG within the list of PAL\r
+ procedures.\r
+\r
+ @param route_cfg_ctl 32-bit vector of routing configuration control bits\r
+\r
+ @param write_map bits[11:0] map to desired Ports[11:0] to be modified.\r
+\r
+ @param buffer_addr Addr of CSR read buffer64(12)\r
+\r
+ @return Status 0 - Call completed without error\r
+\r
+ @return Status -4 - Invalid CSR data write bit requested\r
+\r
+ @return Status -5 - Invalid CSR map requested\r
+\r
+ @return Status -6 - Invalid CSR buffer address\r
+\r
+**/\r
+#define PAL_ROUTE_CONFIG 0x0301\r
+\r
/**\r
Makes a PAL procedure call.\r
\r
This function is only available on IPF.\r
\r
@param Index - The PAL procedure Index number.\r
- @param Arg2 - The 2nd parameter for PAL procedure calls.\r
+ @param Arg2 - The 2nd parameter for PAL procedure calls.\r
@param Arg3 - The 3rd parameter for PAL procedure calls.\r
@param Arg4 - The 4th parameter for PAL procedure calls.\r
\r
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