UefiCpuPkg/AcpiCpuData: Update RegisterTableEntry type

Current RegisterTableEntry filed in CPU_REGISTER_TABLE is one pointer to
CPU_REGISTER_TABLE_ENTRY. If CPU register table wants to be passed from 32bit
PEI to x64 DXE/SMM, x64 DXE/SMM cannot get the correct RegisterTableEntry.

This update is to update RegisterTableEntry type to EFI_PHYSICAL_ADDRESS and
make RegisterTableEntry is fixed length.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
index 3489b9549ce0a3a5c9139c2ef7032b68df4fca1b..07c7102fe0caaab859b568a7aa4a90c4d0d0cec5 100644 (file)
--- a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
+++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
@@ -9,7 +9,7 @@ number of CPUs reported by the MP Services Protocol, so this module does not
 support hot plug CPUs.  This module can be copied into a CPU specific package\r
 and customized if these additional features are required.\r
 \r
-Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>\r
 Copyright (c) 2015, Red Hat, Inc.\r
 \r
 This program and the accompanying materials\r
@@ -246,12 +246,12 @@ CpuS3DataInitialize (
     RegisterTable[Index].InitialApicId      = (UINT32)ProcessorInfoBuffer.ProcessorId;\r
     RegisterTable[Index].TableLength        = 0;\r
     RegisterTable[Index].AllocatedSize      = 0;\r
-    RegisterTable[Index].RegisterTableEntry = NULL;\r
+    RegisterTable[Index].RegisterTableEntry = 0;\r
 \r
     RegisterTable[NumberOfCpus + Index].InitialApicId      = (UINT32)ProcessorInfoBuffer.ProcessorId;\r
     RegisterTable[NumberOfCpus + Index].TableLength        = 0;\r
     RegisterTable[NumberOfCpus + Index].AllocatedSize      = 0;\r
-    RegisterTable[NumberOfCpus + Index].RegisterTableEntry = NULL;\r
+    RegisterTable[NumberOfCpus + Index].RegisterTableEntry = 0;\r
   }\r
   AcpiCpuData->RegisterTable           = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTable;\r
   AcpiCpuData->PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)(RegisterTable + NumberOfCpus);\r

diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuData.h
index 12e9692c5cf80b5294ef14c61c43a1788b9e844a..130eb908953da05a5285cc5f8a958b1c354fb04a 100644 (file)
--- a/UefiCpuPkg/Include/AcpiCpuData.h
+++ b/UefiCpuPkg/Include/AcpiCpuData.h
@@ -1,7 +1,7 @@
 /** @file\r
 Definitions for CPU S3 data.\r
 \r
-Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -55,10 +55,10 @@ typedef struct {
   //\r
   UINT32                    InitialApicId;\r
   //\r
-  // Buffer of CPU_REGISTER_TABLE_ENTRY structures.  This buffer must be\r
+  // Physical address of CPU_REGISTER_TABLE_ENTRY structures.  This buffer must be\r
   // allocated below 4GB from memory of type EfiACPIMemoryNVS.\r
   //\r
-  CPU_REGISTER_TABLE_ENTRY  *RegisterTableEntry;\r
+  EFI_PHYSICAL_ADDRESS      RegisterTableEntry;\r
 } CPU_REGISTER_TABLE;\r
 \r
 //\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 532b7c44bd17a5b0213f68f90eeec11496521e5a..12efc1f90eee61b65a4f5e00439d95ccd77d0580 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -1,7 +1,7 @@
 /** @file\r
 Code for Processor S3 restoration\r
 \r
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -826,13 +826,12 @@ CopyRegisterTable (
 \r
   CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));\r
   for (Index = 0; Index < NumberOfCpus; Index++) {\r
-    DestinationRegisterTableList[Index].RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);\r
-    ASSERT (DestinationRegisterTableList[Index].RegisterTableEntry != NULL);\r
-    CopyMem (DestinationRegisterTableList[Index].RegisterTableEntry, SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);\r
+    RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);\r
+    ASSERT (RegisterTableEntry != NULL);\r
+    CopyMem (RegisterTableEntry, (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);\r
     //\r
     // Go though all MSRs in register table to initialize MSR spin lock\r
     //\r
-    RegisterTableEntry = DestinationRegisterTableList[Index].RegisterTableEntry;\r
     for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {\r
       if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {\r
         //\r
@@ -841,6 +840,7 @@ CopyRegisterTable (
         InitMsrSpinLockByIndex (RegisterTableEntry->Index);\r
       }\r
     }\r
+    DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;\r
   }\r
 }\r
 \r