--- /dev/null
+#\r
+# Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+\r
+[Defines]\r
+ DEC_SPECIFICATION = 0x00010005\r
+ PACKAGE_NAME = ArmJunoPkg\r
+ PACKAGE_GUID = a1147a20-3144-4f8d-8295-b48311c8e4a4\r
+ PACKAGE_VERSION = 0.1\r
+\r
+################################################################################\r
+#\r
+# Include Section - list of Include Paths that are provided by this package.\r
+# Comments are used for Keywords and Module Types.\r
+#\r
+# Supported Module Types:\r
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
+#\r
+################################################################################\r
+[Includes.common]\r
+ Include # Root include for the package\r
+\r
+[Guids.common]\r
+ gArmJunoTokenSpaceGuid = { 0xa1147a20, 0x3144, 0x4f8d, { 0x82, 0x95, 0xb4, 0x83, 0x11, 0xc8, 0xe4, 0xa4 } }\r
+\r
+[PcdsFixedAtBuild.common]\r
+ gArmJunoTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT32|0x00000001\r
+ gArmJunoTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT32|0x00000002\r
+ gArmJunoTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000003\r
+\r
+ gArmJunoTokenSpaceGuid.PcdSynopsysUsbOhciBaseAddress|0x7FFB0000|UINT32|0x00000004\r
+ gArmJunoTokenSpaceGuid.PcdSynopsysUsbEhciBaseAddress|0x7FFC0000|UINT32|0x00000005\r
--- /dev/null
+#\r
+# Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ PLATFORM_NAME = ArmJuno\r
+ PLATFORM_GUID = ca0722fd-7d3d-45ea-948c-d62b2199807d\r
+ PLATFORM_VERSION = 0.1\r
+ DSC_SPECIFICATION = 0x00010005\r
+ OUTPUT_DIRECTORY = Build/ArmJuno\r
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM\r
+ BUILD_TARGETS = DEBUG|RELEASE\r
+ SKUID_IDENTIFIER = DEFAULT\r
+ FLASH_DEFINITION = ArmPlatformPkg/ArmJunoPkg/ArmJuno.fdf\r
+\r
+# On RTSM, most peripherals are VExpress Motherboard peripherals\r
+!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc\r
+\r
+[LibraryClasses.common]\r
+ ArmPlatformLib|ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf\r
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
+\r
+ ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf\r
+ NorFlashPlatformLib|ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/NorFlashJunoLib.inf\r
+ EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf\r
+\r
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf\r
+\r
+ # USB Requirements\r
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf\r
+\r
+[LibraryClasses.ARM]\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
+\r
+[LibraryClasses.AARCH64]\r
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf\r
+\r
+[LibraryClasses.common.SEC]\r
+ PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf\r
+ ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf\r
+ LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
+ MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf\r
+ HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf\r
+ PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf\r
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf\r
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf\r
+ MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf\r
+\r
+[BuildOptions]\r
+ GCC:*_*_*_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmJunoPkg/Include\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+\r
+[PcdsFeatureFlag.common]\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE\r
+\r
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.\r
+ # It could be set FALSE to save size.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE\r
+\r
+[PcdsFixedAtBuild.common]\r
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Juno"\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmJuno"\r
+\r
+ #\r
+ # NV Storage PCDs. Use base of 0x08000000 for NOR0\r
+ #\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0BFC0000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0BFD0000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0BFE0000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000\r
+\r
+ # System Memory (2GB - 16MB of Trusted DRAM at the top of the 32bit address space)\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000\r
+\r
+ # Juno Dual-Cluster profile\r
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|6\r
+ gArmPlatformTokenSpaceGuid.PcdClusterCount|2\r
+\r
+ gArmTokenSpaceGuid.PcdVFPEnabled|1\r
+\r
+ #\r
+ # ARM PrimeCell\r
+ #\r
+\r
+ ## PL011 - Serial Terminal\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x7FF80000\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200\r
+ gArmPlatformTokenSpaceGuid.PL011UartInteger|4\r
+ gArmPlatformTokenSpaceGuid.PL011UartFractional|0\r
+\r
+ ## PL031 RealTimeClock\r
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000\r
+\r
+ # LAN9118 Ethernet Driver\r
+ gEmbeddedTokenSpaceGuid.PcdLan9118DxeBaseAddress|0x18000000\r
+ gEmbeddedTokenSpaceGuid.PcdLan9118DefaultMacAddress|0x1215161822242628\r
+\r
+ #\r
+ # ARM General Interrupt Controller\r
+ #\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C010000\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C02F000\r
+\r
+ # List of Device Paths that support BootMonFs\r
+ gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)"\r
+\r
+ #\r
+ # ARM OS Loader\r
+ #\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from NOR Flash"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/Image"\r
+ gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/juno.dtb"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,115200 earlyprintk=pl011,0x7ff80000 root=/dev/sda1 rootwait verbose debug"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2\r
+\r
+ # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"\r
+\r
+ #\r
+ # ARM Architectural Timer Frequency\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000\r
+ gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000\r
+\r
+[PcdsPatchableInModule]\r
+ # Console Resolution (Full HD)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1920\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|1080\r
+\r
+\r
+################################################################################\r
+#\r
+# Components Section - list of all EDK II Modules needed by this Platform\r
+#\r
+################################################################################\r
+[Components.common]\r
+ #\r
+ # PEI Phase modules\r
+ #\r
+ ArmPlatformPkg/PrePi/PeiMPCore.inf {\r
+ <LibraryClasses>\r
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf\r
+ }\r
+\r
+ #\r
+ # DXE\r
+ #\r
+ MdeModulePkg/Core/Dxe/DxeMain.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf\r
+ }\r
+\r
+ #\r
+ # Architectural Protocols\r
+ #\r
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+\r
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ EmbeddedPkg/SerialDxe/SerialDxe.inf\r
+\r
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
+\r
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+\r
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
+ ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
+ ArmPlatformPkg/ArmJunoPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf\r
+\r
+ #\r
+ # Semi-hosting filesystem\r
+ #\r
+ ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
+\r
+ #\r
+ # FAT filesystem + GPT/MBR partitioning\r
+ #\r
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+ # Networking stack\r
+ EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf\r
+\r
+ #\r
+ # Usb Support\r
+ #\r
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf\r
+ MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf\r
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf\r
+\r
+ #\r
+ # Juno platform driver\r
+ #\r
+ ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf\r
+\r
+ #\r
+ # Bds\r
+ #\r
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ ArmPlatformPkg/Bds/Bds.inf\r
+\r
--- /dev/null
+#\r
+# Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+\r
+################################################################################\r
+#\r
+# FD Section\r
+# The [FD] Section is made up of the definition statements and a\r
+# description of what goes into the Flash Device Image. Each FD section\r
+# defines one flash "device" image. A flash device image may be one of\r
+# the following: Removable media bootable image (like a boot floppy\r
+# image,) an Option ROM image (that would be "flashed" into an add-in\r
+# card,) a System "Flash" image (that would be burned into a system's\r
+# flash) or an Update ("Capsule") image that will be used to update and\r
+# existing system flash.\r
+#\r
+################################################################################\r
+\r
+[FD.BL33_AP_UEFI]\r
+BaseAddress = 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.\r
+Size = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device\r
+ErasePolarity = 1\r
+\r
+# This one is tricky, it must be: BlockSize * NumBlocks = Size\r
+BlockSize = 0x00001000\r
+NumBlocks = 0xF0\r
+\r
+################################################################################\r
+#\r
+# Following are lists of FD Region layout which correspond to the locations of different\r
+# images within the flash device.\r
+#\r
+# Regions must be defined in ascending order and may not overlap.\r
+#\r
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
+# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
+# "0x" characters. Like:\r
+# Offset|Size\r
+# PcdOffsetCName|PcdSizeCName\r
+# RegionType <FV, DATA, or FILE>\r
+#\r
+################################################################################\r
+\r
+0x00000000|0x000F0000\r
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize\r
+FV = FVMAIN_COMPACT\r
+\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+\r
+[FV.FvMain]\r
+BlockSize = 0x40\r
+NumBlocks = 0 # This FV gets compressed so make it just big enough\r
+FvAlignment = 8 # FV alignment and FV attributes setting.\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
+\r
+ #\r
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)\r
+ #\r
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+\r
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
+\r
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+\r
+ #\r
+ # Multiple Console IO support\r
+ #\r
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
+\r
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
+ INF ArmPlatformPkg/ArmJunoPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf\r
+\r
+ # NOR Flash driver\r
+ INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
+\r
+ # Versatile Express FileSystem\r
+ INF ArmPlatformPkg/FileSystem/BootMonFs/BootMonFs.inf\r
+\r
+ #\r
+ # FAT filesystem + GPT/MBR partitioning\r
+ #\r
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ INF FatBinPkg/EnhancedFatDxe/Fat.inf\r
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+ #\r
+ # Usb Support\r
+ #\r
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf\r
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf\r
+ INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf\r
+\r
+ #\r
+ # Networking stack\r
+ #\r
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf\r
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf\r
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf\r
+ INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf\r
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf\r
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf\r
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf\r
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf\r
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf\r
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf\r
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf\r
+ INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf\r
+ INF EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf\r
+\r
+ #\r
+ # UEFI applications\r
+ #\r
+ INF ShellBinPkg/UefiShell/UefiShell.inf\r
+\r
+ #\r
+ # Juno platform driver\r
+ #\r
+ INF ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf\r
+\r
+ #\r
+ # Bds\r
+ #\r
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ INF ArmPlatformPkg/Bds/Bds.inf\r
+\r
+[FV.FVMAIN_COMPACT]\r
+FvAlignment = 8\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+ INF ArmPlatformPkg/PrePi/PeiMPCore.inf\r
+\r
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
+ SECTION FV_IMAGE = FVMAIN\r
+ }\r
+ }\r
+\r
+\r
+################################################################################\r
+#\r
+# Rules are use with the [FV] section's module INF type to define\r
+# how an FFS file is created for a given INF file. The following Rule are the default\r
+# rules for the different module type. User can add the customized rules to define the\r
+# content of the FFS file.\r
+#\r
+################################################################################\r
+\r
+\r
+############################################################################\r
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #\r
+############################################################################\r
+#\r
+#[Rule.Common.DXE_DRIVER]\r
+# FILE DRIVER = $(NAMED_GUID) {\r
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+# COMPRESS PI_STD {\r
+# GUIDED {\r
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+# UI STRING="$(MODULE_NAME)" Optional\r
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+# }\r
+# }\r
+# }\r
+#\r
+############################################################################\r
+\r
+#\r
+# These SEC rules are used for ArmPlatformPkg/PrePi module.\r
+# ArmPlatformPkg/PrePi is declared as a SEC module to make GenFv patch the\r
+# UEFI Firmware to jump to ArmPlatformPkg/PrePi entrypoint\r
+#\r
+[Rule.ARM.SEC]\r
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
+ TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ }\r
+\r
+[Rule.AARCH64.SEC]\r
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
+ TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ }\r
+\r
+# A shim specific rule is required to ensure the alignment is 4K.\r
+# Otherwise BaseTools pick up the AArch32 alignment (ie: 32)\r
+[Rule.ARM.SEC.SHIM]\r
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
+ TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ }\r
+\r
+[Rule.Common.PEI_CORE]\r
+ FILE PEI_CORE = $(NAMED_GUID) {\r
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING ="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.PEIM]\r
+ FILE PEIM = $(NAMED_GUID) {\r
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.PEIM.TIANOCOMPRESSED]\r
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {\r
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+ }\r
+\r
+[Rule.Common.DXE_CORE]\r
+ FILE DXE_CORE = $(NAMED_GUID) {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.DXE_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.DXE_RUNTIME_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ UI STRING ="$(MODULE_NAME)" Optional\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER.BINARY]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION.BINARY]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include "ArmJunoDxeInternal.h"\r
+#include <Library/ArmShellCmdLib.h>\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+ArmJunoEntryPoint (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS HypBase;\r
+\r
+ Status = PciEmulationEntryPoint ();\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // If a hypervisor has been declared then we need to make sure its region is protected at runtime\r
+ //\r
+ // Note: This code is only a workaround for our dummy hypervisor (ArmPkg/Extra/AArch64ToAArch32Shim/)\r
+ // that does not set up (yet) the stage 2 translation table to hide its own memory to EL1.\r
+ //\r
+ if (FixedPcdGet32 (PcdHypFvSize) != 0) {\r
+ // Ensure the hypervisor region is strictly contained into a EFI_PAGE_SIZE-aligned region.\r
+ // The memory must be a multiple of EFI_PAGE_SIZE to ensure we do not reserve more memory than the hypervisor itself.\r
+ // A UEFI Runtime region size granularity cannot be smaller than EFI_PAGE_SIZE. If the hypervisor size is not rounded\r
+ // to this size then there is a risk some non-runtime memory could be visible to the OS view.\r
+ if (((FixedPcdGet32 (PcdHypFvSize) & EFI_PAGE_MASK) == 0) && ((FixedPcdGet32 (PcdHypFvBaseAddress) & EFI_PAGE_MASK) == 0)) {\r
+ // The memory needs to be declared because the DXE core marked it as reserved and removed it from the memory space\r
+ // as it contains the Firmware.\r
+ Status = gDS->AddMemorySpace (\r
+ EfiGcdMemoryTypeSystemMemory,\r
+ FixedPcdGet32 (PcdHypFvBaseAddress), FixedPcdGet32 (PcdHypFvSize),\r
+ EFI_MEMORY_WB | EFI_MEMORY_RUNTIME\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ // We allocate the memory to ensure it is marked as runtime memory\r
+ HypBase = FixedPcdGet32 (PcdHypFvBaseAddress);\r
+ Status = gBS->AllocatePages (AllocateAddress, EfiRuntimeServicesCode,\r
+ EFI_SIZE_TO_PAGES (FixedPcdGet32 (PcdHypFvSize)), &HypBase);\r
+ }\r
+ } else {\r
+ // The hypervisor must be contained into a EFI_PAGE_SIZE-aligned region and its size must also be aligned\r
+ // on a EFI_PAGE_SIZE boundary (ie: 4KB).\r
+ Status = EFI_UNSUPPORTED;\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ }\r
+\r
+ // Install dynamic Shell command to run baremetal binaries.\r
+ Status = ShellDynCmdRunAxfInstall (ImageHandle);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "ArmJunoDxe: Failed to install ShellDynCmdRunAxf\n"));\r
+ }\r
+\r
+ // Try to install the Flat Device Tree (FDT). This function actually installs the\r
+ // UEFI Driver Binding Protocol.\r
+ Status = JunoFdtInstall (ImageHandle);\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+#\r
+# Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmJunoDxe\r
+ FILE_GUID = 1484ebe8-2681-45f1-a2e5-12ecad893b62\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = ArmJunoEntryPoint\r
+\r
+[Sources.common]\r
+ ArmJunoDxe.c\r
+ InstallFdt.c\r
+ PciEmulation.c\r
+ PciRootBridgeIo.c\r
+\r
+[Packages]\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+ ArmShellCmdRunAxfLib\r
+ BaseMemoryLib\r
+ BdsLib\r
+ DebugLib\r
+ DmaLib\r
+ DxeServicesTableLib\r
+ FdtLib\r
+ IoLib\r
+ PcdLib\r
+ PrintLib\r
+ SerialPortLib\r
+ UefiBootServicesTableLib\r
+ UefiRuntimeServicesTableLib\r
+ UefiLib\r
+ UefiDriverEntryPoint\r
+\r
+[Guids]\r
+ gArmGlobalVariableGuid\r
+ gEfiEndOfDxeEventGroupGuid\r
+ gEfiFileInfoGuid\r
+ gFdtTableGuid\r
+\r
+[Protocols]\r
+ gEfiBlockIoProtocolGuid\r
+ gEfiDevicePathFromTextProtocolGuid\r
+ gEfiPciIoProtocolGuid\r
+ gEfiSimpleFileSystemProtocolGuid\r
+\r
+[FixedPcd]\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize\r
+\r
+ gArmTokenSpaceGuid.PcdHypFvBaseAddress\r
+ gArmTokenSpaceGuid.PcdHypFvSize\r
+\r
+ gArmJunoTokenSpaceGuid.PcdSynopsysUsbEhciBaseAddress\r
+ gArmJunoTokenSpaceGuid.PcdSynopsysUsbOhciBaseAddress\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdFdtDevicePath\r
+\r
+[Depex]\r
+ TRUE\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef __ARM_JUNO_DXE_INTERNAL_H__\r
+#define __ARM_JUNO_DXE_INTERNAL_H__\r
+\r
+#include <Uefi.h>\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/DxeServicesTableLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+EFI_STATUS\r
+PciEmulationEntryPoint (\r
+ VOID\r
+ );\r
+\r
+EFI_STATUS\r
+JunoFdtInstall (\r
+ IN EFI_HANDLE ImageHandle\r
+ );\r
+\r
+#endif // __ARM_JUNO_DXE_INTERNAL_H__\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include "ArmJunoDxeInternal.h"\r
+\r
+#include <Protocol/BlockIo.h>\r
+#include <Protocol/DevicePathFromText.h>\r
+#include <Protocol/DriverBinding.h>\r
+#include <Protocol/SimpleFileSystem.h>\r
+\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/BdsLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PrintLib.h>\r
+#include <Library/SerialPortLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+\r
+#include <Guid/ArmGlobalVariableHob.h>\r
+#include <Guid/EventGroup.h>\r
+#include <Guid/Fdt.h>\r
+#include <Guid/FileInfo.h>\r
+\r
+#include <libfdt.h>\r
+\r
+#define FDT_DEFAULT_FILENAME L"juno"\r
+\r
+#define IS_DEVICE_PATH_NODE(node,type,subtype) (((node)->Type == (type)) && ((node)->SubType == (subtype)))\r
+\r
+// Hardware Vendor Device Path node for the Juno NOR Flash. We use the Juno NOR Flash if the user\r
+// has not specified another filesystem location into the UEFI Variable 'Fdt'.\r
+// The Juno NOR Flash has its own filesystem format (supported by ArmPlatformPkg/FileSystem/BootMonFs).\r
+STATIC CONST struct {\r
+ VENDOR_DEVICE_PATH NorGuid;\r
+ EFI_DEVICE_PATH End;\r
+} mJunoNorFlashDevicePath = {\r
+ {\r
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0 } },\r
+ {0xE7223039, 0x5836, 0x41E1, { 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5E, 0x59} }\r
+ },\r
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } }\r
+};\r
+\r
+STATIC EFI_DEVICE_PATH* mFdtFileSystemDevicePath = NULL;\r
+STATIC CHAR16* mFdtFileName = NULL;\r
+\r
+STATIC BOOLEAN mFdtTableInstalled = FALSE;\r
+\r
+/**\r
+ See definition EFI_DRIVER_BINDING_PROTOCOL.Supported()\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+JunoFdtSupported (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
+ IN EFI_HANDLE ControllerHandle,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+\r
+ //\r
+ // Check if the Handle support the Simple File System Protocol\r
+ //\r
+ Status = gBS->OpenProtocol (\r
+ ControllerHandle,\r
+ &gEfiSimpleFileSystemProtocolGuid,\r
+ NULL,\r
+ gImageHandle,\r
+ ControllerHandle,\r
+ EFI_OPEN_PROTOCOL_TEST_PROTOCOL\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ // Check if a DevicePath is attached to the handle\r
+ Status = gBS->OpenProtocol (\r
+ ControllerHandle,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID **)&DevicePath,\r
+ gImageHandle,\r
+ ControllerHandle,\r
+ EFI_OPEN_PROTOCOL_BY_DRIVER\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ // Check if the Device Path is the one from the NOR Flash\r
+ if (CompareMem (mFdtFileSystemDevicePath, DevicePath, GetDevicePathSize (mFdtFileSystemDevicePath)) != 0) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ gBS->CloseProtocol (ControllerHandle, &gEfiDevicePathProtocolGuid, gImageHandle, ControllerHandle);\r
+ return Status;\r
+}\r
+\r
+/**\r
+ This function is used to print messages back to the user.\r
+\r
+ We use the Serial terminal for these messages as the gST->ConOut might not be initialized at this stage.\r
+\r
+ @param Message Message to display to the user\r
+**/\r
+STATIC\r
+VOID\r
+PrintMessage (\r
+ IN CHAR8* Message,\r
+ ...\r
+ )\r
+{\r
+ UINTN CharCount;\r
+ CHAR8 Buffer[100];\r
+ VA_LIST Marker;\r
+\r
+ VA_START (Marker, Message);\r
+ CharCount = AsciiVSPrint (Buffer, sizeof (Buffer), Message, Marker);\r
+ VA_END (Marker);\r
+\r
+ SerialPortWrite ((UINT8*)Buffer, CharCount);\r
+}\r
+\r
+/**\r
+ See definition EFI_DRIVER_BINDING_PROTOCOL.Start ()\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+JunoFdtStart (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
+ IN EFI_HANDLE ControllerHandle,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath OPTIONAL\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *BootMonFs;\r
+ EFI_FILE_PROTOCOL *Fs;\r
+ EFI_FILE_PROTOCOL *File;\r
+ UINTN Size;\r
+ EFI_PHYSICAL_ADDRESS FdtBlob;\r
+ EFI_FILE_INFO *FileInfo;\r
+\r
+ if (mFdtTableInstalled) {\r
+ return EFI_ALREADY_STARTED;\r
+ }\r
+\r
+ Status = gBS->OpenProtocol (\r
+ ControllerHandle,\r
+ &gEfiSimpleFileSystemProtocolGuid,\r
+ (VOID**)&BootMonFs,\r
+ gImageHandle,\r
+ ControllerHandle,\r
+ EFI_OPEN_PROTOCOL_BY_DRIVER\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ // Try to Open the volume and get root directory\r
+ Status = BootMonFs->OpenVolume (BootMonFs, &Fs);\r
+ if (EFI_ERROR (Status)) {\r
+ PrintMessage ("Warning: Fail to open file system that should contain FDT file.\n");\r
+ goto UNLOAD_PROTOCOL;\r
+ }\r
+\r
+ File = NULL;\r
+ Status = Fs->Open (Fs, &File, mFdtFileName, EFI_FILE_MODE_READ, 0);\r
+ if (EFI_ERROR (Status)) {\r
+ PrintMessage ("Warning: Fail to load FDT file '%s'.\n", mFdtFileName);\r
+ goto UNLOAD_PROTOCOL;\r
+ }\r
+\r
+ Size = 0;\r
+ File->GetInfo (File, &gEfiFileInfoGuid, &Size, NULL);\r
+ FileInfo = AllocatePool (Size);\r
+ Status = File->GetInfo (File, &gEfiFileInfoGuid, &Size, FileInfo);\r
+ if (EFI_ERROR (Status)) {\r
+ goto UNLOAD_PROTOCOL;\r
+ }\r
+\r
+ // Get the file size\r
+ Size = FileInfo->FileSize;\r
+ FreePool (FileInfo);\r
+\r
+ // The FDT blob is attached to the Configuration Table. It is better to load it as Runtime Service Data\r
+ // to prevent the kernel to overwrite its data\r
+ Status = gBS->AllocatePages (AllocateAnyPages, EfiRuntimeServicesData, EFI_SIZE_TO_PAGES (Size), &FdtBlob);\r
+ if (!EFI_ERROR (Status)) {\r
+ Status = File->Read (File, &Size, (VOID*)(UINTN)(FdtBlob));\r
+ if (EFI_ERROR (Status)) {\r
+ gBS->FreePages (FdtBlob, EFI_SIZE_TO_PAGES (Size));\r
+ } else {\r
+ // Check the FDT header is valid. We only make this check in DEBUG mode in case the FDT header change on\r
+ // production device and this ASSERT() becomes not valid.\r
+ ASSERT (fdt_check_header ((VOID*)(UINTN)(FdtBlob)) == 0);\r
+\r
+ // Ensure the Size of the Device Tree is smaller than the size of the read file\r
+ ASSERT ((UINTN)fdt_totalsize ((VOID*)(UINTN)FdtBlob) <= Size);\r
+\r
+ // Install the FDT into the Configuration Table\r
+ Status = gBS->InstallConfigurationTable (&gFdtTableGuid, (VOID*)(UINTN)(FdtBlob));\r
+ if (!EFI_ERROR (Status)) {\r
+ mFdtTableInstalled = TRUE;\r
+ }\r
+ }\r
+ }\r
+\r
+UNLOAD_PROTOCOL:\r
+ // We do not need the FileSystem protocol\r
+ gBS->CloseProtocol (\r
+ ControllerHandle,\r
+ &gEfiSimpleFileSystemProtocolGuid,\r
+ DriverBinding->ImageHandle,\r
+ ControllerHandle);\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ See definition EFI_DRIVER_BINDING_PROTOCOL.Stop()\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+JunoFdtStop (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
+ IN EFI_HANDLE ControllerHandle,\r
+ IN UINTN NumberOfChildren,\r
+ IN EFI_HANDLE *ChildHandleBuffer OPTIONAL\r
+ )\r
+{\r
+ UINTN Index;\r
+ VOID* FdtBlob;\r
+ UINTN FdtSize;\r
+\r
+ // Look for FDT Table\r
+ for (Index = 0; Index < gST->NumberOfTableEntries; Index++) {\r
+ // Check for correct GUID type\r
+ if (CompareGuid (&gFdtTableGuid, &(gST->ConfigurationTable[Index].VendorGuid))) {\r
+ FdtBlob = gST->ConfigurationTable[Index].VendorTable;\r
+ FdtSize = (UINTN)fdt_totalsize (FdtBlob);\r
+\r
+ // Uninstall the FDT Configuration Table\r
+ gBS->InstallConfigurationTable (&gFdtTableGuid, NULL);\r
+\r
+ // Free the memory\r
+ gBS->FreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)FdtBlob, EFI_SIZE_TO_PAGES (FdtSize));\r
+\r
+ return EFI_SUCCESS;\r
+ }\r
+ }\r
+\r
+ return EFI_NOT_FOUND;\r
+}\r
+\r
+//\r
+// Driver Binding Protocol for Juno FDT support\r
+//\r
+EFI_DRIVER_BINDING_PROTOCOL mJunoFdtBinding = {\r
+ JunoFdtSupported,\r
+ JunoFdtStart,\r
+ JunoFdtStop,\r
+ 0xa,\r
+ NULL,\r
+ NULL\r
+};\r
+\r
+/**\r
+ Notification function of EFI_END_OF_DXE_EVENT_GROUP_GUID event group.\r
+\r
+ This is a notification function registered on EFI_END_OF_DXE_EVENT_GROUP_GUID event group.\r
+\r
+ @param Event Event whose notification function is being invoked.\r
+ @param Context Pointer to the notification function's context.\r
+\r
+**/\r
+STATIC\r
+VOID\r
+EFIAPI\r
+OnEndOfDxe (\r
+ EFI_EVENT Event,\r
+ VOID *Context\r
+ )\r
+{\r
+ EFI_DEVICE_PATH *DevicePathNode;\r
+ EFI_HANDLE Handle;\r
+ EFI_STATUS Status;\r
+ UINTN VariableSize;\r
+ CHAR16* FdtDevicePathStr;\r
+ EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL *EfiDevicePathFromTextProtocol;\r
+\r
+ //\r
+ // Read the 'FDT' UEFI Variable to know where we should we read the blob from.\r
+ // The 'Fdt' variable contains either the full device path or only the filename of the FDT.\r
+ // If 'Fdt' only contains the filename then we assume its location is on the NOR Flash.\r
+ //\r
+ VariableSize = 0;\r
+ Status = gRT->GetVariable (L"Fdt", &gArmGlobalVariableGuid, NULL, &VariableSize, mFdtFileSystemDevicePath);\r
+ if (Status == EFI_BUFFER_TOO_SMALL) {\r
+ // Get the environment variable value\r
+ mFdtFileSystemDevicePath = AllocatePool (VariableSize);\r
+ if (mFdtFileSystemDevicePath != NULL) {\r
+ Status = gRT->GetVariable (L"Fdt", &gArmGlobalVariableGuid, NULL, &VariableSize, mFdtFileSystemDevicePath);\r
+ if (EFI_ERROR (Status)) {\r
+ FreePool (mFdtFileSystemDevicePath);\r
+ ASSERT_EFI_ERROR (Status);\r
+ return;\r
+ }\r
+ } else {\r
+ ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES);\r
+ return;\r
+ }\r
+ } else if (Status == EFI_NOT_FOUND) {\r
+ // If the 'Fdt' variable does not exist then we get the FDT location from the PCD\r
+ FdtDevicePathStr = (CHAR16*)PcdGetPtr (PcdFdtDevicePath);\r
+\r
+ Status = gBS->LocateProtocol (&gEfiDevicePathFromTextProtocolGuid, NULL, (VOID **)&EfiDevicePathFromTextProtocol);\r
+ if (EFI_ERROR (Status)) {\r
+ ASSERT_EFI_ERROR (Status);\r
+ return;\r
+ }\r
+\r
+ // Conversion of the Device Path string into EFI Device Path\r
+ mFdtFileSystemDevicePath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath (FdtDevicePathStr);\r
+ }\r
+\r
+ if (mFdtFileSystemDevicePath != NULL) {\r
+ // Look for the FDT filename that should be contained into the FilePath device path node\r
+ DevicePathNode = mFdtFileSystemDevicePath;\r
+ while (!IsDevicePathEnd (DevicePathNode)) {\r
+ if (IS_DEVICE_PATH_NODE (DevicePathNode, MEDIA_DEVICE_PATH, MEDIA_FILEPATH_DP)) {\r
+ // Extract the name from the File Path Node. The name of the Filename is the size of the\r
+ // device path node minus the size of the device path node header.\r
+ mFdtFileName = AllocateCopyPool (\r
+ DevicePathNodeLength (DevicePathNode) - sizeof(EFI_DEVICE_PATH_PROTOCOL),\r
+ ((FILEPATH_DEVICE_PATH*)DevicePathNode)->PathName);\r
+ if (mFdtFileName == NULL) {\r
+ ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES);\r
+ return;\r
+ }\r
+\r
+ // We remove the FilePath device path node from the FileSystem Device Path\r
+ // because it will never match a device path installed by the FileSystem driver\r
+ SetDevicePathEndNode (DevicePathNode);\r
+ break;\r
+ }\r
+ DevicePathNode = NextDevicePathNode (DevicePathNode);\r
+ }\r
+\r
+ // The UEFI Variable might just contain the FDT filename. In this case we assume the FileSystem is\r
+ // the NOR Flash based one (ie: BootMonFs).\r
+ // If it was only containing the FilePath device node then the previous condition should have\r
+ // replaced it by the End Device Path Node.\r
+ if (IsDevicePathEndType (mFdtFileSystemDevicePath)) {\r
+ mFdtFileSystemDevicePath = (EFI_DEVICE_PATH*)&mJunoNorFlashDevicePath;\r
+ }\r
+ } else {\r
+ // Fallback on the NOR Flash filesystem\r
+ mFdtFileSystemDevicePath = (EFI_DEVICE_PATH*)&mJunoNorFlashDevicePath;\r
+ }\r
+\r
+ // If the FDT FileName has been provided during the FileSystem identification\r
+ if (mFdtFileName == NULL) {\r
+ mFdtFileName = AllocateCopyPool (StrSize (FDT_DEFAULT_FILENAME), FDT_DEFAULT_FILENAME);\r
+ if (mFdtFileName == NULL) {\r
+ ASSERT_EFI_ERROR (Status);\r
+ return;\r
+ }\r
+ }\r
+\r
+ // Install the Binding protocol to verify when the FileSystem that contains the FDT has been installed\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &gImageHandle,\r
+ &gEfiDriverBindingProtocolGuid, &mJunoFdtBinding,\r
+ NULL\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ ASSERT_EFI_ERROR (Status);\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Force to connect the FileSystem that contains the FDT\r
+ //\r
+ BdsConnectDevicePath (mFdtFileSystemDevicePath, &Handle, NULL);\r
+}\r
+\r
+EFI_STATUS\r
+JunoFdtInstall (\r
+ IN EFI_HANDLE ImageHandle\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_EVENT EndOfDxeEvent;\r
+\r
+ // Register the event handling function to set the End Of DXE flag.\r
+ // We wait until the end of the DXE phase to load the FDT to make sure\r
+ // all the required drivers (NOR Flash, UEFI Variable, BootMonFs) are dispatched\r
+ Status = gBS->CreateEventEx (\r
+ EVT_NOTIFY_SIGNAL,\r
+ TPL_CALLBACK,\r
+ OnEndOfDxe,\r
+ NULL,\r
+ &gEfiEndOfDxeEventGroupGuid,\r
+ &EndOfDxeEvent\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+ Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "PciEmulation.h"\r
+\r
+#define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44\r
+\r
+typedef struct {\r
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;\r
+ PCI_DEVICE_PATH PciDevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r
+} EFI_PCI_IO_DEVICE_PATH;\r
+\r
+typedef struct {\r
+ UINT32 Signature;\r
+ EFI_PCI_IO_DEVICE_PATH DevicePath;\r
+ EFI_PCI_IO_PROTOCOL PciIoProtocol;\r
+ PCI_TYPE00 *ConfigSpace;\r
+ PCI_ROOT_BRIDGE RootBridge;\r
+ UINTN Segment;\r
+} EFI_PCI_IO_PRIVATE_DATA;\r
+\r
+#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', 'o')\r
+#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR (a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)\r
+\r
+EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =\r
+{\r
+ {\r
+ { ACPI_DEVICE_PATH, ACPI_DP, { sizeof (ACPI_HID_DEVICE_PATH), 0 } },\r
+ EISA_PNP_ID(0x0A03), // HID\r
+ 0 // UID\r
+ },\r
+ {\r
+ { HARDWARE_DEVICE_PATH, HW_PCI_DP, { sizeof (PCI_DEVICE_PATH), 0 } },\r
+ 0,\r
+ 0\r
+ },\r
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0} }\r
+};\r
+\r
+STATIC\r
+VOID\r
+ConfigureUSBHost (\r
+ VOID\r
+ )\r
+{\r
+}\r
+\r
+\r
+EFI_STATUS\r
+PciIoPollMem (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT8 BarIndex,\r
+ IN UINT64 Offset,\r
+ IN UINT64 Mask,\r
+ IN UINT64 Value,\r
+ IN UINT64 Delay,\r
+ OUT UINT64 *Result\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+PciIoPollIo (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT8 BarIndex,\r
+ IN UINT64 Offset,\r
+ IN UINT64 Mask,\r
+ IN UINT64 Value,\r
+ IN UINT64 Delay,\r
+ OUT UINT64 *Result\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+PciIoMemRead (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT8 BarIndex,\r
+ IN UINT64 Offset,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+ return PciRootBridgeIoMemRead (&Private->RootBridge.Io,\r
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
+ Private->ConfigSpace->Device.Bar[BarIndex] + Offset, //Fix me ConfigSpace\r
+ Count,\r
+ Buffer\r
+ );\r
+}\r
+\r
+EFI_STATUS\r
+PciIoMemWrite (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT8 BarIndex,\r
+ IN UINT64 Offset,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+ return PciRootBridgeIoMemWrite (&Private->RootBridge.Io,\r
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
+ Private->ConfigSpace->Device.Bar[BarIndex] + Offset, //Fix me ConfigSpace\r
+ Count,\r
+ Buffer\r
+ );\r
+}\r
+\r
+EFI_STATUS\r
+PciIoIoRead (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT8 BarIndex,\r
+ IN UINT64 Offset,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+PciIoIoWrite (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT8 BarIndex,\r
+ IN UINT64 Offset,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+PciIoPciRead (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT32 Offset,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);\r
+ EFI_STATUS Status;\r
+\r
+ Status = PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,\r
+ Count,\r
+ TRUE,\r
+ (PTR)(UINTN)Buffer,\r
+ TRUE,\r
+ (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset) //Fix me ConfigSpace\r
+ );\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+PciIoPciWrite (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT32 Offset,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+ return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
+ Count,\r
+ TRUE,\r
+ (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset), //Fix me ConfigSpace\r
+ TRUE,\r
+ (PTR)(UINTN)Buffer\r
+ );\r
+}\r
+\r
+EFI_STATUS\r
+PciIoCopyMem (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT8 DestBarIndex,\r
+ IN UINT64 DestOffset,\r
+ IN UINT8 SrcBarIndex,\r
+ IN UINT64 SrcOffset,\r
+ IN UINTN Count\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+PciIoMap (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r
+ IN VOID *HostAddress,\r
+ IN OUT UINTN *NumberOfBytes,\r
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
+ OUT VOID **Mapping\r
+ )\r
+{\r
+ DMA_MAP_OPERATION DmaOperation;\r
+\r
+ if (Operation == EfiPciIoOperationBusMasterRead) {\r
+ DmaOperation = MapOperationBusMasterRead;\r
+ } else if (Operation == EfiPciIoOperationBusMasterWrite) {\r
+ DmaOperation = MapOperationBusMasterWrite;\r
+ } else if (Operation == EfiPciIoOperationBusMasterCommonBuffer) {\r
+ DmaOperation = MapOperationBusMasterCommonBuffer;\r
+ } else {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);\r
+}\r
+\r
+EFI_STATUS\r
+PciIoUnmap (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN VOID *Mapping\r
+ )\r
+{\r
+ return DmaUnmap (Mapping);\r
+}\r
+\r
+EFI_STATUS\r
+PciIoAllocateBuffer (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_ALLOCATE_TYPE Type,\r
+ IN EFI_MEMORY_TYPE MemoryType,\r
+ IN UINTN Pages,\r
+ OUT VOID **HostAddress,\r
+ IN UINT64 Attributes\r
+ )\r
+{\r
+ if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {\r
+ // Check this\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ return DmaAllocateBuffer (MemoryType, Pages, HostAddress);\r
+}\r
+\r
+\r
+EFI_STATUS\r
+PciIoFreeBuffer (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN UINTN Pages,\r
+ IN VOID *HostAddress\r
+ )\r
+{\r
+ return DmaFreeBuffer (Pages, HostAddress);\r
+}\r
+\r
+\r
+EFI_STATUS\r
+PciIoFlush (\r
+ IN EFI_PCI_IO_PROTOCOL *This\r
+ )\r
+{\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+PciIoGetLocation (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ OUT UINTN *SegmentNumber,\r
+ OUT UINTN *BusNumber,\r
+ OUT UINTN *DeviceNumber,\r
+ OUT UINTN *FunctionNumber\r
+ )\r
+{\r
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+ if (SegmentNumber != NULL) {\r
+ *SegmentNumber = Private->Segment;\r
+ }\r
+\r
+ if (BusNumber != NULL) {\r
+ *BusNumber = 0xff;\r
+ }\r
+\r
+ if (DeviceNumber != NULL) {\r
+ *DeviceNumber = 0;\r
+ }\r
+\r
+ if (FunctionNumber != NULL) {\r
+ *FunctionNumber = 0;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+PciIoAttributes (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
+ IN UINT64 Attributes,\r
+ OUT UINT64 *Result OPTIONAL\r
+ )\r
+{\r
+ switch (Operation) {\r
+ case EfiPciIoAttributeOperationGet:\r
+ case EfiPciIoAttributeOperationSupported:\r
+ if (Result == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ // We are not a real PCI device so just say things we kind of do\r
+ *Result = EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER | EFI_PCI_DEVICE_ENABLE;\r
+ break;\r
+\r
+ case EfiPciIoAttributeOperationSet:\r
+ case EfiPciIoAttributeOperationEnable:\r
+ case EfiPciIoAttributeOperationDisable:\r
+ // Since we are not a real PCI device no enable/set or disable operations exist.\r
+ return EFI_SUCCESS;\r
+\r
+ default:\r
+ ASSERT (FALSE);\r
+ return EFI_INVALID_PARAMETER;\r
+ };\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+PciIoGetBarAttributes (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN UINT8 BarIndex,\r
+ OUT UINT64 *Supports, OPTIONAL\r
+ OUT VOID **Resources OPTIONAL\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+PciIoSetBarAttributes (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN UINT64 Attributes,\r
+ IN UINT8 BarIndex,\r
+ IN OUT UINT64 *Offset,\r
+ IN OUT UINT64 *Length\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_PCI_IO_PROTOCOL PciIoTemplate =\r
+{\r
+ PciIoPollMem,\r
+ PciIoPollIo,\r
+ { PciIoMemRead, PciIoMemWrite },\r
+ { PciIoIoRead, PciIoIoWrite },\r
+ { PciIoPciRead, PciIoPciWrite },\r
+ PciIoCopyMem,\r
+ PciIoMap,\r
+ PciIoUnmap,\r
+ PciIoAllocateBuffer,\r
+ PciIoFreeBuffer,\r
+ PciIoFlush,\r
+ PciIoGetLocation,\r
+ PciIoAttributes,\r
+ PciIoGetBarAttributes,\r
+ PciIoSetBarAttributes,\r
+ 0,\r
+ 0\r
+};\r
+\r
+EFI_STATUS\r
+PciInstallDevice (\r
+ IN UINTN DeviceId,\r
+ IN PHYSICAL_ADDRESS MemoryStart,\r
+ IN UINT64 MemorySize,\r
+ IN UINTN ClassCode1,\r
+ IN UINTN ClassCode2,\r
+ IN UINTN ClassCode3\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE Handle;\r
+ EFI_PCI_IO_PRIVATE_DATA *Private;\r
+\r
+ // Configure USB host\r
+ ConfigureUSBHost ();\r
+\r
+ // Create a private structure\r
+ Private = AllocatePool (sizeof (EFI_PCI_IO_PRIVATE_DATA));\r
+ if (Private == NULL) {\r
+ Status = EFI_OUT_OF_RESOURCES;\r
+ return Status;\r
+ }\r
+\r
+ Private->Signature = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; // Fill in signature\r
+ Private->RootBridge.Signature = PCI_ROOT_BRIDGE_SIGNATURE; // Fake Root Bridge structure needs a signature too\r
+ Private->RootBridge.MemoryStart = MemoryStart; // Get the USB capability register base\r
+ Private->Segment = 0; // Default to segment zero\r
+\r
+ // Calculate the total size of the USB controller (OHCI + EHCI).\r
+ Private->RootBridge.MemorySize = MemorySize; //CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1));\r
+\r
+ // Create fake PCI config space: OHCI + EHCI\r
+ Private->ConfigSpace = AllocateZeroPool (sizeof (PCI_TYPE00));\r
+ if (Private->ConfigSpace == NULL) {\r
+ Status = EFI_OUT_OF_RESOURCES;\r
+ FreePool (Private);\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Configure PCI config space: OHCI + EHCI\r
+ //\r
+ Private->ConfigSpace->Hdr.VendorId = 0x3530; //TODO: Define one\r
+ Private->ConfigSpace->Hdr.DeviceId = 0x3530; //TODO: Define one\r
+ Private->ConfigSpace->Hdr.ClassCode[0] = ClassCode1;\r
+ Private->ConfigSpace->Hdr.ClassCode[1] = ClassCode2;\r
+ Private->ConfigSpace->Hdr.ClassCode[2] = ClassCode3;\r
+ Private->ConfigSpace->Device.Bar[0] = MemoryStart;\r
+\r
+ Handle = NULL;\r
+\r
+ // Unique device path.\r
+ CopyMem (&Private->DevicePath, &PciIoDevicePathTemplate, sizeof (PciIoDevicePathTemplate));\r
+ Private->DevicePath.AcpiDevicePath.UID = 0;\r
+ Private->DevicePath.PciDevicePath.Device = DeviceId;\r
+\r
+ // Copy protocol structure\r
+ CopyMem (&Private->PciIoProtocol, &PciIoTemplate, sizeof (PciIoTemplate));\r
+\r
+ Status = gBS->InstallMultipleProtocolInterfaces (&Handle,\r
+ &gEfiPciIoProtocolGuid, &Private->PciIoProtocol,\r
+ &gEfiDevicePathProtocolGuid, &Private->DevicePath,\r
+ NULL);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces () failed.\n"));\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+PciEmulationEntryPoint (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Status = PciInstallDevice (0, FixedPcdGet32 (PcdSynopsysUsbOhciBaseAddress), SIZE_64KB, PCI_IF_OHCI, PCI_CLASS_SERIAL_USB, PCI_CLASS_SERIAL);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "PciEmulation: failed to install OHCI device.\n"));\r
+ }\r
+\r
+ Status = PciInstallDevice (1, FixedPcdGet32 (PcdSynopsysUsbEhciBaseAddress), SIZE_64KB, PCI_IF_EHCI, PCI_CLASS_SERIAL_USB, PCI_CLASS_SERIAL);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "PciEmulation: failed to install EHCI device.\n"));\r
+ }\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+ Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _PCI_ROOT_BRIDGE_H_\r
+#define _PCI_ROOT_BRIDGE_H_\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DxeServicesTableLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/DmaLib.h>\r
+\r
+#include <Protocol/EmbeddedExternalDevice.h>\r
+#include <Protocol/DevicePath.h>\r
+#include <Protocol/PciIo.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+#include <Protocol/PciHostBridgeResourceAllocation.h>\r
+\r
+#include <IndustryStandard/Pci23.h>\r
+\r
+#include "ArmJunoDxeInternal.h"\r
+\r
+#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r
+#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r
+#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL\r
+\r
+\r
+typedef struct {\r
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;\r
+\r
+\r
+#define ACPI_CONFIG_IO 0\r
+#define ACPI_CONFIG_MMIO 1\r
+#define ACPI_CONFIG_BUS 2\r
+\r
+typedef struct {\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Desc[3];\r
+ EFI_ACPI_END_TAG_DESCRIPTOR EndDesc;\r
+} ACPI_CONFIG_INFO;\r
+\r
+\r
+#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('P', 'c', 'i', 'F')\r
+\r
+typedef struct {\r
+ UINT32 Signature;\r
+ EFI_HANDLE Handle;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;\r
+ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath;\r
+\r
+ UINT8 StartBus;\r
+ UINT8 EndBus;\r
+ UINT16 Type;\r
+ UINT32 MemoryStart;\r
+ UINT32 MemorySize;\r
+ UINTN IoOffset;\r
+ UINT32 IoStart;\r
+ UINT32 IoSize;\r
+ UINT64 PciAttributes;\r
+\r
+ ACPI_CONFIG_INFO *Config;\r
+\r
+} PCI_ROOT_BRIDGE;\r
+\r
+\r
+#define INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE, Io, PCI_ROOT_BRIDGE_SIGNATURE)\r
+\r
+\r
+typedef union {\r
+ UINT8 volatile *Buffer;\r
+ UINT8 volatile *Ui8;\r
+ UINT16 volatile *Ui16;\r
+ UINT32 volatile *Ui32;\r
+ UINT64 volatile *Ui64;\r
+ UINTN volatile Ui;\r
+} PTR;\r
+\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoPollMem (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINT64 Mask,\r
+ IN UINT64 Value,\r
+ IN UINT64 Delay,\r
+ OUT UINT64 *Result\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoPollIo (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINT64 Mask,\r
+ IN UINT64 Value,\r
+ IN UINT64 Delay,\r
+ OUT UINT64 *Result\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoMemRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoMemWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoIoRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 UserAddress,\r
+ IN UINTN Count,\r
+ IN OUT VOID *UserBuffer\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoIoWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 UserAddress,\r
+ IN UINTN Count,\r
+ IN OUT VOID *UserBuffer\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoCopyMem (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 DestAddress,\r
+ IN UINT64 SrcAddress,\r
+ IN UINTN Count\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoPciRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoPciWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoMap (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r
+ IN VOID *HostAddress,\r
+ IN OUT UINTN *NumberOfBytes,\r
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
+ OUT VOID **Mapping\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoUnmap (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN VOID *Mapping\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoAllocateBuffer (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_ALLOCATE_TYPE Type,\r
+ IN EFI_MEMORY_TYPE MemoryType,\r
+ IN UINTN Pages,\r
+ OUT VOID **HostAddress,\r
+ IN UINT64 Attributes\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoFreeBuffer (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN UINTN Pages,\r
+ OUT VOID *HostAddress\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoFlush (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoGetAttributes (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ OUT UINT64 *Supported,\r
+ OUT UINT64 *Attributes\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoSetAttributes (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN UINT64 Attributes,\r
+ IN OUT UINT64 *ResourceBase,\r
+ IN OUT UINT64 *ResourceLength\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoConfiguration (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ OUT VOID **Resources\r
+ );\r
+\r
+//\r
+// Private Function Prototypes\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoMemRW (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINTN Count,\r
+ IN BOOLEAN InStrideFlag,\r
+ IN PTR In,\r
+ IN BOOLEAN OutStrideFlag,\r
+ OUT PTR Out\r
+ );\r
+\r
+BOOLEAN\r
+PciIoMemAddressValid (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN UINT64 Address\r
+ );\r
+\r
+EFI_STATUS\r
+EmulatePciIoForEhci (\r
+ INTN MvPciIfMaxIf\r
+ );\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "PciEmulation.h"\r
+\r
+BOOLEAN\r
+PciRootBridgeMemAddressValid (\r
+ IN PCI_ROOT_BRIDGE *Private,\r
+ IN UINT64 Address\r
+ )\r
+{\r
+ if ((Address >= Private->MemoryStart) && (Address < (Private->MemoryStart + Private->MemorySize))) {\r
+ return TRUE;\r
+ }\r
+\r
+ return FALSE;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+PciRootBridgeIoMemRW (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINTN Count,\r
+ IN BOOLEAN InStrideFlag,\r
+ IN PTR In,\r
+ IN BOOLEAN OutStrideFlag,\r
+ OUT PTR Out\r
+ )\r
+{\r
+ UINTN Stride;\r
+ UINTN InStride;\r
+ UINTN OutStride;\r
+\r
+ Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ Stride = (UINTN)1 << Width;\r
+ InStride = InStrideFlag ? Stride : 0;\r
+ OutStride = OutStrideFlag ? Stride : 0;\r
+\r
+ //\r
+ // Loop for each iteration and move the data\r
+ //\r
+ switch (Width) {\r
+ case EfiPciWidthUint8:\r
+ for (;Count > 0; Count--, In.Buffer += InStride, Out.Buffer += OutStride) {\r
+ *In.Ui8 = *Out.Ui8;\r
+ }\r
+ break;\r
+ case EfiPciWidthUint16:\r
+ for (;Count > 0; Count--, In.Buffer += InStride, Out.Buffer += OutStride) {\r
+ *In.Ui16 = *Out.Ui16;\r
+ }\r
+ break;\r
+ case EfiPciWidthUint32:\r
+ for (;Count > 0; Count--, In.Buffer += InStride, Out.Buffer += OutStride) {\r
+ *In.Ui32 = *Out.Ui32;\r
+ }\r
+ break;\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+PciRootBridgeIoPciRW (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN BOOLEAN Write,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 UserAddress,\r
+ IN UINTN Count,\r
+ IN OUT VOID *UserBuffer\r
+ )\r
+{\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
+\r
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param Width Signifies the width of the memory operations.\r
+ @param Address The base address of the memory operations.\r
+ @param Count The number of memory operations to perform.\r
+ @param Buffer For read operations, the destination buffer to store the results. For write\r
+ operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoMemRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ PCI_ROOT_BRIDGE *Private;\r
+ UINTN AlignMask;\r
+ PTR In;\r
+ PTR Out;\r
+\r
+ if ( Buffer == NULL ) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
+\r
+ if (!PciRootBridgeMemAddressValid (Private, Address)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ AlignMask = (1 << (Width & 0x03)) - 1;\r
+ if (Address & AlignMask) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ In.Buffer = Buffer;\r
+ Out.Buffer = (VOID *)(UINTN) Address;\r
+\r
+ switch (Width) {\r
+ case EfiPciWidthUint8:\r
+ case EfiPciWidthUint16:\r
+ case EfiPciWidthUint32:\r
+ case EfiPciWidthUint64:\r
+ return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);\r
+\r
+ case EfiPciWidthFifoUint8:\r
+ case EfiPciWidthFifoUint16:\r
+ case EfiPciWidthFifoUint32:\r
+ case EfiPciWidthFifoUint64:\r
+ return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);\r
+\r
+ case EfiPciWidthFillUint8:\r
+ case EfiPciWidthFillUint16:\r
+ case EfiPciWidthFillUint32:\r
+ case EfiPciWidthFillUint64:\r
+ return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return EFI_INVALID_PARAMETER;\r
+}\r
+\r
+/**\r
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
+\r
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param Width Signifies the width of the memory operations.\r
+ @param Address The base address of the memory operations.\r
+ @param Count The number of memory operations to perform.\r
+ @param Buffer For read operations, the destination buffer to store the results. For write\r
+ operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoMemWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ PCI_ROOT_BRIDGE *Private;\r
+ UINTN AlignMask;\r
+ PTR In;\r
+ PTR Out;\r
+\r
+ if ( Buffer == NULL ) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
+\r
+ if (!PciRootBridgeMemAddressValid (Private, Address)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ AlignMask = (1 << (Width & 0x03)) - 1;\r
+ if (Address & AlignMask) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ In.Buffer = (VOID *)(UINTN) Address;\r
+ Out.Buffer = Buffer;\r
+\r
+ switch (Width) {\r
+ case EfiPciWidthUint8:\r
+ case EfiPciWidthUint16:\r
+ case EfiPciWidthUint32:\r
+ case EfiPciWidthUint64:\r
+ return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);\r
+\r
+ case EfiPciWidthFifoUint8:\r
+ case EfiPciWidthFifoUint16:\r
+ case EfiPciWidthFifoUint32:\r
+ case EfiPciWidthFifoUint64:\r
+ return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);\r
+\r
+ case EfiPciWidthFillUint8:\r
+ case EfiPciWidthFillUint16:\r
+ case EfiPciWidthFillUint32:\r
+ case EfiPciWidthFillUint64:\r
+ return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return EFI_INVALID_PARAMETER;\r
+}\r
+\r
+/**\r
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
+\r
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param Width Signifies the width of the memory operations.\r
+ @param Address The base address of the memory operations.\r
+ @param Count The number of memory operations to perform.\r
+ @param Buffer For read operations, the destination buffer to store the results. For write\r
+ operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoPciRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ if (Buffer == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return PciRootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);\r
+}\r
+\r
+/**\r
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
+\r
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param Width Signifies the width of the memory operations.\r
+ @param Address The base address of the memory operations.\r
+ @param Count The number of memory operations to perform.\r
+ @param Buffer For read operations, the destination buffer to store the results. For write\r
+ operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciRootBridgeIoPciWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ if (Buffer == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return PciRootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);\r
+}\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD\r
+* License which accompanies this distribution. The full text of the license\r
+* may be found at http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/ArmGenericTimerCounterLib.h>\r
+\r
+#include <Protocol/WatchdogTimer.h>\r
+#include <Protocol/HardwareInterrupt.h>\r
+\r
+#include <Drivers/GenericWatchdog.h>\r
+\r
+// The number of 100ns periods (the unit of time passed to these functions)\r
+// in a second\r
+#define TIME_UNITS_PER_SECOND 10000000\r
+\r
+// Tick frequency of the generic timer that is the basis of the generic watchdog\r
+UINTN mTimerFrequencyHz = 0;\r
+\r
+// In cases where the compare register was set manually, information about\r
+// how long the watchdog was asked to wait cannot be retrieved from hardware.\r
+// It is therefore stored here. 0 means the timer is not running.\r
+UINT64 mNumTimerTicks = 0;\r
+\r
+EFI_HARDWARE_INTERRUPT_PROTOCOL *mInterruptProtocol;\r
+\r
+EFI_STATUS\r
+WatchdogWriteOffsetRegister (\r
+ UINT32 Value\r
+ )\r
+{\r
+ return MmioWrite32 (GENERIC_WDOG_OFFSET_REG, Value);\r
+}\r
+\r
+EFI_STATUS\r
+WatchdogWriteCompareRegister (\r
+ UINT64 Value\r
+ )\r
+{\r
+ return MmioWrite64 (GENERIC_WDOG_COMPARE_VALUE_REG, Value);\r
+}\r
+\r
+EFI_STATUS\r
+WatchdogEnable (\r
+ VOID\r
+ )\r
+{\r
+ return MmioWrite32 (GENERIC_WDOG_CONTROL_STATUS_REG, GENERIC_WDOG_ENABLED);\r
+}\r
+\r
+EFI_STATUS\r
+WatchdogDisable (\r
+ VOID\r
+ )\r
+{\r
+ return MmioWrite32 (GENERIC_WDOG_CONTROL_STATUS_REG, GENERIC_WDOG_DISABLED);\r
+}\r
+\r
+/**\r
+ On exiting boot services we must make sure the Watchdog Timer\r
+ is stopped.\r
+**/\r
+VOID\r
+EFIAPI\r
+WatchdogExitBootServicesEvent (\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
+ )\r
+{\r
+ WatchdogDisable ();\r
+ mNumTimerTicks = 0;\r
+}\r
+\r
+/*\r
+ This function is called when the watchdog's first signal (WS0) goes high.\r
+ It uses the ResetSystem Runtime Service to reset the board.\r
+*/\r
+VOID\r
+EFIAPI\r
+WatchdogInterruptHandler (\r
+ IN HARDWARE_INTERRUPT_SOURCE Source,\r
+ IN EFI_SYSTEM_CONTEXT SystemContext\r
+ )\r
+{\r
+ STATIC CONST CHAR16 ResetString[] = L"The generic watchdog timer ran out.";\r
+\r
+ WatchdogDisable ();\r
+\r
+ mInterruptProtocol->EndOfInterrupt (mInterruptProtocol, Source);\r
+\r
+ gRT->ResetSystem (\r
+ EfiResetCold,\r
+ EFI_TIMEOUT,\r
+ StrSize (ResetString),\r
+ &ResetString\r
+ );\r
+\r
+ // If we got here then the reset didn't work\r
+ ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+ This function registers the handler NotifyFunction so it is called every time\r
+ the watchdog timer expires. It also passes the amount of time since the last\r
+ handler call to the NotifyFunction.\r
+ If NotifyFunction is not NULL and a handler is not already registered,\r
+ then the new handler is registered and EFI_SUCCESS is returned.\r
+ If NotifyFunction is NULL, and a handler is already registered,\r
+ then that handler is unregistered.\r
+ If an attempt is made to register a handler when a handler is already registered,\r
+ then EFI_ALREADY_STARTED is returned.\r
+ If an attempt is made to unregister a handler when a handler is not registered,\r
+ then EFI_INVALID_PARAMETER is returned.\r
+\r
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.\r
+ @param NotifyFunction The function to call when a timer interrupt fires.\r
+ This function executes at TPL_HIGH_LEVEL. The DXE\r
+ Core will register a handler for the timer interrupt,\r
+ so it can know how much time has passed. This\r
+ information is used to signal timer based events.\r
+ NULL will unregister the handler.\r
+\r
+ @retval EFI_SUCCESS The watchdog timer handler was registered.\r
+ @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already\r
+ registered.\r
+ @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not\r
+ previously registered.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+WatchdogRegisterHandler (\r
+ IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,\r
+ IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction\r
+ )\r
+{\r
+ // ERROR: This function is not supported.\r
+ // The watchdog will reset the board\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+/**\r
+ This function sets the amount of time to wait before firing the watchdog\r
+ timer to TimerPeriod 100 nS units. If TimerPeriod is 0, then the watchdog\r
+ timer is disabled.\r
+\r
+ @param This The EFI_WATCHDOG_TIMER_ARCH_PROTOCOL instance.\r
+ @param TimerPeriod The amount of time in 100 nS units to wait before the watchdog\r
+ timer is fired. If TimerPeriod is zero, then the watchdog\r
+ timer is disabled.\r
+\r
+ @retval EFI_SUCCESS The watchdog timer has been programmed to fire in Time\r
+ 100 nS units.\r
+ @retval EFI_DEVICE_ERROR A watchdog timer could not be programmed due to a device\r
+ error.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+WatchdogSetTimerPeriod (\r
+ IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,\r
+ IN UINT64 TimerPeriod // In 100ns units\r
+ )\r
+{\r
+ UINTN TimerVal;\r
+ EFI_STATUS Status;\r
+\r
+ // if TimerPerdiod is 0, this is a request to stop the watchdog.\r
+ if (TimerPeriod == 0) {\r
+ mNumTimerTicks = 0;\r
+ return WatchdogDisable ();\r
+ }\r
+\r
+ // Work out how many timer ticks will equate to TimerPeriod\r
+ mNumTimerTicks = (mTimerFrequencyHz * TimerPeriod) / TIME_UNITS_PER_SECOND;\r
+\r
+ //\r
+ // If the number of required ticks is greater than the max number the\r
+ // watchdog's offset register (WOR) can hold, we need to manually compute and\r
+ // set the compare register (WCV)\r
+ //\r
+ if (mNumTimerTicks > MAX_UINT32) {\r
+ //\r
+ // We need to enable the watchdog *before* writing to the compare register,\r
+ // because enabling the watchdog causes an "explicit refresh", which\r
+ // clobbers the compare register (WCV). In order to make sure this doesn't\r
+ // trigger an interrupt, set the offset to max.\r
+ //\r
+ Status = WatchdogWriteOffsetRegister (MAX_UINT32);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ WatchdogEnable ();\r
+ TimerVal = ArmGenericTimerGetTimerVal ();\r
+ Status = WatchdogWriteCompareRegister (TimerVal + mNumTimerTicks);\r
+ } else {\r
+ Status = WatchdogWriteOffsetRegister ((UINT32)mNumTimerTicks);\r
+ WatchdogEnable ();\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ This function retrieves the period of timer interrupts in 100 ns units,\r
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod\r
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is\r
+ returned, then the timer is currently disabled.\r
+\r
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.\r
+ @param TimerPeriod A pointer to the timer period to retrieve in 100\r
+ ns units. If 0 is returned, then the timer is\r
+ currently disabled.\r
+\r
+\r
+ @retval EFI_SUCCESS The timer period was returned in TimerPeriod.\r
+ @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+WatchdogGetTimerPeriod (\r
+ IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,\r
+ OUT UINT64 *TimerPeriod\r
+ )\r
+{\r
+ if (TimerPeriod == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ *TimerPeriod = ((TIME_UNITS_PER_SECOND / mTimerFrequencyHz) * mNumTimerTicks);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Interface structure for the Watchdog Architectural Protocol.\r
+\r
+ @par Protocol Description:\r
+ This protocol provides a service to set the amount of time to wait\r
+ before firing the watchdog timer, and it also provides a service to\r
+ register a handler that is invoked when the watchdog timer fires.\r
+\r
+ @par When the watchdog timer fires, control will be passed to a handler\r
+ if one has been registered. If no handler has been registered,\r
+ or the registered handler returns, then the system will be\r
+ reset by calling the Runtime Service ResetSystem().\r
+\r
+ @param RegisterHandler\r
+ Registers a handler that will be called each time the\r
+ watchdogtimer interrupt fires. TimerPeriod defines the minimum\r
+ time between timer interrupts, so TimerPeriod will also\r
+ be the minimum time between calls to the registered\r
+ handler.\r
+ NOTE: If the watchdog resets the system in hardware, then\r
+ this function will not have any chance of executing.\r
+\r
+ @param SetTimerPeriod\r
+ Sets the period of the timer interrupt in 100 nS units.\r
+ This function is optional, and may return EFI_UNSUPPORTED.\r
+ If this function is supported, then the timer period will\r
+ be rounded up to the nearest supported timer period.\r
+\r
+ @param GetTimerPeriod\r
+ Retrieves the period of the timer interrupt in 100 nS units.\r
+\r
+**/\r
+EFI_WATCHDOG_TIMER_ARCH_PROTOCOL gWatchdogTimer = {\r
+ (EFI_WATCHDOG_TIMER_REGISTER_HANDLER) WatchdogRegisterHandler,\r
+ (EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD) WatchdogSetTimerPeriod,\r
+ (EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD) WatchdogGetTimerPeriod\r
+};\r
+\r
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+GenericWatchdogEntry (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE Handle;\r
+\r
+ //\r
+ // Make sure the Watchdog Timer Architectural Protocol has not been installed\r
+ // in the system yet.\r
+ // This will avoid conflicts with the universal watchdog\r
+ //\r
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolGuid);\r
+\r
+ mTimerFrequencyHz = ArmGenericTimerGetTimerFreq ();\r
+ ASSERT (mTimerFrequencyHz != 0);\r
+\r
+ // Register for an ExitBootServicesEvent\r
+ Status = gBS->CreateEvent (\r
+ EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY,\r
+ WatchdogExitBootServicesEvent, NULL, &EfiExitBootServicesEvent\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ // Install interrupt handler\r
+ Status = gBS->LocateProtocol (\r
+ &gHardwareInterruptProtocolGuid,\r
+ NULL,\r
+ (VOID **)&mInterruptProtocol\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ Status = mInterruptProtocol->RegisterInterruptSource (\r
+ mInterruptProtocol,\r
+ FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),\r
+ WatchdogInterruptHandler\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ // Install the Timer Architectural Protocol onto a new handle\r
+ Handle = NULL;\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &Handle,\r
+ &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer,\r
+ NULL\r
+ );\r
+ }\r
+ }\r
+ }\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ // The watchdog failed to initialize\r
+ ASSERT (FALSE);\r
+ }\r
+\r
+ mNumTimerTicks = 0;\r
+ WatchdogDisable ();\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+#\r
+# Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010016\r
+ BASE_NAME = GenericWatchdogDxe\r
+ FILE_GUID = 0619f5c2-4858-4caa-a86a-73a21a18df6b\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+\r
+ ENTRY_POINT = GenericWatchdogEntry\r
+\r
+[Sources.common]\r
+ GenericWatchdogDxe.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec\r
+\r
+[LibraryClasses]\r
+ ArmGenericTimerCounterLib\r
+ BaseLib\r
+ BaseMemoryLib\r
+ DebugLib\r
+ IoLib\r
+ PcdLib\r
+ UefiLib\r
+ UefiBootServicesTableLib\r
+ UefiDriverEntryPoint\r
+ UefiRuntimeServicesTableLib\r
+\r
+[FixedPcd]\r
+ gArmJunoTokenSpaceGuid.PcdGenericWatchdogControlBase\r
+ gArmJunoTokenSpaceGuid.PcdGenericWatchdogRefreshBase\r
+ gArmJunoTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum\r
+\r
+[Protocols]\r
+ gEfiWatchdogTimerArchProtocolGuid\r
+ gHardwareInterruptProtocolGuid\r
+\r
+[Depex]\r
+ gHardwareInterruptProtocolGuid\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef __ARM_JUNO_H__\r
+#define __ARM_JUNO_H__\r
+\r
+#include <VExpressMotherBoard.h>\r
+\r
+/***********************************************************************************\r
+// Platform Memory Map\r
+************************************************************************************/\r
+\r
+// Motherboard Peripheral and On-chip peripheral\r
+#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000\r
+\r
+// NOR Flash 0\r
+#define ARM_VE_SMB_NOR0_BASE 0x08000000\r
+#define ARM_VE_SMB_NOR0_SZ SIZE_64MB\r
+\r
+// Off-Chip peripherals (USB, Ethernet, VRAM)\r
+#define ARM_VE_SMB_PERIPH_BASE 0x18000000\r
+#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_2MB)\r
+\r
+// On-Chip non-secure ROM\r
+#define ARM_JUNO_NON_SECURE_ROM_BASE 0x1F000000\r
+#define ARM_JUNO_NON_SECURE_ROM_SZ SIZE_16MB\r
+\r
+// On-Chip Peripherals\r
+#define ARM_JUNO_PERIPHERALS_BASE 0x20000000\r
+#define ARM_JUNO_PERIPHERALS_SZ 0x0E000000\r
+\r
+// On-Chip non-secure SRAM\r
+#define ARM_JUNO_NON_SECURE_SRAM_BASE 0x2E000000\r
+#define ARM_JUNO_NON_SECURE_SRAM_SZ SIZE_16MB\r
+\r
+// SOC peripherals (HDLCD, UART, I2C, I2S, USB, SMC-PL354, etc)\r
+#define ARM_JUNO_SOC_PERIPHERALS_BASE 0x7FF50000\r
+#define ARM_JUNO_SOC_PERIPHERALS_SZ (SIZE_64KB * 9)\r
+\r
+// 6GB of DRAM from the 64bit address space\r
+#define ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE 0x0880000000\r
+#define ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ (SIZE_2GB + SIZE_4GB)\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD\r
+* License which accompanies this distribution. The full text of the license\r
+* may be found at http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+#ifndef __GENERIC_WATCHDOG_H__\r
+#define __GENERIC_WATCHDOG_H__\r
+\r
+// Refresh Frame:\r
+#define GENERIC_WDOG_REFRESH_REG ((UINT32)FixedPcdGet32 (PcdGenericWatchdogRefreshBase) + 0x000)\r
+\r
+// Control Frame:\r
+#define GENERIC_WDOG_CONTROL_STATUS_REG ((UINT32)FixedPcdGet32 (PcdGenericWatchdogControlBase) + 0x000)\r
+#define GENERIC_WDOG_OFFSET_REG ((UINT32)FixedPcdGet32 (PcdGenericWatchdogControlBase) + 0x008)\r
+#define GENERIC_WDOG_COMPARE_VALUE_REG ((UINT32)FixedPcdGet32 (PcdGenericWatchdogControlBase) + 0x010)\r
+\r
+// Values of bit 0 of the Control/Status Register\r
+#define GENERIC_WDOG_ENABLED 1\r
+#define GENERIC_WDOG_DISABLED 0\r
+\r
+#endif // __GENERIC_WATCHDOG_H__\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <AsmMacroIoLibV8.h>\r
+#include <Library/ArmLib.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
+\r
+\r
+PrimaryCoreMpid: .word 0x0\r
+\r
+//UINTN\r
+//ArmPlatformGetCorePosition (\r
+// IN UINTN MpId\r
+// );\r
+// With this function: CorePos = (ClusterId * 2) + CoreId\r
+ASM_PFX(ArmPlatformGetCorePosition):\r
+ and x1, x0, #ARM_CORE_MASK\r
+ and x0, x0, #ARM_CLUSTER_MASK\r
+ add x0, x1, x0, LSR #7\r
+ ret\r
+\r
+//UINTN\r
+//ArmPlatformGetPrimaryCoreMpId (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
+ ldr x0, =PrimaryCoreMpid\r
+ ldrh w0, [x0]\r
+ ret\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ASM_PFX(ArmPlatformIsPrimaryCore):\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, x1)\r
+ ldrh w1, [x1]\r
+ and x0, x0, x1\r
+\r
+ ldr x1, =PrimaryCoreMpid\r
+ ldrh w1, [x1]\r
+\r
+ cmp w0, w1\r
+ mov x0, #1\r
+ mov x1, #0\r
+ csel x0, x0, x1, eq\r
+ ret\r
+\r
+ASM_PFX(ArmPlatformPeiBootAction):\r
+ // The trusted firmware passes the primary CPU MPID through x0 register.\r
+ // Save it in a variable.\r
+ ldr x1, =PrimaryCoreMpid\r
+ str w0, [x1]\r
+ ret\r
+\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <AsmMacroIoLibV8.h>\r
+#include <Library/ArmLib.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
+\r
+\r
+PrimaryCoreMpid: .word 0x0\r
+\r
+//\r
+// Return the core position from the value of its MpId register\r
+//\r
+// This function returns the core position from the position 0 in the processor.\r
+// This function might be called from assembler before any stack is set.\r
+//\r
+// @return Return the core position\r
+//\r
+//UINTN\r
+//ArmPlatformGetCorePosition (\r
+// IN UINTN MpId\r
+// );\r
+// With this function: CorePos = (ClusterId * 2) + CoreId\r
+ASM_PFX(ArmPlatformGetCorePosition):\r
+ and r1, r0, #ARM_CORE_MASK\r
+ and r0, r0, #ARM_CLUSTER_MASK\r
+ add r0, r1, r0, LSR #7\r
+ bx lr\r
+\r
+//\r
+// Return the MpId of the primary core\r
+//\r
+// This function returns the MpId of the primary core.\r
+// This function might be called from assembler before any stack is set.\r
+//\r
+// @return Return the MpId of the primary core\r
+//\r
+//UINTN\r
+//ArmPlatformGetPrimaryCoreMpId (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
+ ldr r0, =PrimaryCoreMpid\r
+ ldr r0, [r0]\r
+ bx lr\r
+\r
+//\r
+// Return a non-zero value if the callee is the primary core\r
+//\r
+// This function returns a non-zero value if the callee is the primary core.\r
+// The primary core is the core responsible to initialize the hardware and run UEFI.\r
+// This function might be called from assembler before any stack is set.\r
+//\r
+// @return Return a non-zero value if the callee is the primary core.\r
+//\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ASM_PFX(ArmPlatformIsPrimaryCore):\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r
+ ldr r1, [r1]\r
+ and r0, r0, r1\r
+\r
+ ldr r1, =PrimaryCoreMpid\r
+ ldr r1, [r1]\r
+\r
+ cmp r0, r1\r
+ moveq r0, #1\r
+ movne r0, #0\r
+ bx lr\r
+\r
+//\r
+// First platform specific function to be called in the PEI phase\r
+//\r
+// This function is actually the first function called by the PrePi\r
+// or PrePeiCore modules. It allows to retrieve arguments passed to\r
+// the UEFI firmware through the CPU registers.\r
+//\r
+ASM_PFX(ArmPlatformPeiBootAction):\r
+ // The trusted firmware passes the primary CPU MPID through r0 register.\r
+ // Save it in a variable.\r
+ ldr r1, =PrimaryCoreMpid\r
+ str r0, [r1]\r
+ bx lr\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <Ppi/ArmMpCoreInfo.h>\r
+\r
+#include <ArmPlatform.h>\r
+\r
+ARM_CORE_INFO mJunoInfoTable[] = {\r
+ {\r
+ // Cluster 0, Core 0\r
+ 0x0, 0x0,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
+ (UINT64)0xFFFFFFFF\r
+ },\r
+ {\r
+ // Cluster 0, Core 1\r
+ 0x0, 0x1,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
+ (UINT64)0xFFFFFFFF\r
+ },\r
+ {\r
+ // Cluster 1, Core 0\r
+ 0x1, 0x0,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
+ (UINT64)0xFFFFFFFF\r
+ },\r
+ {\r
+ // Cluster 1, Core 1\r
+ 0x1, 0x1,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
+ (UINT64)0xFFFFFFFF\r
+ },\r
+ {\r
+ // Cluster 1, Core 2\r
+ 0x1, 0x2,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
+ (UINT64)0xFFFFFFFF\r
+ },\r
+ {\r
+ // Cluster 1, Core 3\r
+ 0x1, 0x3,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
+ (UINT64)0xFFFFFFFF\r
+ }\r
+};\r
+\r
+/**\r
+ Return the current Boot Mode\r
+\r
+ This function returns the boot reason on the platform\r
+\r
+ @return Return the current Boot Mode of the platform\r
+\r
+**/\r
+EFI_BOOT_MODE\r
+ArmPlatformGetBootMode (\r
+ VOID\r
+ )\r
+{\r
+ return BOOT_WITH_FULL_CONFIGURATION;\r
+}\r
+\r
+/**\r
+ Initialize controllers that must setup in the normal world\r
+\r
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim\r
+ in the PEI phase.\r
+\r
+**/\r
+RETURN_STATUS\r
+ArmPlatformInitialize (\r
+ IN UINTN MpId\r
+ )\r
+{\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Initialize the system (or sometimes called permanent) memory\r
+\r
+ This memory is generally represented by the DRAM.\r
+\r
+**/\r
+VOID\r
+ArmPlatformInitializeSystemMemory (\r
+ VOID\r
+ )\r
+{\r
+}\r
+\r
+EFI_STATUS\r
+PrePeiCoreGetMpCoreInfo (\r
+ OUT UINTN *CoreCount,\r
+ OUT ARM_CORE_INFO **ArmCoreTable\r
+ )\r
+{\r
+ // Only support one cluster\r
+ *CoreCount = sizeof(mJunoInfoTable) / sizeof(ARM_CORE_INFO);\r
+ *ArmCoreTable = mJunoInfoTable;\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore\r
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;\r
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };\r
+\r
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {\r
+ {\r
+ EFI_PEI_PPI_DESCRIPTOR_PPI,\r
+ &mArmMpCoreInfoPpiGuid,\r
+ &mMpCoreInfoPpi\r
+ }\r
+};\r
+\r
+VOID\r
+ArmPlatformGetPlatformPpiList (\r
+ OUT UINTN *PpiListSize,\r
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
+ )\r
+{\r
+ *PpiListSize = sizeof(gPlatformPpiTable);\r
+ *PpiList = gPlatformPpiTable;\r
+}\r
--- /dev/null
+#\r
+# Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmJunoLib\r
+ FILE_GUID = 87c525cd-e1a2-469e-994c-c28cd0c7bd0d\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ArmPlatformLib\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec\r
+\r
+[LibraryClasses]\r
+ IoLib\r
+ ArmLib\r
+ HobLib\r
+ MemoryAllocationLib\r
+ SerialPortLib\r
+\r
+[Sources.common]\r
+ ArmJuno.c\r
+ ArmJunoMem.c\r
+\r
+[Sources.AARCH64]\r
+ AArch64/ArmJunoHelper.S | GCC\r
+\r
+[Sources.ARM]\r
+ Arm/ArmJunoHelper.S | GCC\r
+\r
+[FeaturePcd]\r
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
+\r
+[FixedPcd]\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize\r
+ gArmTokenSpaceGuid.PcdFvBaseAddress\r
+\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+\r
+#include <ArmPlatform.h>\r
+\r
+// The total number of descriptors, including the final "end-of-table" descriptor.\r
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12\r
+\r
+// DDR attributes\r
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
+\r
+/**\r
+ Return the Virtual Memory Map of your platform\r
+\r
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r
+\r
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r
+ Virtual Memory mapping. This array must be ended by a zero-filled\r
+ entry\r
+\r
+**/\r
+VOID\r
+ArmPlatformGetVirtualMemoryMap (\r
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
+ )\r
+{\r
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;\r
+ UINTN Index = 0;\r
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;\r
+\r
+ ASSERT (VirtualMemoryMap != NULL);\r
+\r
+ //\r
+ // Declared the additional 6GB of memory\r
+ //\r
+ ResourceAttributes =\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED;\r
+\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY,\r
+ ResourceAttributes,\r
+ ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE,\r
+ ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ);\r
+\r
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r
+ if (VirtualMemoryTable == NULL) {\r
+ return;\r
+ }\r
+\r
+ if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
+ CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
+ } else {\r
+ CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
+ }\r
+\r
+ // SMB CS0 - NOR0 Flash\r
+ VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;\r
+ VirtualMemoryTable[Index].Length = SIZE_256KB * 255;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+ // Environment Variables region\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);\r
+ VirtualMemoryTable[Index].Length = SIZE_64KB * 4;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // SMB CS2 & CS3 - Off-chip (motherboard) peripherals\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // Juno OnChip non-secure ROM\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_NON_SECURE_ROM_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_NON_SECURE_ROM_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_JUNO_NON_SECURE_ROM_SZ;\r
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
+\r
+ // Juno OnChip peripherals\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_PERIPHERALS_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_PERIPHERALS_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_JUNO_PERIPHERALS_SZ;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // Juno OnChip non-secure SRAM\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_NON_SECURE_SRAM_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_NON_SECURE_SRAM_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_JUNO_NON_SECURE_SRAM_SZ;\r
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
+\r
+ // Juno SOC peripherals\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_SOC_PERIPHERALS_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_SOC_PERIPHERALS_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_JUNO_SOC_PERIPHERALS_SZ;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // DDR - 2GB\r
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);\r
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);\r
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);\r
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
+\r
+ // DDR - 6GB\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ;\r
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
+\r
+ // End of Table\r
+ VirtualMemoryTable[++Index].PhysicalBase = 0;\r
+ VirtualMemoryTable[Index].VirtualBase = 0;\r
+ VirtualMemoryTable[Index].Length = 0;\r
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+\r
+ ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);\r
+\r
+ *VirtualMemoryMap = VirtualMemoryTable;\r
+}\r
--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ **/\r
+\r
+#include <PiDxe.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/NorFlashPlatformLib.h>\r
+#include <ArmPlatform.h>\r
+\r
+NOR_FLASH_DESCRIPTION mNorFlashDevices[] = {\r
+ {\r
+ ARM_VE_SMB_NOR0_BASE,\r
+ ARM_VE_SMB_NOR0_BASE,\r
+ SIZE_256KB * 255,\r
+ SIZE_256KB,\r
+ {0xE7223039, 0x5836, 0x41E1, { 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5E, 0x59} }\r
+ },\r
+ {\r
+ ARM_VE_SMB_NOR0_BASE,\r
+ ARM_VE_SMB_NOR0_BASE + SIZE_256KB * 255,\r
+ SIZE_64KB * 4,\r
+ SIZE_64KB,\r
+ {0x02118005, 0x9DA7, 0x443A, { 0x92, 0xD5, 0x78, 0x1F, 0x02, 0x2A, 0xED, 0xBB } }\r
+ },\r
+};\r
+\r
+EFI_STATUS\r
+NorFlashPlatformInitialization (\r
+ VOID\r
+ )\r
+{\r
+ // Everything seems ok so far, so now we need to disable the platform-specific\r
+ // flash write protection for Versatile Express\r
+ if ((MmioRead32 (ARM_VE_SYS_FLASH) & 0x1) == 0) {\r
+ // Writing to NOR FLASH is disabled, so enable it\r
+ MmioWrite32 (ARM_VE_SYS_FLASH, 1);\r
+ DEBUG((DEBUG_BLKIO, "NorFlashPlatformInitialization: informational - Had to enable HSYS_FLASH flag.\n" ));\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+NorFlashPlatformGetDevices (\r
+ OUT NOR_FLASH_DESCRIPTION **NorFlashDevices,\r
+ OUT UINT32 *Count\r
+ )\r
+{\r
+ if ((NorFlashDevices == NULL) || (Count == NULL)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ *NorFlashDevices = mNorFlashDevices;\r
+ *Count = sizeof (mNorFlashDevices) / sizeof (NOR_FLASH_DESCRIPTION);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+#/** @file\r
+#\r
+# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = NorFlashJunoLib\r
+ FILE_GUID = 3eb6cbc4-ce95-11e2-b1bd-00241d0c1ba8\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = NorFlashPlatformLib\r
+\r
+[Sources.common]\r
+ NorFlashJuno.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ DebugLib\r
+ IoLib\r
--- /dev/null
+#
+# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+# Define the following variables to specify an alternative toolchain to the one located in your PATH:
+# - RVCT_TOOLS_PATH: for RVCT and RVCTLINUX toolchains
+# - ARMGCC_TOOLS_PATH: for ARMGCC toolchain
+# - ARMLINUXGCC_TOOLS_PATH: for ARMLINUXGCC
+
+EDK2_TOOLCHAIN ?= GCC49
+GCC49_AARCH64_PREFIX ?= aarch64-none-elf-
+EDK2_ARCH ?= AARCH64
+EDK2_BUILD ?= DEBUG
+EDK2_DSC = ArmPlatformPkg/ArmJunoPkg/ArmJuno.dsc
+DEST_BIN_ROOT ?=
+
+ifeq ($(EDK2_DSC),"")
+ $(error The Makefile macro 'EDK2_DSC' must be defined with an EDK2 DSC file.)
+endif
+
+ifeq ("$(OS)","Windows_NT")
+export WORKSPACE?=$(PWD)
+export EDK_TOOLS_PATH ?= $(WORKSPACE)\BaseTools
+else
+export WORKSPACE?=$(PWD)
+endif
+
+# Define the destination of the Firmware Image Package (FIP) if not defined
+ifndef JUNO_FIP
+ ifdef DEST_BIN_ROOT
+ JUNO_FIP=$(DEST_BIN_ROOT)/fip.bin
+ else
+ JUNO_FIP=fip.bin
+ endif
+endif
+
+SHELL := /bin/bash
+SILENT ?= @
+ECHO ?= echo
+MAKE ?= make -i -k
+RM ?= rm -f
+CP ?= cp
+
+.PHONY: all clean
+
+EDK2_CONF = Conf/BuildEnv.sh Conf/build_rule.txt Conf/target.txt Conf/tools_def.txt
+
+all: $(EDK2_CONF)
+ifeq ("$(OS)","Windows_NT")
+ build -a $(EDK2_ARCH) -p $(EDK2_DSC) -t $(EDK2_TOOLCHAIN) -b $(EDK2_BUILD) $(EDK2_MACROS)
+else
+ . ./edksetup.sh; GCC49_AARCH64_PREFIX=$(GCC49_AARCH64_PREFIX) build -a $(EDK2_ARCH) -p $(EDK2_DSC) -t $(EDK2_TOOLCHAIN) -b $(EDK2_BUILD) $(EDK2_MACROS)
+endif
+ifeq ("$(OS)","Windows_NT")
+ $(SILENT)$(ECHO) "Warning: The UEFI Firmware must be added to the Firmware Image Package (FIP)."
+else
+ $(SILENT)which fip_create ; \
+ if [ $$? -ne 0 ]; then \
+ $(ECHO) "Warning: 'fip_create' tool is not in the PATH. The UEFI binary will not be added in the Firmware Image Package (FIP)."; \
+ else \
+ fip_create --bl33 $(WORKSPACE)/Build/ArmJuno/$(EDK2_BUILD)_$(EDK2_TOOLCHAIN)/FV/BL33_AP_UEFI.fd --dump $(JUNO_FIP); \
+ fi
+endif
+
+$(EDK2_CONF):
+ifeq ("$(OS)","Windows_NT")
+ copy $(EDK_TOOLS_PATH)\Conf\build_rule.template Conf\build_rule.txt
+ copy $(EDK_TOOLS_PATH)\Conf\FrameworkDatabase.template Conf\FrameworkDatabase.txt
+ copy $(EDK_TOOLS_PATH)\Conf\target.template Conf\target.txt
+ copy $(EDK_TOOLS_PATH)\Conf\tools_def.template Conf\tools_def.txt
+else
+ . ./edksetup.sh; $(MAKE) -C BaseTools
+endif
+
+clean:
+ifeq ("$(OS)","Windows_NT")
+ build -a $(EDK2_ARCH) -p $(EDK2_DSC) -t $(EDK2_TOOLCHAIN) -b $(EDK2_BUILD) $(EDK2_MACROS) cleanall
+else
+ . ./edksetup.sh; build -a $(EDK2_ARCH) -p $(EDK2_DSC) -t $(EDK2_TOOLCHAIN) -b $(EDK2_BUILD) $(EDK2_MACROS) cleanall; \
+ rm -Rf $(EDK2_CONF) Conf/.cache
+endif
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