\r
/* - Set the destination frame index CDFI[31:0]*/\r
MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);\r
- \r
+ \r
+ MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);\r
+\r
+ // Enable all the status bits since we are polling\r
+ MmioWrite32 (DMA4_CICR (Channel), DMA4_CICR_ENABLE_ALL);\r
+ MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET);\r
+\r
/* 2) Start the DMA transfer by Setting the enable bit CCR[7]=1 */\r
/*--------------------------------------------------------------*/\r
//write enable bit\r
- MmioOr32 (DMA4_CCR(0), DMA4_CCR_ENABLE); //Launch transfer
+ MmioOr32 (DMA4_CCR(Channel), DMA4_CCR_ENABLE); //Launch transfer
return EFI_SUCCESS;
}
Turn of DMA channel configured by EnableDma().\r
\r
@param Channel DMA Channel to configure\r
+ @param SuccesMask Bits in DMA4_CSR register indicate EFI_SUCCESS\r
+ @param ErrorMask Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR\r
\r
@retval EFI_SUCCESS DMA hardware disabled\r
@retval EFI_INVALID_PARAMETER Channel is not valid\r
EFI_STATUS
EFIAPI
DisableDmaChannel (
- IN UINTN Channel
+ IN UINTN Channel,
+ IN UINT32 SuccessMask,
+ IN UINT32 ErrorMask
)
{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT32 Reg;
+
+
if (Channel > DMA4_MAX_CHANNEL) {
return EFI_INVALID_PARAMETER;
}
+ do {
+ Reg = MmioRead32 (DMA4_CSR(Channel));
+ if ((Reg & ErrorMask) != 0) {
+ Status = EFI_DEVICE_ERROR;
+ DEBUG ((EFI_D_ERROR, "DMA Error (%d) %x\n", Channel, Reg));
+ break;
+ }
+ } while ((Reg & SuccessMask) != SuccessMask);
+
+
+ // Disable all status bits and clear them
+ MmioWrite32 (DMA4_CICR (Channel), 0);\r
+ MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET);
+
MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE));
- return EFI_SUCCESS;
+ return Status;
}
+
+
/** \r
Provides the DMA controller-specific addresses needed to access system memory.\r
\r
)
{
EFI_STATUS Status;
- UINTN RetryCount = 0;
+ UINTN DmaSize = 0;
UINTN Cmd = 0;
UINTN CmdInterruptEnable;
UINTN CmdArgument;
OMAP_DMA4 Dma4;
DMA_MAP_OPERATION DmaOperation;
+CpuDeadLoop ();
+ // Map passed in buffer for DMA xfer
+ DmaSize = BlockCount * This->Media->BlockSize;
+ Status = DmaMap (DmaOperation, Buffer, &DmaSize, &BufferAddress, &BufferMap);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ ZeroMem (&DmaOperation, sizeof (DMA_MAP_OPERATION));
+ \r
+ Dma4.DataType = 2; // DMA4_CSDPi[1:0] 32-bit elements from MMCHS_DATA\r
+ Dma4.SourceEndiansim = 0; // DMA4_CSDPi[21] \r
+ Dma4.DestinationEndianism = 0; // DMA4_CSDPi[19]\r
+ Dma4.SourcePacked = 0; // DMA4_CSDPi[6]\r
+ Dma4.DestinationPacked = 0; // DMA4_CSDPi[13]\r
+ Dma4.NumberOfElementPerFrame = This->Media->BlockSize/4; // DMA4_CENi (TRM 4K is optimum value) \r
+ Dma4.NumberOfFramePerTransferBlock = BlockCount; // DMA4_CFNi \r
+ Dma4.ReadPriority = 0; // DMA4_CCRi[6] Low priority read \r
+ Dma4.WritePriority = 0; // DMA4_CCRi[23] Prefetech disabled\r
//Populate the command information based on the operation type.
if (OperationType == READ) {
Cmd = CMD18; //Multiple block read
CmdInterruptEnable = CMD18_INT_EN;
DmaOperation = MapOperationBusMasterCommonBuffer;
+
+ Dma4.ReadPortAccessType =0 ; // DMA4_CSDPi[8:7] Can not burst MMCHS_DATA reg\r
+ Dma4.WritePortAccessType = 3; // DMA4_CSDPi[15:14] Memory burst 16x32\r
+ Dma4.WriteMode = 1; // DMA4_CSDPi[17:16] Write posted\r
+ \r
+ Dma4.SourceStartAddress = MMCHS_DATA; // DMA4_CSSAi\r
+ Dma4.DestinationStartAddress = (UINT32)BufferAddress; // DMA4_CDSAi\r
+ Dma4.SourceElementIndex = 1; // DMA4_CSEi\r
+ Dma4.SourceFrameIndex = 0x200; // DMA4_CSFi\r
+ Dma4.DestinationElementIndex = 1; // DMA4_CDEi\r
+ Dma4.DestinationFrameIndex = 0; // DMA4_CDFi\r
+\r
+ Dma4.ReadPortAccessMode = 0; // DMA4_CCRi[13:12] Always read MMCHS_DATA\r
+ Dma4.WritePortAccessMode = 1; // DMA4_CCRi[15:14] Post increment memory address\r
+ Dma4.ReadRequestNumber = 0x1e; // DMA4_CCRi[4:0] Syncro with MMCA_DMA_RX (61) \r
+ Dma4.WriteRequestNumber = 1; // DMA4_CCRi[20:19] Syncro upper 0x3e == 62 (one based)
+
} else if (OperationType == WRITE) {
Cmd = CMD25; //Multiple block write
CmdInterruptEnable = CMD25_INT_EN;
DmaOperation = MapOperationBusMasterRead;
- } else {
- return EFI_INVALID_PARAMETER;
- }
- // Map passed in buffer for DMA xfer
- RetryCount = BlockCount * This->Media->BlockSize;
- Status = DmaMap (DmaOperation, Buffer, &RetryCount, &BufferAddress, &BufferMap);
- if (EFI_ERROR (Status)) {
- return Status;
- }
+ Dma4.ReadPortAccessType = 3; // DMA4_CSDPi[8:7] Memory burst 16x32\r
+ Dma4.WritePortAccessType = 0; // DMA4_CSDPi[15:14] Can not burst MMCHS_DATA reg\r
+ Dma4.WriteMode = 1; // DMA4_CSDPi[17:16] Write posted ???\r
+ \r
+ Dma4.SourceStartAddress = (UINT32)BufferAddress; // DMA4_CSSAi\r
+ Dma4.DestinationStartAddress = MMCHS_DATA; // DMA4_CDSAi\r
+ Dma4.SourceElementIndex = 1; // DMA4_CSEi\r
+ Dma4.SourceFrameIndex = 0x200; // DMA4_CSFi\r
+ Dma4.DestinationElementIndex = 1; // DMA4_CDEi\r
+ Dma4.DestinationFrameIndex = 0; // DMA4_CDFi\r
+\r
+ Dma4.ReadPortAccessMode = 1; // DMA4_CCRi[13:12] Post increment memory address\r
+ Dma4.WritePortAccessMode = 0; // DMA4_CCRi[15:14] Always write MMCHS_DATA\r
+ Dma4.ReadRequestNumber = 0x1d; // DMA4_CCRi[4:0] Syncro with MMCA_DMA_TX (60) \r
+ Dma4.WriteRequestNumber = 1; // DMA4_CCRi[20:19] Syncro upper 0x3d == 61 (one based)
- #if 0
- MmioWrite32 (DMA4_CSDP(0), DMA4_CSDP_DATA_TYPE32 | DMA4_CSDP_SRC_BURST_EN64 | DMA4_CSDP_WRITE_MODE_POSTED);
- MmioWrite32 (DMA4_CEN(0), 0x4096); // Channel Element number
- MmioWrite32 (DMA4_CFN(0), 0x1); // Channel Frame number
- if () {
- MmioWrite32 (DMA4_CCR(0), X | DMA4_CCR_FS_PACKET | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE | DMA4_CCR_DST_AMODE_POST_INC | DMA4_CCR_SEL_SRC_DEST_SYNC_SOURCE);
- MmioWrite32 (DMA4_CSSA(0), MMCHS_DATA); // Src is SD Card
- MmioWrite32 (DMA4_CDSA(0), (UINT32)BufferAddress); // Dst memory
} else {
- MmioWrite32 (DMA4_CCR(0), X | DMA4_CCR_FS_PACKET | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE | DMA4_CCR_SRC_AMODE_POST_INC);
- MmioWrite32 (DMA4_CSSA(0), (UINT32)BufferAddress); // Src memory
- MmioWrite32 (DMA4_CDSA(0), MMCHS_DATA); // Dst SD Card
+ return EFI_INVALID_PARAMETER;
}
- MmioWrite32 (DMA4_CSE(0), 1);
- MmioWrite32 (DMA4_CSF(0), This->Media->BlockSize);
- MmioWrite32 (DMA4_CDE(0), 1);
-#endif
- Dma4.DataType = 0; // DMA4_CSDPi[1:0]\r
- Dma4.ReadPortAccessType =0; // DMA4_CSDPi[8:7]\r
- Dma4.WritePortAccessType =0; // DMA4_CSDPi[15:14]\r
- Dma4.SourceEndiansim = 0; // DMA4_CSDPi[21]\r
- Dma4.DestinationEndianism = 0; // DMA4_CSDPi[19]\r
- Dma4.WriteMode = 0; // DMA4_CSDPi[17:16]\r
- Dma4.SourcePacked = 0; // DMA4_CSDPi[6]\r
- Dma4.DestinationPacked = 0; // DMA4_CSDPi[13]\r
- Dma4.NumberOfElementPerFrame = 0; // DMA4_CENi\r
- Dma4.NumberOfFramePerTransferBlock = 0; // DMA4_CFNi\r
- Dma4.SourceStartAddress = 0; // DMA4_CSSAi\r
- Dma4.DestinationStartAddress = 0; // DMA4_CDSAi\r
- Dma4.SourceElementIndex = 0; // DMA4_CSEi\r
- Dma4.SourceFrameIndex = 0; // DMA4_CSFi\r
- Dma4.DestinationElementIndex = 0; // DMA4_CDEi\r
- Dma4.DestinationFrameIndex = 0; // DMA4_CDFi\r
- Dma4.ReadPortAccessMode = 0; // DMA4_CCRi[13:12]\r
- Dma4.WritePortAccessMode = 0; // DMA4_CCRi[15:14]\r
- Dma4.ReadPriority = 0; // DMA4_CCRi[6]\r
- Dma4.WritePriority = 0; // DMA4_CCRi[23]\r
- Dma4.ReadRequestNumber = 0; // DMA4_CCRi[4:0]\r
- Dma4.WriteRequestNumber = 0; // DMA4_CCRi[20:19]
+
EnableDmaChannel (2, &Dma4);
return Status;
}
- DisableDmaChannel (2);
+ DisableDmaChannel (2, DMA4_CSR_BLOCK, DMA4_CSR_ERR);
Status = DmaUnmap (BufferMap);
return Status;
return Status;
}
+#define MAX_MMCHS_TRANSFER_SIZE 0x4000
EFI_STATUS
SdReadWrite (
EFI_STATUS Status = EFI_SUCCESS;
UINTN RetryCount = 0;
UINTN BlockCount;
- UINTN BytesToBeTranferedThisPass;
+ UINTN BytesToBeTranferedThisPass = 0;
UINTN BytesRemainingToBeTransfered;
EFI_TPL OldTpl;\r
BOOLEAN Update;\r
Status = gBS->CreateEvent (EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_CALLBACK, TimerCallback, NULL, &gTimerEvent);
ASSERT_EFI_ERROR (Status);
- Status = gBS->SetTimer (gTimerEvent, TimerPeriodic, 1000000ULL); // make me a PCD
+ Status = gBS->SetTimer (gTimerEvent, TimerPeriodic, FixedPcdGet32 (PcdMmchsTimerFreq100NanoSeconds));
ASSERT_EFI_ERROR (Status);
//Publish BlockIO.
projects / mirror_edk2.git / commitdiff