UefiCpuPkg/Include: Update MSEG structure comments

Add comments to describe fields of MSEG_HEADER and
add define values for the MonitorFeatures field.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>

diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index af3f39de94ccaaa615a10dd55a55db7a20119ff0..633e54d4e050e6612d75afef7c45b976f1a972b7 100644 (file)
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -520,7 +520,19 @@ typedef union {
   field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
 **/\r
 typedef struct {\r
+  ///\r
+  /// Different processors may use different MSEG revision identifiers. These\r
+  /// identifiers enable software to avoid using an MSEG header formatted for\r
+  /// one processor on a processor that uses a different format. Software can\r
+  /// discover the MSEG revision identifier that a processor uses by reading\r
+  /// the VMX capability MSR IA32_VMX_MISC.\r
+  //\r
   UINT32  MsegHeaderRevision;\r
+  ///\r
+  /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field\r
+  /// is the IA-32e mode SMM feature bit. It indicates whether the logical\r
+  /// processor will be in IA-32e mode after the STM is activated.\r
+  ///\r
   UINT32  MonitorFeatures;\r
   UINT32  GdtrLimit;\r
   UINT32  GdtrBaseOffset;\r
@@ -528,12 +540,19 @@ typedef struct {
   UINT32  EipOffset;\r
   UINT32  EspOffset;\r
   UINT32  Cr3Offset;\r
-  //\r
-  // Pad header so total size is 2KB\r
-  //\r
+  ///\r
+  /// Pad header so total size is 2KB\r
+  ///\r
   UINT8   Reserved[SIZE_2KB - 8 * sizeof (UINT32)];\r
 } MSEG_HEADER;\r
 \r
+///\r
+/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER\r
+///\r
+#define STM_FEATURES_IA32E 0x1\r
+///\r
+/// @}\r
+///\r
 \r
 /**\r
   Base address of the logical processor's SMRAM image (RO, SMM only). If\r