UefiCpuPkg/Include: Add Pentium MSR include file

Add Pentium MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-20.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>

diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
new file mode 100644 (file)
index 0000000..a8916b4
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
@@ -0,0 +1,121 @@
+/** @file\r
+  MSR Definitions for Pentium Processors.\r
+\r
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+  are provided for MSRs that contain one or more bit fields.  If the MSR value\r
+  returned is a single 32-bit or 64-bit value, then a data structure is not\r
+  provided for that MSR.\r
+\r
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+  @par Specification Reference:\r
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-20.\r
+\r
+**/\r
+\r
+#ifndef __PENTIUM_MSR_H__\r
+#define __PENTIUM_MSR_H__\r
+\r
+#include <Register/ArchitecturalMsr.h>\r
+\r
+/**\r
+  See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".\r
+\r
+  @param  ECX  MSR_PENTIUM_P5_MC_ADDR (0x00000000)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);\r
+  AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_PENTIUM_P5_MC_ADDR                   0x00000000\r
+\r
+\r
+/**\r
+  See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".\r
+\r
+  @param  ECX  MSR_PENTIUM_P5_MC_TYPE (0x00000001)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);\r
+  AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_PENTIUM_P5_MC_TYPE                   0x00000001\r
+\r
+\r
+/**\r
+  See Section 17.14, "Time-Stamp Counter.".\r
+\r
+  @param  ECX  MSR_PENTIUM_TSC (0x00000010)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);\r
+  AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_PENTIUM_TSC                          0x00000010\r
+\r
+\r
+/**\r
+  See Section 18.20.1, "Control and Event Select Register (CESR).".\r
+\r
+  @param  ECX  MSR_PENTIUM_CESR (0x00000011)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);\r
+  AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_PENTIUM_CESR                         0x00000011\r
+\r
+\r
+/**\r
+  Section 18.20.3, "Events Counted.".\r
+\r
+  @param  ECX  MSR_PENTIUM_CTRn\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);\r
+  AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);\r
+  @endcode\r
+  @{\r
+**/\r
+#define MSR_PENTIUM_CTR0                         0x00000012\r
+#define MSR_PENTIUM_CTR1                         0x00000013\r
+/// @}\r
+\r
+#endif\r