1. refine the comments

2. use BITx

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6695 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdePkg/Include/IndustryStandard/Acpi10.h b/MdePkg/Include/IndustryStandard/Acpi10.h
index 159a01cc4110823d0eefd3f9643bc1276457976d..7afb678a9917c8a33b1af96718da49443b0d4d76 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Acpi10.h
+++ b/MdePkg/Include/IndustryStandard/Acpi10.h
@@ -23,11 +23,10 @@ typedef struct {
   UINT32  Length;\r
 } EFI_ACPI_COMMON_HEADER;\r
 \r
-//\r
-// Common ACPI description table header.  This structure prefaces most ACPI tables.\r
-//\r
 #pragma pack(1)\r
-\r
+///\r
+/// Common ACPI description table header.  This structure prefaces most ACPI tables.\r
+///\r
 typedef struct {\r
   UINT32  Signature;\r
   UINT32  Length;\r
@@ -39,8 +38,8 @@ typedef struct {
   UINT32  CreatorId;\r
   UINT32  CreatorRevision;\r
 } EFI_ACPI_DESCRIPTION_HEADER;\r
-\r
 #pragma pack()\r
+\r
 //\r
 // Define for Desriptor\r
 //\r
@@ -63,10 +62,11 @@ typedef struct {
 // Ensure proper structure formats\r
 //\r
 #pragma pack(1)\r
-//\r
-// The commond definition of QWORD, DWORD, and WORD\r
-// Address Space Descriptors\r
-//\r
+\r
+///\r
+/// The commond definition of QWORD, DWORD, and WORD\r
+/// Address Space Descriptors\r
+///\r
 typedef struct {\r
   UINT8   Desc;\r
   UINT16  Len;\r
@@ -208,16 +208,16 @@ typedef struct {
 // Fixed ACPI Description Table Fixed Feature Flags\r
 // All other bits are reserved and must be set to 0.\r
 //\r
-#define EFI_ACPI_1_0_WBINVD       (1 << 0)\r
-#define EFI_ACPI_1_0_WBINVD_FLUSH (1 << 1)\r
-#define EFI_ACPI_1_0_PROC_C1      (1 << 2)\r
-#define EFI_ACPI_1_0_P_LVL2_UP    (1 << 3)\r
-#define EFI_ACPI_1_0_PWR_BUTTON   (1 << 4)\r
-#define EFI_ACPI_1_0_SLP_BUTTON   (1 << 5)\r
-#define EFI_ACPI_1_0_FIX_RTC      (1 << 6)\r
-#define EFI_ACPI_1_0_RTC_S4       (1 << 7)\r
-#define EFI_ACPI_1_0_TMR_VAL_EXT  (1 << 8)\r
-#define EFI_ACPI_1_0_DCK_CAP      (1 << 9)\r
+#define EFI_ACPI_1_0_WBINVD               BIT0\r
+#define EFI_ACPI_1_0_WBINVD_FLUSH         BIT1\r
+#define EFI_ACPI_1_0_PROC_C1              BIT2\r
+#define EFI_ACPI_1_0_P_LVL2_UP            BIT3\r
+#define EFI_ACPI_1_0_PWR_BUTTON           BIT4\r
+#define EFI_ACPI_1_0_SLP_BUTTON           BIT5\r
+#define EFI_ACPI_1_0_FIX_RTC              BIT6\r
+#define EFI_ACPI_1_0_RTC_S4               BIT7\r
+#define EFI_ACPI_1_0_TMR_VAL_EXT          BIT8\r
+#define EFI_ACPI_1_0_DCK_CAP              BIT9\r
 \r
 ///\r
 /// Firmware ACPI Control Structure\r
@@ -236,7 +236,7 @@ typedef struct {
 /// Firmware Control Structure Feature Flags\r
 /// All other bits are reserved and must be set to 0.\r
 ///\r
-#define EFI_ACPI_1_0_S4BIOS_F (1 << 0)\r
+#define EFI_ACPI_1_0_S4BIOS_F             BIT0\r
 \r
 ///\r
 /// Multiple APIC Description Table header definition.  The rest of the table\r
@@ -257,7 +257,7 @@ typedef struct {
 /// Multiple APIC Flags\r
 /// All other bits are reserved and must be set to 0.\r
 ///\r
-#define EFI_ACPI_1_0_PCAT_COMPAT  (1 << 0)\r
+#define EFI_ACPI_1_0_PCAT_COMPAT           BIT0\r
 \r
 //\r
 // Multiple APIC Description Table APIC structure types\r
@@ -288,7 +288,7 @@ typedef struct {
 ///\r
 /// Local APIC Flags.  All other bits are reserved and must be 0.\r
 ///\r
-#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED      BIT0\r
 \r
 ///\r
 /// IO APIC Structure\r

diff --git a/MdePkg/Include/IndustryStandard/Acpi20.h b/MdePkg/Include/IndustryStandard/Acpi20.h
index 8ac8076f7d34d1586315c1f4442f4296c2e19426..bf529e499d7a1bb87414a9658627932045cb449d 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Acpi20.h
+++ b/MdePkg/Include/IndustryStandard/Acpi20.h
@@ -160,31 +160,31 @@ typedef struct {
 ///\r
 #define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION  0x03\r
 \r
-///\r
-/// Fixed ACPI Description Table Boot Architecture Flags\r
-/// All other bits are reserved and must be set to 0.\r
-///\r
-#define EFI_ACPI_2_0_LEGACY_DEVICES (1 << 0)\r
-#define EFI_ACPI_2_0_8042           (1 << 1)\r
+//\r
+// Fixed ACPI Description Table Boot Architecture Flags\r
+// All other bits are reserved and must be set to 0.\r
+//\r
+#define EFI_ACPI_2_0_LEGACY_DEVICES          BIT0\r
+#define EFI_ACPI_2_0_8042                    BIT1\r
 \r
 //\r
 // Fixed ACPI Description Table Fixed Feature Flags\r
 // All other bits are reserved and must be set to 0.\r
 //\r
-#define EFI_ACPI_2_0_WBINVD         (1 << 0)\r
-#define EFI_ACPI_2_0_WBINVD_FLUSH   (1 << 1)\r
-#define EFI_ACPI_2_0_PROC_C1        (1 << 2)\r
-#define EFI_ACPI_2_0_P_LVL2_UP      (1 << 3)\r
-#define EFI_ACPI_2_0_PWR_BUTTON     (1 << 4)\r
-#define EFI_ACPI_2_0_SLP_BUTTON     (1 << 5)\r
-#define EFI_ACPI_2_0_FIX_RTC        (1 << 6)\r
-#define EFI_ACPI_2_0_RTC_S4         (1 << 7)\r
-#define EFI_ACPI_2_0_TMR_VAL_EXT    (1 << 8)\r
-#define EFI_ACPI_2_0_DCK_CAP        (1 << 9)\r
-#define EFI_ACPI_2_0_RESET_REG_SUP  (1 << 10)\r
-#define EFI_ACPI_2_0_SEALED_CASE    (1 << 11)\r
-#define EFI_ACPI_2_0_HEADLESS       (1 << 12)\r
-#define EFI_ACPI_2_0_CPU_SW_SLP     (1 << 13)\r
+#define EFI_ACPI_2_0_WBINVD                  BIT0\r
+#define EFI_ACPI_2_0_WBINVD_FLUSH            BIT1\r
+#define EFI_ACPI_2_0_PROC_C1                 BIT2\r
+#define EFI_ACPI_2_0_P_LVL2_UP               BIT3\r
+#define EFI_ACPI_2_0_PWR_BUTTON              BIT4\r
+#define EFI_ACPI_2_0_SLP_BUTTON              BIT5\r
+#define EFI_ACPI_2_0_FIX_RTC                 BIT6\r
+#define EFI_ACPI_2_0_RTC_S4                  BIT7\r
+#define EFI_ACPI_2_0_TMR_VAL_EXT             BIT8\r
+#define EFI_ACPI_2_0_DCK_CAP                 BIT9\r
+#define EFI_ACPI_2_0_RESET_REG_SUP           BIT10\r
+#define EFI_ACPI_2_0_SEALED_CASE             BIT11\r
+#define EFI_ACPI_2_0_HEADLESS                BIT12\r
+#define EFI_ACPI_2_0_CPU_SW_SLP              BIT13\r
 \r
 ///\r
 /// Firmware ACPI Control Structure\r
@@ -210,7 +210,7 @@ typedef struct {
 /// Firmware Control Structure Feature Flags\r
 /// All other bits are reserved and must be set to 0.\r
 ///\r
-#define EFI_ACPI_2_0_S4BIOS_F (1 << 0)\r
+#define EFI_ACPI_2_0_S4BIOS_F        BIT0\r
 \r
 ///\r
 /// Multiple APIC Description Table header definition.  The rest of the table\r
@@ -231,7 +231,7 @@ typedef struct {
 /// Multiple APIC Flags\r
 /// All other bits are reserved and must be set to 0.\r
 ///\r
-#define EFI_ACPI_2_0_PCAT_COMPAT  (1 << 0)\r
+#define EFI_ACPI_2_0_PCAT_COMPAT          BIT0\r
 \r
 //\r
 // Multiple APIC Description Table APIC structure types\r
@@ -266,7 +266,7 @@ typedef struct {
 ///\r
 /// Local APIC Flags.  All other bits are reserved and must be 0.\r
 ///\r
-#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED         BIT0\r
 \r
 ///\r
 /// IO APIC Structure\r

diff --git a/MdePkg/Include/IndustryStandard/Acpi30.h b/MdePkg/Include/IndustryStandard/Acpi30.h
index 75b5f8eba88d42405d44756f9f3c60fa5fcb7cc4..69a5e70ca900e73578e3a15c3134650538dc881b 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Acpi30.h
+++ b/MdePkg/Include/IndustryStandard/Acpi30.h
@@ -185,36 +185,36 @@ typedef struct {
 // Fixed ACPI Description Table Boot Architecture Flags\r
 // All other bits are reserved and must be set to 0.\r
 //\r
-#define EFI_ACPI_3_0_LEGACY_DEVICES     (1 << 0)\r
-#define EFI_ACPI_3_0_8042               (1 << 1)\r
-#define EFI_ACPI_3_0_VGA_NOT_PRESENT    (1 << 2)\r
-#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED  (1 << 3)\r
-#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS (1 << 4)\r
+#define EFI_ACPI_3_0_LEGACY_DEVICES              BIT0\r
+#define EFI_ACPI_3_0_8042                        BIT1\r
+#define EFI_ACPI_3_0_VGA_NOT_PRESENT             BIT2\r
+#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED           BIT3\r
+#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS          BIT4\r
 \r
 //\r
 // Fixed ACPI Description Table Fixed Feature Flags\r
 // All other bits are reserved and must be set to 0.\r
 //\r
-#define EFI_ACPI_3_0_WBINVD                   (1 << 0)\r
-#define EFI_ACPI_3_0_WBINVD_FLUSH             (1 << 1)\r
-#define EFI_ACPI_3_0_PROC_C1                  (1 << 2)\r
-#define EFI_ACPI_3_0_P_LVL2_UP                (1 << 3)\r
-#define EFI_ACPI_3_0_PWR_BUTTON               (1 << 4)\r
-#define EFI_ACPI_3_0_SLP_BUTTON               (1 << 5)\r
-#define EFI_ACPI_3_0_FIX_RTC                  (1 << 6)\r
-#define EFI_ACPI_3_0_RTC_S4                   (1 << 7)\r
-#define EFI_ACPI_3_0_TMR_VAL_EXT              (1 << 8)\r
-#define EFI_ACPI_3_0_DCK_CAP                  (1 << 9)\r
-#define EFI_ACPI_3_0_RESET_REG_SUP            (1 << 10)\r
-#define EFI_ACPI_3_0_SEALED_CASE              (1 << 11)\r
-#define EFI_ACPI_3_0_HEADLESS                 (1 << 12)\r
-#define EFI_ACPI_3_0_CPU_SW_SLP               (1 << 13)\r
-#define EFI_ACPI_3_0_PCI_EXP_WAK              (1 << 14)\r
-#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK       (1 << 15)\r
-#define EFI_ACPI_3_0_S4_RTC_STS_VALID         (1 << 16)\r
-#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE  (1 << 17)\r
-#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL (1 << 18)\r
-#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE (1 << 19)\r
+#define EFI_ACPI_3_0_WBINVD                                 BIT0\r
+#define EFI_ACPI_3_0_WBINVD_FLUSH                           BIT1\r
+#define EFI_ACPI_3_0_PROC_C1                                BIT2\r
+#define EFI_ACPI_3_0_P_LVL2_UP                              BIT3\r
+#define EFI_ACPI_3_0_PWR_BUTTON                             BIT4\r
+#define EFI_ACPI_3_0_SLP_BUTTON                             BIT5\r
+#define EFI_ACPI_3_0_FIX_RTC                                BIT6\r
+#define EFI_ACPI_3_0_RTC_S4                                 BIT7\r
+#define EFI_ACPI_3_0_TMR_VAL_EXT                            BIT8\r
+#define EFI_ACPI_3_0_DCK_CAP                                BIT9\r
+#define EFI_ACPI_3_0_RESET_REG_SUP                          BIT10\r
+#define EFI_ACPI_3_0_SEALED_CASE                            BIT11\r
+#define EFI_ACPI_3_0_HEADLESS                               BIT12\r
+#define EFI_ACPI_3_0_CPU_SW_SLP                             BIT13\r
+#define EFI_ACPI_3_0_PCI_EXP_WAK                            BIT14\r
+#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK                     BIT15\r
+#define EFI_ACPI_3_0_S4_RTC_STS_VALID                       BIT16\r
+#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE                BIT17\r
+#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL               BIT18\r
+#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE   BIT19\r
 \r
 ///\r
 /// Firmware ACPI Control Structure\r
@@ -240,7 +240,7 @@ typedef struct {
 /// Firmware Control Structure Feature Flags\r
 /// All other bits are reserved and must be set to 0.\r
 ///\r
-#define EFI_ACPI_3_0_S4BIOS_F (1 << 0)\r
+#define EFI_ACPI_3_0_S4BIOS_F       BIT0\r
 \r
 //\r
 // Differentiated System Description Table,\r
@@ -271,7 +271,7 @@ typedef struct {
 /// Multiple APIC Flags\r
 /// All other bits are reserved and must be set to 0.\r
 ///\r
-#define EFI_ACPI_3_0_PCAT_COMPAT  (1 << 0)\r
+#define EFI_ACPI_3_0_PCAT_COMPAT         BIT0\r
 \r
 //\r
 // Multiple APIC Description Table APIC structure types\r
@@ -306,7 +306,7 @@ typedef struct {
 ///\r
 /// Local APIC Flags.  All other bits are reserved and must be 0.\r
 ///\r
-#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED        BIT0\r
 \r
 ///\r
 /// IO APIC Structure\r
@@ -433,7 +433,7 @@ typedef struct {
 /// Platform Interrupt Source Flags.\r
 /// All other bits are reserved and must be set to 0.\r
 ///\r
-#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE     (1 << 0)\r
+#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE          BIT0\r
 \r
 ///\r
 /// Smart Battery Description Table (SBST)\r
@@ -474,7 +474,7 @@ typedef struct {
 ///\r
 typedef struct {\r
   EFI_ACPI_DESCRIPTION_HEADER Header;\r
-  UINT32                      Reserved1;  // Must be set to 1\r
+  UINT32                      Reserved1;  ///< Must be set to 1\r
   UINT64                      Reserved2;\r
 } EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\r
 \r
@@ -483,11 +483,11 @@ typedef struct {
 ///\r
 #define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION  0x02\r
 \r
-///\r
-/// SRAT structure types.\r
-/// All other values between 0x02 an 0xFF are reserved and\r
-/// will be ignored by OSPM.\r
-///\r
+//\r
+// SRAT structure types.\r
+// All other values between 0x02 an 0xFF are reserved and\r
+// will be ignored by OSPM.\r
+//\r
 #define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY  0x00\r
 #define EFI_ACPI_3_0_MEMORY_AFFINITY                      0x01\r
 \r

diff --git a/MdePkg/Include/IndustryStandard/Atapi.h b/MdePkg/Include/IndustryStandard/Atapi.h
index 0f34d8dfc4760e02b65d55e076c4ab2c0501443c..4fadf10eeeff095f530ab1807e07095f30bf4026 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Atapi.h
+++ b/MdePkg/Include/IndustryStandard/Atapi.h
@@ -141,9 +141,9 @@ typedef struct {
   UINT8 additional_sense_bytes_18_253[253 - 18 + 1];\r
 } ATAPI_REQUEST_SENSE_DATA;\r
 \r
-///\r
-/// The followings are defined in SFF-8070i(ATAPI Removable Rewritable Specification)\r
-///\r
+//\r
+// The followings are defined in SFF-8070i(ATAPI Removable Rewritable Specification)\r
+//\r
 \r
 ///\r
 /// READ CAPACITY Data \r
@@ -342,7 +342,6 @@ typedef union {
 #define ATA_CMD_READ_LONG_WITH_RETRY    0x23   ///< defined in ATA-5\r
 #define ATA_CMD_READ_SECTORS_EXT        0x24   ///< defined in ATA-6\r
 \r
-\r
 //\r
 // Class 2: PIO Data-Out Commands\r
 //\r
@@ -382,28 +381,25 @@ typedef union {
 #define ATA_CMD_STANDBY_ALIAS           0xe2  ///< defined in ATA-6\r
 #define ATA_CMD_STANDBY_IMMEDIATE       0x94  ///< defined in ATA-3\r
 #define ATA_CMD_STANDBY_IMMEDIATE_ALIAS 0xe0  ///< defined in ATA-6\r
-///\r
-/// S.M.A.R.T\r
-///\r
+//\r
+// S.M.A.R.T\r
+//\r
 #define ATA_CMD_SMART               0xb0\r
 #define ATA_CONSTANT_C2             0xc2\r
 #define ATA_CONSTANT_4F             0x4f\r
 #define ATA_SMART_ENABLE_OPERATION  0xd8\r
 #define ATA_SMART_RETURN_STATUS     0xda\r
 \r
-\r
-///\r
-/// Class 4: DMA Command\r
-///\r
+//\r
+// Class 4: DMA Command\r
+//\r
 #define ATA_CMD_READ_DMA              0xc8   ///< defined in ATA-6\r
 #define ATA_CMD_READ_DMA_WITH_RETRY   0xc9   ///< defined in ATA-4\r
 #define ATA_CMD_READ_DMA_EXT          0x25   ///< defined in ATA-6\r
 #define ATA_CMD_WRITE_DMA             0xca   ///< defined in ATA-6\r
 #define ATA_CMD_WRITE_DMA_WITH_RETRY  0xcb   ///< defined in ATA-4\r
 #define ATA_CMD_WRITE_DMA_EXT         0x35   ///< defined in ATA-6\r
-\r
-\r
-\r
+        \r
 ///\r
 /// default content of device control register, disable INT,\r
 /// Bit3 is set to 1 according ATA-1\r
@@ -419,12 +415,12 @@ typedef union {
 \r
 #define ATA_REQUEST_SENSE_ERROR (0x70) ///< defined in SFF-8070i\r
 \r
-///\r
-/// Sense Key, Additional Sense Codes and Additional Sense Code Qualifier\r
-/// defined in MultiMedia Commands (MMC, MMC-2) \r
-///\r
-/// Sense Key \r
-///\r
+//\r
+// Sense Key, Additional Sense Codes and Additional Sense Code Qualifier\r
+// defined in MultiMedia Commands (MMC, MMC-2) \r
+//\r
+// Sense Key \r
+//\r
 #define ATA_SK_NO_SENSE         (0x0)\r
 #define ATA_SK_RECOVERY_ERROR   (0x1)\r
 #define ATA_SK_NOT_READY        (0x2)\r
@@ -442,9 +438,9 @@ typedef union {
 #define ATA_SK_MISCOMPARE       (0xE)\r
 #define ATA_SK_RESERVED_F       (0xF)\r
 \r
-///\r
-/// Additional Sense Codes\r
-///\r
+//\r
+// Additional Sense Codes\r
+//\r
 #define ATA_ASC_NOT_READY                   (0x04)\r
 #define ATA_ASC_MEDIA_ERR1                  (0x10)\r
 #define ATA_ASC_MEDIA_ERR2                  (0x11)\r
@@ -466,9 +462,9 @@ typedef union {
 //\r
 #define ATA_ASCQ_IN_PROGRESS  (0x01)\r
 \r
-///\r
-/// Error Register\r
-///\r
+//\r
+// Error Register\r
+//\r
 #define ATA_ERRREG_BBK   BIT7  ///< Bad block detected      defined in ATA-1\r
 #define ATA_ERRREG_UNC   BIT6  ///< Uncorrectable Data      defined in ATA-3\r
 #define ATA_ERRREG_MC    BIT5  ///< Media Change            defined in ATA-3\r
@@ -478,9 +474,9 @@ typedef union {
 #define ATA_ERRREG_TK0NF BIT1  ///< Track 0 Not Found       defined in ATA-3\r
 #define ATA_ERRREG_AMNF  BIT0  ///< Address Mark Not Found  defined in ATA-3\r
 \r
-///\r
-/// Status Register\r
-///\r
+//\r
+// Status Register\r
+//\r
 #define ATA_STSREG_BSY   BIT7  ///< Controller Busy         defined in ATA-6\r
 #define ATA_STSREG_DRDY  BIT6  ///< Drive Ready             defined in ATA-6\r
 #define ATA_STSREG_DWF   BIT5  ///< Drive Write Fault       defined in ATA-6\r
@@ -490,9 +486,9 @@ typedef union {
 #define ATA_STSREG_IDX   BIT1  ///< Index                   defined in ATA-3\r
 #define ATA_STSREG_ERR   BIT0  ///< Error                   defined in ATA-6\r
 \r
-///\r
-/// Device Control Register\r
-///\r
+//\r
+// Device Control Register\r
+//\r
 #define ATA_CTLREG_SRST  BIT2  ///< Software Reset\r
 #define ATA_CTLREG_IEN_L BIT1  ///< Interrupt Enable #\r
 \r

diff --git a/MdePkg/Include/IndustryStandard/ElTorito.h b/MdePkg/Include/IndustryStandard/ElTorito.h
index 12375015ef1ec0ce549d1c6a557ce345409fb3b0..a8deb461d0ae9e64bab2c89cba6bdd7574861fff 100644 (file)
--- a/MdePkg/Include/IndustryStandard/ElTorito.h
+++ b/MdePkg/Include/IndustryStandard/ElTorito.h
@@ -19,9 +19,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #ifndef _ELTORITO_H_\r
 #define _ELTORITO_H_\r
 \r
-///\r
-/// CDROM_VOLUME_DESCRIPTOR.Types, defined in ISO 9660\r
-///\r
+//\r
+// CDROM_VOLUME_DESCRIPTOR.Types, defined in ISO 9660\r
+//\r
 #define CDVOL_TYPE_STANDARD 0x0\r
 #define CDVOL_TYPE_CODED    0x1\r
 #define CDVOL_TYPE_END      0xFF\r

diff --git a/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h b/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h
index 7fc7ac63776d54e5929b38fd317bad8bdcff40df..a156b53e1a7f9d0825fdaf50f09450fd698afa04 100644 (file)
--- a/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h
+++ b/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h
@@ -1,6 +1,6 @@
 /** @file\r
-  The definition for iSCSI Boot Firmware Table, it's defined in\r
-  Microsoft iBFT document. \r
+  The definition for iSCSI Boot Firmware Table, it's defined in Microsoft's\r
+  iSCSI Boot Firmware Table(iBFT) as Defined in ACPI 3.0b Specification. \r
   \r
   Copyright (c) 2006 - 2008, Intel Corporation\r
   All rights reserved. This program and the accompanying materials                          \r
@@ -85,8 +85,9 @@ typedef struct {
   UINT16                                               Target1Offset;  \r
 } EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE;\r
 \r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_VERSION            0x1\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_FLAG_BOOT_FAILOVER 0x1\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_VERSION              0x1\r
+\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_FLAG_BOOT_FAILOVER   BIT0\r
 \r
 ///\r
 /// Initiator Structure\r
@@ -101,9 +102,10 @@ typedef struct {
   UINT16                                               IScsiNameOffset;\r
 } EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE;\r
 \r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_VERSION            0x1\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID   0x1 \r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED 0x2 \r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_VERSION             0x1\r
+\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID    BIT0 \r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED  BIT1 \r
 \r
 ///\r
 /// NIC Structure\r
@@ -124,10 +126,11 @@ typedef struct {
   UINT16                                               HostNameOffset;\r
 } EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE;\r
 \r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_VERSION            0x1\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BLOCK_VALID   0x1\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BOOT_SELECTED 0x2\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_GLOBAL        0x4\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_VERSION                 0x1\r
+\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BLOCK_VALID        BIT0\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BOOT_SELECTED      BIT1\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_GLOBAL             BIT2\r
 \r
 ///\r
 /// Target Structure\r
@@ -151,11 +154,12 @@ typedef struct {
   UINT16                                               ReverseCHAPSecretOffset;\r
 } EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE;\r
 \r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_VERSION            0x1\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BLOCK_VALID   0x1\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BOOT_SELECTED 0x2\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_CHAP   0x4\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_RCHAP  0x8\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_VERSION               0x1\r
+\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BLOCK_VALID      BIT0\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BOOT_SELECTED    BIT1\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_CHAP      BIT2\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_RCHAP     BIT3\r
 \r
 #pragma pack()\r
 \r

diff --git a/MdePkg/Include/IndustryStandard/Pci22.h b/MdePkg/Include/IndustryStandard/Pci22.h
index d88b28f82557b696c92858d6a47dfb93aefaf57c..9ac34aae8229cc37266f35dfd11a46faca500352 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Pci22.h
+++ b/MdePkg/Include/IndustryStandard/Pci22.h
@@ -123,9 +123,9 @@ typedef struct {
   UINT16  BridgeControl;        ///< Bridge Control\r
 } PCI_CARDBUS_CONTROL_REGISTER;\r
 \r
-///\r
-/// Definitions of PCI class bytes and manipulation macros.\r
-///\r
+//\r
+// Definitions of PCI class bytes and manipulation macros.\r
+//\r
 #define PCI_CLASS_OLD                 0x00\r
 #define   PCI_CLASS_OLD_OTHER           0x00\r
 #define   PCI_CLASS_OLD_VGA             0x01\r
@@ -350,9 +350,9 @@ typedef struct {
 #define PCI_MAXGNT_OFFSET                           0x3E ///< Max Grant Register\r
 #define PCI_MAXLAT_OFFSET                           0x3F ///< Max Latency Register\r
 \r
-///\r
-/// defined in PCI-to-PCI Bridge Architecture Specification\r
-///\r
+//\r
+// defined in PCI-to-PCI Bridge Architecture Specification\r
+//\r
 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18   \r
 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19   \r
 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a   \r
@@ -389,9 +389,9 @@ typedef union {
 #define EFI_PCI_COMMAND_SERR                            BIT8   ///< 0x0100\r
 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK               BIT9   ///< 0x0200\r
 \r
-///\r
-/// defined in PCI-to-PCI Bridge Architecture Specification\r
-///\r
+//\r
+// defined in PCI-to-PCI Bridge Architecture Specification\r
+//\r
 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE    BIT0   ///< 0x0001\r
 #define EFI_PCI_BRIDGE_CONTROL_SERR                     BIT1   ///< 0x0002\r
 #define EFI_PCI_BRIDGE_CONTROL_ISA                      BIT2   ///< 0x0004\r
@@ -405,9 +405,9 @@ typedef union {
 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS             BIT10  ///< 0x0400\r
 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR       BIT11  ///< 0x0800\r
 \r
-///\r
-/// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r
-///\r
+//\r
+// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r
+//\r
 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE           BIT7   ///< 0x0080\r
 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE       BIT8   ///< 0x0100\r
 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE       BIT9   ///< 0x0200\r
@@ -436,6 +436,7 @@ typedef union {
 #define EFI_PCI_CAPABILITY_ID_SLOTID  0x04\r
 #define EFI_PCI_CAPABILITY_ID_MSI     0x05\r
 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
+\r
 typedef struct {\r
   UINT8 CapabilityID;\r
   UINT8 NextItemPtr;\r
@@ -543,7 +544,7 @@ typedef struct {
 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE              0xaa55\r
 #define PCI_DATA_STRUCTURE_SIGNATURE                    SIGNATURE_32 ('P', 'C', 'I', 'R')\r
 #define PCI_CODE_TYPE_PCAT_IMAGE                        0x00\r
-#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED         0x0001  ///<defined in UEFI spec.\r
+#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED         0x0001  ///< defined in UEFI spec.\r
 \r
 typedef struct {\r
   UINT16  Signature;    ///< 0xaa55\r

diff --git a/MdePkg/Include/IndustryStandard/Pci23.h b/MdePkg/Include/IndustryStandard/Pci23.h
index e1289f75c610127546ead10bf64e07197afd55d6..b100dce1a086022bd6159aa8d0b973ee25df393b 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Pci23.h
+++ b/MdePkg/Include/IndustryStandard/Pci23.h
@@ -27,9 +27,9 @@
 ///\r
 #define PCI_EXP_MAX_CONFIG_OFFSET     0x1000\r
 \r
-//\r
-// PCI Capability List IDs and records\r
-//\r
+///\r
+/// PCI Capability List IDs and records\r
+///\r
 #define EFI_PCI_CAPABILITY_ID_PCIX    0x07\r
 \r
 #pragma pack(1)\r