--- /dev/null
+#\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+\r
+#include <AsmMacroIoLibV8.h>\r
+#include <Base.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+\r
+.text\r
+.align 2\r
+\r
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
+GCC_ASM_EXPORT(ArmGetPhysAddrTop)\r
+\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdCoreCount)\r
+\r
+ASM_PFX(ArmPlatformPeiBootAction):\r
+ ret\r
+\r
+//UINTN\r
+//ArmPlatformGetPrimaryCoreMpId (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x0)\r
+ ldrh w0, [x0]\r
+ ret\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ASM_PFX(ArmPlatformIsPrimaryCore):\r
+ mov x0, #1\r
+ ret\r
+\r
+//UINTN\r
+//ArmPlatformGetCorePosition (\r
+// IN UINTN MpId\r
+// );\r
+// With this function: CorePos = (ClusterId * 4) + CoreId\r
+ASM_PFX(ArmPlatformGetCorePosition):\r
+ and x1, x0, #ARM_CORE_MASK\r
+ and x0, x0, #ARM_CLUSTER_MASK\r
+ add x0, x1, x0, LSR #6\r
+ ret\r
+\r
+//EFI_PHYSICAL_ADDRESS\r
+//GetPhysAddrTop (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmGetPhysAddrTop):\r
+ mrs x0, id_aa64mmfr0_el1\r
+ adr x1, .LPARanges\r
+ and x0, x0, #7\r
+ ldrb w1, [x1, x0]\r
+ mov x0, #1\r
+ lsl x0, x0, x1\r
+ ret\r
+\r
+//\r
+// Bits 0..2 of the AA64MFR0_EL1 system register encode the size of the\r
+// physical address space support on this CPU:\r
+// 0 == 32 bits, 1 == 36 bits, etc etc\r
+// 6 and 7 are reserved\r
+//\r
+.LPARanges:\r
+ .byte 32, 36, 40, 42, 44, 48, -1, -1\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
--- /dev/null
+#\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+\r
+.text\r
+.align 2\r
+\r
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
+GCC_ASM_EXPORT(ArmGetPhysAddrTop)\r
+\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdCoreCount)\r
+\r
+ASM_PFX(ArmPlatformPeiBootAction):\r
+ bx lr\r
+\r
+//UINTN\r
+//ArmPlatformGetPrimaryCoreMpId (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
+ ldr r0, [r0]\r
+ bx lr\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ASM_PFX(ArmPlatformIsPrimaryCore):\r
+ mov r0, #1\r
+ bx lr\r
+\r
+//UINTN\r
+//ArmPlatformGetCorePosition (\r
+// IN UINTN MpId\r
+// );\r
+// With this function: CorePos = (ClusterId * 4) + CoreId\r
+ASM_PFX(ArmPlatformGetCorePosition):\r
+ and r1, r0, #ARM_CORE_MASK\r
+ and r0, r0, #ARM_CLUSTER_MASK\r
+ add r0, r1, r0, LSR #6\r
+ bx lr\r
+\r
+//EFI_PHYSICAL_ADDRESS\r
+//GetPhysAddrTop (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmGetPhysAddrTop):\r
+ mov r0, #0x00000000\r
+ mov r1, #0x10000\r
+ bx lr\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
--- /dev/null
+#\r
+# Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+ EXPORT ArmPlatformPeiBootAction\r
+ EXPORT ArmPlatformIsPrimaryCore\r
+ EXPORT ArmPlatformGetPrimaryCoreMpId\r
+ EXPORT ArmPlatformGetCorePosition\r
+ EXPORT ArmGetPhysAddrTop\r
+\r
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore\r
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask\r
+ IMPORT _gPcd_FixedAtBuild_PcdCoreCount\r
+\r
+ArmPlatformPeiBootAction FUNCTION\r
+ bx lr\r
+ ENDFUNC\r
+\r
+//UINTN\r
+//ArmPlatformGetPrimaryCoreMpId (\r
+// VOID\r
+// );\r
+ArmPlatformGetPrimaryCoreMpId FUNCTION\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
+ ldr r0, [r0]\r
+ bx lr\r
+ ENDFUNC\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ArmPlatformIsPrimaryCore FUNCTION\r
+ mov r0, #1\r
+ bx lr\r
+ ENDFUNC\r
+\r
+//UINTN\r
+//ArmPlatformGetCorePosition (\r
+// IN UINTN MpId\r
+// );\r
+// With this function: CorePos = (ClusterId * 4) + CoreId\r
+ArmPlatformGetCorePosition FUNCTION\r
+ and r1, r0, #ARM_CORE_MASK\r
+ and r0, r0, #ARM_CLUSTER_MASK\r
+ add r0, r1, r0, LSR #6\r
+ bx lr\r
+ ENDFUNC\r
+\r
+//EFI_PHYSICAL_ADDRESS\r
+//GetPhysAddrTop (\r
+// VOID\r
+// );\r
+ArmGetPhysAddrTop FUNCTION\r
+ mov r0, #0x00000000\r
+ mov r1, #0x10000\r
+ bx lr\r
+ ENDFUNC\r
+\r
+ END\r
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmVirtualizationPlatformLib\r
+ FILE_GUID = 00214cc1-06d1-45fe-9700-dca5726ad7bf\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ArmPlatformLib|SEC PEIM\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationPkg.dec\r
+\r
+[LibraryClasses]\r
+ IoLib\r
+ ArmLib\r
+ PrintLib\r
+ FdtLib\r
+ SerialPortLib\r
+ HobLib\r
+\r
+[Sources.common]\r
+ Virt.c\r
+ VirtMem.c\r
+\r
+[Sources.AARCH64]\r
+ AARCH64/VirtHelper.S | GCC\r
+\r
+[Sources.ARM]\r
+ ARM/VirtHelper.S | GCC\r
+ ARM/VirtHelper.asm | RVCT\r
+\r
+[FeaturePcd]\r
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec\r
+\r
+[Pcd]\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize\r
+\r
+[FixedPcd]\r
+ gArmVirtualizationTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress\r
+ gArmPlatformTokenSpaceGuid.PcdCoreCount\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore\r
+ gArmTokenSpaceGuid.PcdFdBaseAddress\r
+ gArmTokenSpaceGuid.PcdFdSize\r
+\r
+[Guids]\r
+ gEarlyPL011BaseAddressGuid\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+* Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+* Copyright (c) 2014, Red Hat, Inc.\r
+*\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <ArmPlatform.h>\r
+#include <libfdt.h>\r
+#include <Pi/PiBootMode.h>\r
+#include <Uefi/UefiBaseType.h>\r
+#include <Uefi/UefiMultiPhase.h>\r
+#include <Pi/PiHob.h>\r
+#include <Library/HobLib.h>\r
+#include <Guid/EarlyPL011BaseAddress.h>\r
+\r
+/**\r
+ Return the current Boot Mode\r
+\r
+ This function returns the boot reason on the platform\r
+\r
+ @return Return the current Boot Mode of the platform\r
+\r
+**/\r
+EFI_BOOT_MODE\r
+ArmPlatformGetBootMode (\r
+ VOID\r
+ )\r
+{\r
+ return BOOT_WITH_FULL_CONFIGURATION;\r
+}\r
+\r
+/**\r
+ This function is called by PrePeiCore, in the SEC phase.\r
+**/\r
+RETURN_STATUS\r
+ArmPlatformInitialize (\r
+ IN UINTN MpId\r
+ )\r
+{\r
+ //\r
+ // We are relying on ArmPlatformInitializeSystemMemory () being called from\r
+ // InitializeMemory (), which only occurs if the following feature is disabled\r
+ //\r
+ ASSERT (!FeaturePcdGet (PcdSystemMemoryInitializeInSec));\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Initialize the system (or sometimes called permanent) memory\r
+\r
+ This memory is generally represented by the DRAM.\r
+\r
+ This function is called from InitializeMemory() in MemoryInitPeim, in the PEI\r
+ phase.\r
+**/\r
+VOID\r
+ArmPlatformInitializeSystemMemory (\r
+ VOID\r
+ )\r
+{\r
+ VOID *DeviceTreeBase;\r
+ INT32 Node, Prev;\r
+ UINT64 NewBase;\r
+ UINT64 NewSize;\r
+ BOOLEAN HaveMemory, HaveUART;\r
+ UINT64 *HobData;\r
+ CONST CHAR8 *Type;\r
+ CONST CHAR8 *Compatible;\r
+ CONST CHAR8 *CompItem;\r
+ INT32 Len;\r
+ CONST UINT64 *RegProp;\r
+ UINT64 UartBase;\r
+\r
+ NewBase = 0;\r
+ NewSize = 0;\r
+\r
+ HaveMemory = FALSE;\r
+ HaveUART = FALSE;\r
+\r
+ HobData = BuildGuidHob (&gEarlyPL011BaseAddressGuid, sizeof *HobData);\r
+ ASSERT (HobData != NULL);\r
+ *HobData = 0;\r
+\r
+ DeviceTreeBase = (VOID *)(UINTN)FixedPcdGet64 (PcdDeviceTreeInitialBaseAddress);\r
+ ASSERT (DeviceTreeBase != NULL);\r
+\r
+ //\r
+ // Make sure we have a valid device tree blob\r
+ //\r
+ ASSERT (fdt_check_header (DeviceTreeBase) == 0);\r
+\r
+ //\r
+ // Look for a memory node\r
+ //\r
+ for (Prev = 0; !(HaveMemory && HaveUART); Prev = Node) {\r
+ Node = fdt_next_node (DeviceTreeBase, Prev, NULL);\r
+ if (Node < 0) {\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Check for memory node\r
+ //\r
+ Type = fdt_getprop (DeviceTreeBase, Node, "device_type", &Len);\r
+ if (Type && AsciiStrnCmp (Type, "memory", Len) == 0) {\r
+ //\r
+ // Get the 'reg' property of this node. For now, we will assume\r
+ // two 8 byte quantities for base and size, respectively.\r
+ //\r
+ RegProp = fdt_getprop (DeviceTreeBase, Node, "reg", &Len);\r
+ if (RegProp != 0 && Len == (2 * sizeof (UINT64))) {\r
+\r
+ NewBase = fdt64_to_cpu (ReadUnaligned64 (RegProp));\r
+ NewSize = fdt64_to_cpu (ReadUnaligned64 (RegProp + 1));\r
+\r
+ //\r
+ // Make sure the start of DRAM matches our expectation\r
+ //\r
+ ASSERT (FixedPcdGet64 (PcdSystemMemoryBase) == NewBase);\r
+ PcdSet64 (PcdSystemMemorySize, NewSize);\r
+\r
+ DEBUG ((EFI_D_INFO, "%a: System RAM @ 0x%lx - 0x%lx\n",\r
+ __FUNCTION__, NewBase, NewBase + NewSize - 1));\r
+ } else {\r
+ DEBUG ((EFI_D_ERROR, "%a: Failed to parse FDT memory node\n",\r
+ __FUNCTION__));\r
+ }\r
+ HaveMemory = TRUE;\r
+ continue;\r
+ }\r
+\r
+ //\r
+ // Check for UART node\r
+ //\r
+ Compatible = fdt_getprop (DeviceTreeBase, Node, "compatible", &Len);\r
+\r
+ //\r
+ // Iterate over the NULL-separated items in the compatible string\r
+ //\r
+ for (CompItem = Compatible; CompItem != NULL && CompItem < Compatible + Len;\r
+ CompItem += 1 + AsciiStrLen (CompItem)) {\r
+\r
+ if (AsciiStrCmp (CompItem, "arm,pl011") == 0) {\r
+ RegProp = fdt_getprop (DeviceTreeBase, Node, "reg", &Len);\r
+ ASSERT (Len == 16);\r
+\r
+ UartBase = fdt64_to_cpu (ReadUnaligned64 (RegProp));\r
+\r
+ DEBUG ((EFI_D_INFO, "%a: PL011 UART @ 0x%lx\n", __FUNCTION__, UartBase));\r
+\r
+ *HobData = UartBase;\r
+\r
+ HaveUART = TRUE;\r
+ continue;\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // We need to make sure that the machine we are running on has at least\r
+ // 128 MB of memory configured, and is currently executing this binary from\r
+ // NOR flash. This prevents a device tree image in DRAM from getting\r
+ // clobbered when our caller installs permanent PEI RAM, before we have a\r
+ // chance of marking its location as reserved or copy it to a freshly\r
+ // allocated block in the permanent PEI RAM in the platform PEIM.\r
+ //\r
+ ASSERT (NewSize >= SIZE_128MB);\r
+ ASSERT (\r
+ (((UINT64)PcdGet32 (PcdFdBaseAddress) +\r
+ (UINT64)PcdGet32 (PcdFdSize)) <= NewBase) ||\r
+ ((UINT64)PcdGet32 (PcdFdBaseAddress) >= (NewBase + NewSize)));\r
+}\r
+\r
+VOID\r
+ArmPlatformGetPlatformPpiList (\r
+ OUT UINTN *PpiListSize,\r
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
+ )\r
+{\r
+ *PpiListSize = 0;\r
+ *PpiList = NULL;\r
+}\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/ArmPlatformGlobalVariableLib.h>\r
+#include <ArmPlatform.h>\r
+\r
+// Number of Virtual Memory Map Descriptors\r
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 4\r
+\r
+// DDR attributes\r
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
+\r
+EFI_PHYSICAL_ADDRESS\r
+ArmGetPhysAddrTop (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Return the Virtual Memory Map of your platform\r
+\r
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU\r
+ on your platform.\r
+\r
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR\r
+ describing a Physical-to-Virtual Memory\r
+ mapping. This array must be ended by a\r
+ zero-filled entry\r
+\r
+**/\r
+VOID\r
+ArmPlatformGetVirtualMemoryMap (\r
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
+ )\r
+{\r
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;\r
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
+\r
+ ASSERT (VirtualMemoryMap != NULL);\r
+\r
+ VirtualMemoryTable = AllocatePages (\r
+ EFI_SIZE_TO_PAGES (\r
+ sizeof (ARM_MEMORY_REGION_DESCRIPTOR)\r
+ * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS\r
+ )\r
+ );\r
+\r
+ if (VirtualMemoryTable == NULL) {\r
+ DEBUG ((EFI_D_ERROR, "%a: Error: Failed AllocatePages()\n", __FUNCTION__));\r
+ return;\r
+ }\r
+\r
+ if (FeaturePcdGet (PcdCacheEnable) == TRUE) {\r
+ CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
+ } else {\r
+ CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
+ }\r
+\r
+ // System DRAM\r
+ VirtualMemoryTable[0].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);\r
+ VirtualMemoryTable[0].VirtualBase = VirtualMemoryTable[0].PhysicalBase;\r
+ VirtualMemoryTable[0].Length = PcdGet64 (PcdSystemMemorySize);\r
+ VirtualMemoryTable[0].Attributes = CacheAttributes;\r
+\r
+ DEBUG ((EFI_D_INFO, "%a: Dumping System DRAM Memory Map:\n"\r
+ "\tPhysicalBase: 0x%lX\n"\r
+ "\tVirtualBase: 0x%lX\n"\r
+ "\tLength: 0x%lX\n",\r
+ __FUNCTION__,\r
+ VirtualMemoryTable[0].PhysicalBase,\r
+ VirtualMemoryTable[0].VirtualBase,\r
+ VirtualMemoryTable[0].Length));\r
+\r
+ // Peripheral space before DRAM\r
+ VirtualMemoryTable[1].PhysicalBase = 0x0;\r
+ VirtualMemoryTable[1].VirtualBase = 0x0;\r
+ VirtualMemoryTable[1].Length = VirtualMemoryTable[0].PhysicalBase;\r
+ VirtualMemoryTable[1].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // Peripheral space after DRAM\r
+ VirtualMemoryTable[2].PhysicalBase = VirtualMemoryTable[0].Length + VirtualMemoryTable[1].Length;\r
+ VirtualMemoryTable[2].VirtualBase = VirtualMemoryTable[2].PhysicalBase;\r
+ VirtualMemoryTable[2].Length = ArmGetPhysAddrTop () - VirtualMemoryTable[2].PhysicalBase;\r
+ VirtualMemoryTable[2].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // End of Table\r
+ ZeroMem (&VirtualMemoryTable[3], sizeof (ARM_MEMORY_REGION_DESCRIPTOR));\r
+\r
+ *VirtualMemoryMap = VirtualMemoryTable;\r
+}\r
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