1. Added SetLocalApicBaseAdress() and GetLocalApicBaseAddress() APIs in Local APIC...

2. Updated Local APIC library instances to get Local APIC base Address by invoking GetLocalApicBaseAddress() instead of by PCD PcdCpuLocalApicBaseAddress.

Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Kinney Michael D <michael.d.kinney@intel.com>
Reviewed-by: Rui Sun <rui.sun@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13668 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h
index 52914fa9bdf97b7907b77f6b44870f3747b620f8..ed847b9579319d3bce53ea0de9441cc7e2318109 100644 (file)
--- a/UefiCpuPkg/Include/Library/LocalApicLib.h
+++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
@@ -4,7 +4,7 @@
   Local APIC library assumes local APIC is enabled. It does not\r
   handles cases where local APIC is disabled.\r
 \r
-  Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -21,6 +21,32 @@
 #define LOCAL_APIC_MODE_XAPIC   0x1  ///< xAPIC mode.\r
 #define LOCAL_APIC_MODE_X2APIC  0x2  ///< x2APIC mode.\r
 \r
+/**\r
+  Retrieve the base address of local APIC.\r
+\r
+  @return The base address of local APIC.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+GetLocalApicBaseAddress (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Set the base address of local APIC.\r
+\r
+  If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r
+\r
+  @param[in] BaseAddress   Local APIC base address to be set.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SetLocalApicBaseAddress (\r
+  IN UINTN                BaseAddress\r
+  );\r
+\r
 /**\r
   Get the current local APIC mode.\r
 \r

diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
index 77c24deed0b3096b941bea0d3c62bac96ae8d757..53c1610810722a85d5c99a28dfea695e6f10345b 100644 (file)
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -3,7 +3,7 @@
 \r
   This local APIC library instance supports xAPIC mode only.\r
 \r
-  Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -21,12 +21,57 @@
 #include <Library/LocalApicLib.h>\r
 #include <Library/IoLib.h>\r
 #include <Library/TimerLib.h>\r
-#include <Library/PcdLib.h>\r
 \r
 //\r
 // Library internal functions\r
 //\r
 \r
+/**\r
+  Retrieve the base address of local APIC.\r
+\r
+  @return The base address of local APIC.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+GetLocalApicBaseAddress (\r
+  VOID\r
+  )\r
+{\r
+  MSR_IA32_APIC_BASE ApicBaseMsr;\r
+  \r
+  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+  \r
+  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +\r
+           (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);\r
+}\r
+\r
+/**\r
+  Set the base address of local APIC.\r
+\r
+  If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r
+\r
+  @param[in] BaseAddress   Local APIC base address to be set.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SetLocalApicBaseAddress (\r
+  IN UINTN                BaseAddress\r
+  )\r
+{\r
+  MSR_IA32_APIC_BASE ApicBaseMsr;\r
+\r
+  ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r
+\r
+  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+\r
+  ApicBaseMsr.Bits.ApicBaseLow  = (UINT32) (BaseAddress >> 12);\r
+  ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
+\r
+  AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r
+}\r
+\r
 /**\r
   Read from a local APIC register.\r
 \r
@@ -49,7 +94,7 @@ ReadLocalApicReg (
   ASSERT ((MmioOffset & 0xf) == 0);\r
   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
 \r
-  return MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset);\r
+  return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);\r
 }\r
 \r
 /**\r
@@ -76,7 +121,7 @@ WriteLocalApicReg (
   ASSERT ((MmioOffset & 0xf) == 0);\r
   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
 \r
-  MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset, Value);\r
+  MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);\r
 }\r
 \r
 /**\r

diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
index 470e02971de53a2d1334ad6eb1a7a5987b12dbe5..5f0f0be1bbdc5741ca8cb460660932bca22e3415 100644 (file)
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
@@ -3,7 +3,7 @@
 #\r
 #  This library instance supports xAPIC mode only.\r
 #\r
-#  Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
+#  Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>\r
 #  This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
 #  which accompanies this distribution.  The full text of the license may be found at\r
@@ -41,6 +41,3 @@
   TimerLib\r
   IoLib\r
 \r
-[Pcd]\r
-  gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress\r
-\r

diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index 62201cd2404128dab76adc968e430a3af7650617..48468e8bc96b465b52ced2d458ac3953b905e8cd 100644 (file)
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -4,7 +4,7 @@
   This local APIC library instance supports x2APIC capable processors\r
   which have xAPIC and x2APIC modes.\r
 \r
-  Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -22,12 +22,57 @@
 #include <Library/LocalApicLib.h>\r
 #include <Library/IoLib.h>\r
 #include <Library/TimerLib.h>\r
-#include <Library/PcdLib.h>\r
 \r
 //\r
 // Library internal functions\r
 //\r
 \r
+/**\r
+  Retrieve the base address of local APIC.\r
+\r
+  @return The base address of local APIC.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+GetLocalApicBaseAddress (\r
+  VOID\r
+  )\r
+{\r
+  MSR_IA32_APIC_BASE ApicBaseMsr;\r
+  \r
+  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+  \r
+  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +\r
+           (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);\r
+}\r
+\r
+/**\r
+  Set the base address of local APIC.\r
+\r
+  If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r
+\r
+  @param[in] BaseAddress   Local APIC base address to be set.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SetLocalApicBaseAddress (\r
+  IN UINTN                BaseAddress\r
+  )\r
+{\r
+  MSR_IA32_APIC_BASE ApicBaseMsr;\r
+\r
+  ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r
+\r
+  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+\r
+  ApicBaseMsr.Bits.ApicBaseLow  = (UINT32) (BaseAddress >> 12);\r
+  ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
+\r
+  AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r
+}\r
+\r
 /**\r
   Read from a local APIC register.\r
 \r
@@ -52,7 +97,7 @@ ReadLocalApicReg (
   ASSERT ((MmioOffset & 0xf) == 0);\r
 \r
   if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
-    return MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset);\r
+    return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);\r
   } else {\r
     //\r
     // DFR is not supported in x2APIC mode.\r
@@ -95,7 +140,7 @@ WriteLocalApicReg (
   ASSERT ((MmioOffset & 0xf) == 0);\r
 \r
   if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
-    MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset, Value);\r
+    MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);\r
   } else {\r
     //\r
     // DFR is not supported in x2APIC mode.\r
@@ -134,6 +179,7 @@ SendIpi (
 {\r
   UINT64             MsrValue;\r
   LOCAL_APIC_ICR_LOW IcrLowReg;\r
+  UINTN              LocalApciBaseAddress;\r
 \r
   if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
     ASSERT (ApicId <= 0xff);\r
@@ -141,10 +187,11 @@ SendIpi (
     //\r
     // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r
     //\r
-    MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r
-    MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + XAPIC_ICR_LOW_OFFSET, IcrLow);\r
+    LocalApciBaseAddress = GetLocalApicBaseAddress();\r
+    MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r
+    MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET, IcrLow);\r
     do {\r
-      IcrLowReg.Uint32 = MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + XAPIC_ICR_LOW_OFFSET);\r
+      IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);\r
     } while (IcrLowReg.Bits.DeliveryStatus != 0);\r
   } else {\r
     //\r

diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
index df2769c9ff84a1f4aa4635fa544713f75fb90d35..baece39a4362e2d54181df0ecedb19020a7266a1 100644 (file)
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
@@ -4,7 +4,7 @@
 #  This library instance supports x2APIC capable processors\r
 #  which have xAPIC and x2APIC modes.\r
 #\r
-#  Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
+#  Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>\r
 #  This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
 #  which accompanies this distribution.  The full text of the license may be found at\r
@@ -42,6 +42,3 @@
   TimerLib\r
   IoLib\r
 \r
-[Pcd]\r
-  gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress\r
-\r