Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);\r
AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);\r
@endcode\r
+ @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
**/\r
#define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);\r
AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
**/\r
#define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);\r
AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r
**/\r
#define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);\r
@endcode\r
+ @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
#define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);\r
@endcode\r
+ @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
**/\r
#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);\r
@endcode\r
+ @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.\r
**/\r
#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_MC5_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
+ MSR_HASWELL_E_MC6_CTL is defined as MSR_MC6_CTL in SDM.\r
+ MSR_HASWELL_E_MC7_CTL is defined as MSR_MC7_CTL in SDM.\r
+ MSR_HASWELL_E_MC8_CTL is defined as MSR_MC8_CTL in SDM.\r
+ MSR_HASWELL_E_MC9_CTL is defined as MSR_MC9_CTL in SDM.\r
+ MSR_HASWELL_E_MC10_CTL is defined as MSR_MC10_CTL in SDM.\r
+ MSR_HASWELL_E_MC11_CTL is defined as MSR_MC11_CTL in SDM.\r
+ MSR_HASWELL_E_MC12_CTL is defined as MSR_MC12_CTL in SDM.\r
+ MSR_HASWELL_E_MC13_CTL is defined as MSR_MC13_CTL in SDM.\r
+ MSR_HASWELL_E_MC14_CTL is defined as MSR_MC14_CTL in SDM.\r
+ MSR_HASWELL_E_MC15_CTL is defined as MSR_MC15_CTL in SDM.\r
+ MSR_HASWELL_E_MC16_CTL is defined as MSR_MC16_CTL in SDM.\r
+ MSR_HASWELL_E_MC17_CTL is defined as MSR_MC17_CTL in SDM.\r
+ MSR_HASWELL_E_MC18_CTL is defined as MSR_MC18_CTL in SDM.\r
+ MSR_HASWELL_E_MC19_CTL is defined as MSR_MC19_CTL in SDM.\r
+ MSR_HASWELL_E_MC20_CTL is defined as MSR_MC20_CTL in SDM.\r
+ MSR_HASWELL_E_MC21_CTL is defined as MSR_MC21_CTL in SDM.\r
@{\r
**/\r
#define MSR_HASWELL_E_MC5_CTL 0x00000414\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_MC5_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
+ MSR_HASWELL_E_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.\r
+ MSR_HASWELL_E_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.\r
+ MSR_HASWELL_E_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.\r
+ MSR_HASWELL_E_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.\r
+ MSR_HASWELL_E_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.\r
+ MSR_HASWELL_E_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.\r
+ MSR_HASWELL_E_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.\r
+ MSR_HASWELL_E_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.\r
+ MSR_HASWELL_E_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.\r
+ MSR_HASWELL_E_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.\r
+ MSR_HASWELL_E_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.\r
+ MSR_HASWELL_E_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.\r
+ MSR_HASWELL_E_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.\r
+ MSR_HASWELL_E_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.\r
+ MSR_HASWELL_E_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.\r
+ MSR_HASWELL_E_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.\r
@{\r
**/\r
#define MSR_HASWELL_E_MC5_STATUS 0x00000415\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_ADDR);\r
AsmWriteMsr64 (MSR_HASWELL_E_MC5_ADDR, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
+ MSR_HASWELL_E_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.\r
+ MSR_HASWELL_E_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.\r
+ MSR_HASWELL_E_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.\r
+ MSR_HASWELL_E_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.\r
+ MSR_HASWELL_E_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.\r
+ MSR_HASWELL_E_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.\r
+ MSR_HASWELL_E_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.\r
+ MSR_HASWELL_E_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.\r
+ MSR_HASWELL_E_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.\r
+ MSR_HASWELL_E_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.\r
+ MSR_HASWELL_E_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.\r
+ MSR_HASWELL_E_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.\r
+ MSR_HASWELL_E_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.\r
+ MSR_HASWELL_E_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.\r
+ MSR_HASWELL_E_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.\r
+ MSR_HASWELL_E_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.\r
@{\r
**/\r
#define MSR_HASWELL_E_MC5_ADDR 0x00000416\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_MISC);\r
AsmWriteMsr64 (MSR_HASWELL_E_MC5_MISC, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
+ MSR_HASWELL_E_MC6_MISC is defined as MSR_MC6_MISC in SDM.\r
+ MSR_HASWELL_E_MC7_MISC is defined as MSR_MC7_MISC in SDM.\r
+ MSR_HASWELL_E_MC8_MISC is defined as MSR_MC8_MISC in SDM.\r
+ MSR_HASWELL_E_MC9_MISC is defined as MSR_MC9_MISC in SDM.\r
+ MSR_HASWELL_E_MC10_MISC is defined as MSR_MC10_MISC in SDM.\r
+ MSR_HASWELL_E_MC11_MISC is defined as MSR_MC11_MISC in SDM.\r
+ MSR_HASWELL_E_MC12_MISC is defined as MSR_MC12_MISC in SDM.\r
+ MSR_HASWELL_E_MC13_MISC is defined as MSR_MC13_MISC in SDM.\r
+ MSR_HASWELL_E_MC14_MISC is defined as MSR_MC14_MISC in SDM.\r
+ MSR_HASWELL_E_MC15_MISC is defined as MSR_MC15_MISC in SDM.\r
+ MSR_HASWELL_E_MC16_MISC is defined as MSR_MC16_MISC in SDM.\r
+ MSR_HASWELL_E_MC17_MISC is defined as MSR_MC17_MISC in SDM.\r
+ MSR_HASWELL_E_MC18_MISC is defined as MSR_MC18_MISC in SDM.\r
+ MSR_HASWELL_E_MC19_MISC is defined as MSR_MC19_MISC in SDM.\r
+ MSR_HASWELL_E_MC20_MISC is defined as MSR_MC20_MISC in SDM.\r
+ MSR_HASWELL_E_MC21_MISC is defined as MSR_MC21_MISC in SDM.\r
@{\r
**/\r
#define MSR_HASWELL_E_MC5_MISC 0x00000417\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);\r
@endcode\r
+ @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
#define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);\r
AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
**/\r
#define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618\r
\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);\r
@endcode\r
+ @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619\r
\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);\r
@endcode\r
+ @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);\r
AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
**/\r
#define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);\r
AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
**/\r
#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);\r
AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
**/\r
#define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);\r
AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
**/\r
#define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);\r
AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.\r
**/\r
#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);\r
AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.\r
**/\r
#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_U_PMON_CTR0 0x00000709\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);\r
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.\r
**/\r
#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);\r
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.\r
**/\r
#define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);\r
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.\r
**/\r
#define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);\r
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.\r
**/\r
#define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);\r
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.\r
**/\r
#define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);\r
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.\r
**/\r
#define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.\r
**/\r
#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);\r
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM.\r
+ MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM.\r
+ MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM.\r
+ MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.\r
@{\r
**/\r
#define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18\r