UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitions

#define MSR_IA32_APIC_BASE_ADDRESS is duplicated with #define MSR_IA32_APIC_BASE
defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it
and update the modules to use MSR_IA32_APIC_BASE from ArchitecturalMsr.h.

Structure MSR_IA32_APIC_BASE conflicts with #define MSR_IA32_APIC_BASE defined
in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and
update the modules to use structure MSR_IA32_APIC_BASE_REGISTER from
ArchitecturalMsr.h.

v5:
  1. Update SourceLevelDebugPkg to use APIC Base MSR from ArchitecturalMsr.h.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>

diff --git a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.h b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.h
index 64e4c3eaf0dc4f46b33453cf85c6e64f03a51444..e09ead9cf07433ea259af116b844a727ce9e0729 100644 (file)
--- a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.h
+++ b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.h
@@ -1,7 +1,7 @@
 /** @file\r
   Command header of for Debug Agent library instance.\r
 \r
 /** @file\r
   Command header of for Debug Agent library instance.\r
 \r

-  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r

   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r


@@ -34,6 +34,7 @@
 #include <Library/PrintLib.h>\r
 #include <Library/PeCoffGetEntryPointLib.h>\r
 #include <Library/PeCoffExtraActionLib.h>\r
 #include <Library/PrintLib.h>\r
 #include <Library/PeCoffGetEntryPointLib.h>\r
 #include <Library/PeCoffExtraActionLib.h>\r

+#include <Register/ArchitecturalMsr.h>\r

 \r
 #include <TransferProtocol.h>\r
 #include <ImageDebugSupport.h>\r
 \r
 #include <TransferProtocol.h>\r
 #include <ImageDebugSupport.h>\r

diff --git a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c
index bdb6742811ea03f47ffea623b8480f1ef9f800eb..d49d4ee32347f6481f0d320dbb94aeb03b1f57f4 100644 (file)
--- a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c
+++ b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c
@@ -1,7 +1,7 @@
 /** @file\r
   Multi-Processor support functions implementation.\r
 \r
 /** @file\r
   Multi-Processor support functions implementation.\r
 \r

-  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r

   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r


@@ -141,6 +141,8 @@ IsBsp (
   IN UINT32  ProcessorIndex\r
   )\r
 {\r
   IN UINT32  ProcessorIndex\r
   )\r
 {\r

+  MSR_IA32_APIC_BASE_REGISTER  MsrApicBase;\r
+  \r

   //\r
   // If there are less than 2 CPUs detected, then the currently executing CPU\r
   // must be the BSP.  This avoids an access to an MSR that may not be supported \r
   //\r
   // If there are less than 2 CPUs detected, then the currently executing CPU\r
   // must be the BSP.  This avoids an access to an MSR that may not be supported \r


@@ -150,7 +152,8 @@ IsBsp (
     return TRUE;\r
   }\r
 \r
     return TRUE;\r
   }\r
 \r

-  if (AsmMsrBitFieldRead64 (MSR_IA32_APIC_BASE_ADDRESS, 8, 8) == 1) {\r
+  MsrApicBase.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
+  if (MsrApicBase.Bits.BSP == 1) {\r

     if (mDebugMpContext.BspIndex != ProcessorIndex) {\r
       AcquireMpSpinLock (&mDebugMpContext.MpContextSpinLock);\r
       mDebugMpContext.BspIndex = ProcessorIndex;\r
     if (mDebugMpContext.BspIndex != ProcessorIndex) {\r
       AcquireMpSpinLock (&mDebugMpContext.MpContextSpinLock);\r
       mDebugMpContext.BspIndex = ProcessorIndex;\r

diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.h b/UefiCpuPkg/CpuMpPei/CpuMpPei.h
index b2e578b96ab8e58004f5136433d0c38a1cbd1527..0d1a14a5f48a74b682199cef1010f60b50615004 100644 (file)
--- a/UefiCpuPkg/CpuMpPei/CpuMpPei.h
+++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.h
@@ -25,6 +25,7 @@
 \r
 #include <Register/Cpuid.h>\r
 #include <Register/LocalApic.h>\r
 \r
 #include <Register/Cpuid.h>\r
 #include <Register/LocalApic.h>\r

+#include <Register/Msr.h>\r

 \r
 #include <Library/BaseLib.h>\r
 #include <Library/BaseMemoryLib.h>\r
 \r
 #include <Library/BaseLib.h>\r
 #include <Library/BaseMemoryLib.h>\r

diff --git a/UefiCpuPkg/CpuMpPei/PeiMpServices.c b/UefiCpuPkg/CpuMpPei/PeiMpServices.c
index e784377d674a5db253ed1d1cdcfca92fa5d9a771..e06fdf14fad5b1dfa0f0d22ac121cb5a9480d81f 100644 (file)
--- a/UefiCpuPkg/CpuMpPei/PeiMpServices.c
+++ b/UefiCpuPkg/CpuMpPei/PeiMpServices.c
@@ -1,7 +1,7 @@
 /** @file\r
   Implementation of Multiple Processor PPI services.\r
 \r
 /** @file\r
   Implementation of Multiple Processor PPI services.\r
 \r

-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r

   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r


@@ -729,9 +729,9 @@ PeiSwitchBSP (
   IN  BOOLEAN                  EnableOldBSP\r
   )\r
 {\r
   IN  BOOLEAN                  EnableOldBSP\r
   )\r
 {\r

-  PEI_CPU_MP_DATA         *PeiCpuMpData;\r
-  UINTN                   CallerNumber;\r
-  MSR_IA32_APIC_BASE      ApicBaseMsr;\r
+  PEI_CPU_MP_DATA              *PeiCpuMpData;\r
+  UINTN                        CallerNumber;\r
+  MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;\r

 \r
   PeiCpuMpData = GetMpHobData ();\r
   if (PeiCpuMpData == NULL) {\r
 \r
   PeiCpuMpData = GetMpHobData ();\r
   if (PeiCpuMpData == NULL) {\r


@@ -774,9 +774,9 @@ PeiSwitchBSP (
   //\r
   // Clear the BSP bit of MSR_IA32_APIC_BASE\r
   //\r
   //\r
   // Clear the BSP bit of MSR_IA32_APIC_BASE\r
   //\r

-  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
-  ApicBaseMsr.Bits.Bsp = 0;\r
-  AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r
+  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
+  ApicBaseMsr.Bits.BSP = 0;\r
+  AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r

 \r
   PeiCpuMpData->BSPInfo.State = CPU_SWITCH_STATE_IDLE;\r
   PeiCpuMpData->APInfo.State  = CPU_SWITCH_STATE_IDLE;\r
 \r
   PeiCpuMpData->BSPInfo.State = CPU_SWITCH_STATE_IDLE;\r
   PeiCpuMpData->APInfo.State  = CPU_SWITCH_STATE_IDLE;\r


@@ -805,9 +805,9 @@ PeiSwitchBSP (
   //\r
   // Set the BSP bit of MSR_IA32_APIC_BASE on new BSP\r
   //\r
   //\r
   // Set the BSP bit of MSR_IA32_APIC_BASE on new BSP\r
   //\r

-  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
-  ApicBaseMsr.Bits.Bsp = 1;\r
-  AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r
+  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
+  ApicBaseMsr.Bits.BSP = 1;\r
+  AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r

   //\r
   // Set old BSP enable state\r
   //\r
   //\r
   // Set old BSP enable state\r
   //\r

diff --git a/UefiCpuPkg/Include/Register/LocalApic.h b/UefiCpuPkg/Include/Register/LocalApic.h
index 346cce675643062d137adc2da9dba533d6ce317e..cfb6d76d8b3449244e9c92e790c70dae7d9bd709 100644 (file)
--- a/UefiCpuPkg/Include/Register/LocalApic.h
+++ b/UefiCpuPkg/Include/Register/LocalApic.h
@@ -1,7 +1,7 @@
 /** @file\r
   IA32 Local APIC Definitions.\r
 \r
 /** @file\r
   IA32 Local APIC Definitions.\r
 \r

-  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r

   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r


@@ -15,11 +15,6 @@
 #ifndef __LOCAL_APIC_H__\r
 #define __LOCAL_APIC_H__\r
 \r
 #ifndef __LOCAL_APIC_H__\r
 #define __LOCAL_APIC_H__\r
 \r

-//\r
-// Definitions for IA32 architectural MSRs\r
-//\r
-#define MSR_IA32_APIC_BASE_ADDRESS              0x1B\r
-\r

 //\r
 // Definition for Local APIC registers and related values\r
 //\r
 //\r
 // Definition for Local APIC registers and related values\r
 //\r


@@ -53,19 +48,6 @@
 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2\r
 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3\r
 \r
 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2\r
 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3\r
 \r

-typedef union {\r
-  struct {\r
-    UINT32  Reserved0:8;     ///< Reserved.\r
-    UINT32  Bsp:1;           ///< Processor is BSP.\r
-    UINT32  Reserved1:1;     ///< Reserved.\r
-    UINT32  Extd:1;          ///< Enable x2APIC mode.\r
-    UINT32  En:1;            ///< xAPIC global enable/disable.\r
-    UINT32  ApicBaseLow:20;  ///< APIC Base physical address. The actual field width depends on physical address width.\r
-    UINT32  ApicBaseHigh:32;\r
-  } Bits;\r
-  UINT64    Uint64;\r
-} MSR_IA32_APIC_BASE;\r
-\r

 //\r
 // Local APIC Version Register.\r
 //\r
 //\r
 // Local APIC Version Register.\r
 //\r

diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
index 1fca66ef1b293b76483aa818d5e757c094e5d01c..8d0fb021092992bac3904fdfc1e8d15e3436078a 100644 (file)
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -3,7 +3,7 @@
 \r
   This local APIC library instance supports xAPIC mode only.\r
 \r
 \r
   This local APIC library instance supports xAPIC mode only.\r
 \r

-  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r

   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r


@@ -15,6 +15,7 @@
 **/\r
 \r
 #include <Register/Cpuid.h>\r
 **/\r
 \r
 #include <Register/Cpuid.h>\r

+#include <Register/Msr.h>\r

 #include <Register/LocalApic.h>\r
 \r
 #include <Library/BaseLib.h>\r
 #include <Register/LocalApic.h>\r
 \r
 #include <Library/BaseLib.h>\r


@@ -67,7 +68,7 @@ GetLocalApicBaseAddress (
   VOID\r
   )\r
 {\r
   VOID\r
   )\r
 {\r

-  MSR_IA32_APIC_BASE  ApicBaseMsr;\r
+  MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;\r

 \r
   if (!LocalApicBaseAddressMsrSupported ()) {\r
     //\r
 \r
   if (!LocalApicBaseAddressMsrSupported ()) {\r
     //\r


@@ -77,10 +78,10 @@ GetLocalApicBaseAddress (
     return PcdGet32 (PcdCpuLocalApicBaseAddress);\r
   }\r
 \r
     return PcdGet32 (PcdCpuLocalApicBaseAddress);\r
   }\r
 \r

-  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r

   \r
   \r

-  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +\r
-           (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);\r
+  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
+           (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -97,7 +98,7 @@ SetLocalApicBaseAddress (
   IN UINTN                BaseAddress\r
   )\r
 {\r
   IN UINTN                BaseAddress\r
   )\r
 {\r

-  MSR_IA32_APIC_BASE  ApicBaseMsr;\r
+  MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;\r

 \r
   ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r
 \r
 \r
   ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r
 \r


@@ -108,12 +109,12 @@ SetLocalApicBaseAddress (
     return;\r
   }\r
 \r
     return;\r
   }\r
 \r

-  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r

 \r
 \r

-  ApicBaseMsr.Bits.ApicBaseLow  = (UINT32) (BaseAddress >> 12);\r
-  ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
+  ApicBaseMsr.Bits.ApicBase   = (UINT32) (BaseAddress >> 12);\r
+  ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r

 \r
 \r

-  AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r
+  AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -246,18 +247,18 @@ GetApicMode (
 {\r
   DEBUG_CODE (\r
     {\r
 {\r
   DEBUG_CODE (\r
     {\r

-      MSR_IA32_APIC_BASE  ApicBaseMsr;\r
+      MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;\r

 \r
       //\r
       // Check to see if the CPU supports the APIC Base Address MSR \r
       //\r
       if (LocalApicBaseAddressMsrSupported ()) {\r
 \r
       //\r
       // Check to see if the CPU supports the APIC Base Address MSR \r
       //\r
       if (LocalApicBaseAddressMsrSupported ()) {\r

-        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r

         //\r
         // Local APIC should have been enabled\r
         //\r
         //\r
         // Local APIC should have been enabled\r
         //\r

-        ASSERT (ApicBaseMsr.Bits.En != 0);\r
-        ASSERT (ApicBaseMsr.Bits.Extd == 0);\r
+        ASSERT (ApicBaseMsr.Bits.EN != 0);\r
+        ASSERT (ApicBaseMsr.Bits.EXTD == 0);\r

       }\r
     }\r
   );\r
       }\r
     }\r
   );\r

diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index 38f5370cc3dfd5b6e8e01b67e4cba8f2f5b0afe9..4c4269612746c2840b5c792ce3b85c2f9ee7b622 100644 (file)
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -4,7 +4,7 @@
   This local APIC library instance supports x2APIC capable processors\r
   which have xAPIC and x2APIC modes.\r
 \r
   This local APIC library instance supports x2APIC capable processors\r
   which have xAPIC and x2APIC modes.\r
 \r

-  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r

   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r


@@ -16,6 +16,7 @@
 **/\r
 \r
 #include <Register/Cpuid.h>\r
 **/\r
 \r
 #include <Register/Cpuid.h>\r

+#include <Register/Msr.h>\r

 #include <Register/LocalApic.h>\r
 \r
 #include <Library/BaseLib.h>\r
 #include <Register/LocalApic.h>\r
 \r
 #include <Library/BaseLib.h>\r


@@ -68,7 +69,7 @@ GetLocalApicBaseAddress (
   VOID\r
   )\r
 {\r
   VOID\r
   )\r
 {\r

-  MSR_IA32_APIC_BASE  ApicBaseMsr;\r
+  MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;\r

 \r
   if (!LocalApicBaseAddressMsrSupported ()) {\r
     //\r
 \r
   if (!LocalApicBaseAddressMsrSupported ()) {\r
     //\r


@@ -78,10 +79,10 @@ GetLocalApicBaseAddress (
     return PcdGet32 (PcdCpuLocalApicBaseAddress);\r
   }\r
 \r
     return PcdGet32 (PcdCpuLocalApicBaseAddress);\r
   }\r
 \r

-  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r

   \r
   \r

-  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +\r
-           (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);\r
+  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
+           (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -98,7 +99,7 @@ SetLocalApicBaseAddress (
   IN UINTN                BaseAddress\r
   )\r
 {\r
   IN UINTN                BaseAddress\r
   )\r
 {\r

-  MSR_IA32_APIC_BASE  ApicBaseMsr;\r
+  MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;\r

 \r
   ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r
 \r
 \r
   ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r
 \r


@@ -109,12 +110,12 @@ SetLocalApicBaseAddress (
     return;\r
   }\r
 \r
     return;\r
   }\r
 \r

-  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r

 \r
 \r

-  ApicBaseMsr.Bits.ApicBaseLow  = (UINT32) (BaseAddress >> 12);\r
-  ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
+  ApicBaseMsr.Bits.ApicBase   = (UINT32) (BaseAddress >> 12);\r
+  ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r

 \r
 \r

-  AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r
+  AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -301,7 +302,7 @@ GetApicMode (
   VOID\r
   )\r
 {\r
   VOID\r
   )\r
 {\r

-  MSR_IA32_APIC_BASE  ApicBaseMsr;\r
+  MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;\r

 \r
   if (!LocalApicBaseAddressMsrSupported ()) {\r
     //\r
 \r
   if (!LocalApicBaseAddressMsrSupported ()) {\r
     //\r


@@ -310,12 +311,12 @@ GetApicMode (
     return LOCAL_APIC_MODE_XAPIC;\r
   }\r
 \r
     return LOCAL_APIC_MODE_XAPIC;\r
   }\r
 \r

-  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r

   //\r
   // Local APIC should have been enabled\r
   //\r
   //\r
   // Local APIC should have been enabled\r
   //\r

-  ASSERT (ApicBaseMsr.Bits.En != 0);\r
-  if (ApicBaseMsr.Bits.Extd != 0) {\r
+  ASSERT (ApicBaseMsr.Bits.EN != 0);\r
+  if (ApicBaseMsr.Bits.EXTD != 0) {\r

     return LOCAL_APIC_MODE_X2APIC;\r
   } else {\r
     return LOCAL_APIC_MODE_XAPIC;\r
     return LOCAL_APIC_MODE_X2APIC;\r
   } else {\r
     return LOCAL_APIC_MODE_XAPIC;\r


@@ -339,8 +340,8 @@ SetApicMode (
   IN UINTN  ApicMode\r
   )\r
 {\r
   IN UINTN  ApicMode\r
   )\r
 {\r

-  UINTN               CurrentMode;\r
-  MSR_IA32_APIC_BASE  ApicBaseMsr;\r
+  UINTN                        CurrentMode;\r
+  MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;\r

 \r
   if (!LocalApicBaseAddressMsrSupported ()) {\r
     //\r
 \r
   if (!LocalApicBaseAddressMsrSupported ()) {\r
     //\r


@@ -355,9 +356,9 @@ SetApicMode (
       case LOCAL_APIC_MODE_XAPIC:\r
         break;\r
       case LOCAL_APIC_MODE_X2APIC:\r
       case LOCAL_APIC_MODE_XAPIC:\r
         break;\r
       case LOCAL_APIC_MODE_X2APIC:\r

-        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
-        ApicBaseMsr.Bits.Extd = 1;\r
-        AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r
+        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
+        ApicBaseMsr.Bits.EXTD = 1;\r
+        AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r

         break;\r
       default:\r
         ASSERT (FALSE);\r
         break;\r
       default:\r
         ASSERT (FALSE);\r


@@ -369,12 +370,12 @@ SetApicMode (
         //  Transition from x2APIC mode to xAPIC mode is a two-step process:\r
         //    x2APIC -> Local APIC disabled -> xAPIC\r
         //\r
         //  Transition from x2APIC mode to xAPIC mode is a two-step process:\r
         //    x2APIC -> Local APIC disabled -> xAPIC\r
         //\r

-        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
-        ApicBaseMsr.Bits.Extd = 0;\r
-        ApicBaseMsr.Bits.En = 0;\r
-        AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r
-        ApicBaseMsr.Bits.En = 1;\r
-        AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r
+        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
+        ApicBaseMsr.Bits.EXTD = 0;\r
+        ApicBaseMsr.Bits.EN = 0;\r
+        AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
+        ApicBaseMsr.Bits.EN = 1;\r
+        AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r

         break;\r
       case LOCAL_APIC_MODE_X2APIC:\r
         break;\r
         break;\r
       case LOCAL_APIC_MODE_X2APIC:\r
         break;\r