--- /dev/null
+/** @file\r
+ This file contains some basic ACPI definitions that are consumed by drivers\r
+ that do not care about ACPI versions.\r
+\r
+ Copyright (c) 2006, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ Module Name: Acpi.h\r
+\r
+**/\r
+\r
+#ifndef _ACPI_H_\r
+#define _ACPI_H_\r
+\r
+//\r
+// Common table header, this prefaces all ACPI tables, including FACS, but\r
+// excluding the RSD PTR structure\r
+//\r
+typedef struct {\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+} EFI_ACPI_COMMON_HEADER;\r
+\r
+//\r
+// Common ACPI description table header. This structure prefaces most ACPI tables.\r
+//\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+ UINT8 Revision;\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT64 OemTableId;\r
+ UINT32 OemRevision;\r
+ UINT32 CreatorId;\r
+ UINT32 CreatorRevision;\r
+} EFI_ACPI_DESCRIPTION_HEADER;\r
+\r
+#pragma pack()\r
+//\r
+// Define for Pci Host Bridge Resource Allocation\r
+//\r
+#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A\r
+#define ACPI_END_TAG_DESCRIPTOR 0x79\r
+\r
+#define ACPI_ADDRESS_SPACE_TYPE_MEM 0x00\r
+#define ACPI_ADDRESS_SPACE_TYPE_IO 0x01\r
+#define ACPI_ADDRESS_SPACE_TYPE_BUS 0x02\r
+\r
+//\r
+// Power Management Timer frequency is fixed at 3.579545MHz\r
+//\r
+#define ACPI_TIMER_FREQUENCY 3579545\r
+\r
+//\r
+// Make sure structures match spec\r
+//\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+ UINT8 Desc;\r
+ UINT16 Len;\r
+ UINT8 ResType;\r
+ UINT8 GenFlag;\r
+ UINT8 SpecificFlag;\r
+ UINT64 AddrSpaceGranularity;\r
+ UINT64 AddrRangeMin;\r
+ UINT64 AddrRangeMax;\r
+ UINT64 AddrTranslationOffset;\r
+ UINT64 AddrLen;\r
+} EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
+\r
+typedef struct {\r
+ UINT8 Desc;\r
+ UINT8 Checksum;\r
+} EFI_ACPI_END_TAG_DESCRIPTOR;\r
+\r
+//\r
+// General use definitions\r
+//\r
+#define EFI_ACPI_RESERVED_BYTE 0x00\r
+#define EFI_ACPI_RESERVED_WORD 0x0000\r
+#define EFI_ACPI_RESERVED_DWORD 0x00000000\r
+#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000\r
+\r
+//\r
+// Resource Type Specific Flags\r
+// Ref ACPI specification 6.4.3.5.5\r
+//\r
+// Bit [0] : Write Status, _RW\r
+//\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_WRITE (1 << 0)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_ONLY (0 << 0)\r
+//\r
+// Bit [2:1] : Memory Attributes, _MEM\r
+//\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE (0 << 1)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE (1 << 1)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_WRITE_COMBINING (2 << 1)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE (3 << 1)\r
+//\r
+// Bit [4:3] : Memory Attributes, _MTP\r
+//\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_MEMORY (0 << 3)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_RESERVED (1 << 3)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_ACPI (2 << 3)\r
+#define EFI_APCI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_NVS (3 << 3)\r
+//\r
+// Bit [5] : Memory to I/O Translation, _TTP\r
+//\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_TRANSLATION (1 << 5)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_STATIC (0 << 5)\r
+\r
+#pragma pack()\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ ElTorito Partitions Format Definition.\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+--*/\r
+\r
+#ifndef _ELTORITO_H_\r
+#define _ELTORITO_H_\r
+\r
+//\r
+// CDROM_VOLUME_DESCRIPTOR.Types\r
+//\r
+#define CDVOL_TYPE_STANDARD 0x0\r
+#define CDVOL_TYPE_CODED 0x1\r
+#define CDVOL_TYPE_END 0xFF\r
+\r
+//\r
+// CDROM_VOLUME_DESCRIPTOR.Id\r
+//\r
+#define CDVOL_ID "CD001"\r
+\r
+//\r
+// CDROM_VOLUME_DESCRIPTOR.SystemId\r
+//\r
+#define CDVOL_ELTORITO_ID "EL TORITO SPECIFICATION"\r
+\r
+//\r
+// Indicator types\r
+//\r
+#define ELTORITO_ID_CATALOG 0x01\r
+#define ELTORITO_ID_SECTION_BOOTABLE 0x88\r
+#define ELTORITO_ID_SECTION_NOT_BOOTABLE 0x00\r
+#define ELTORITO_ID_SECTION_HEADER 0x90\r
+#define ELTORITO_ID_SECTION_HEADER_FINAL 0x91\r
+\r
+//\r
+// ELTORITO_CATALOG.Boot.MediaTypes\r
+//\r
+#define ELTORITO_NO_EMULATION 0x00\r
+#define ELTORITO_12_DISKETTE 0x01\r
+#define ELTORITO_14_DISKETTE 0x02\r
+#define ELTORITO_28_DISKETTE 0x03\r
+#define ELTORITO_HARD_DISK 0x04\r
+\r
+\r
+#pragma pack(1)\r
+\r
+//\r
+// El Torito Volume Descriptor\r
+// Note that the CDROM_VOLUME_DESCRIPTOR does not match the ISO-9660\r
+// descriptor. For some reason descriptor used by El Torito is\r
+// different, but they start the same. The El Torito descriptor\r
+// is left shifted 1 byte starting with the SystemId. (Note this\r
+// causes the field to get unaligned)\r
+//\r
+typedef struct {\r
+ UINT8 Type;\r
+ CHAR8 Id[5]; // CD001\r
+ UINT8 Version;\r
+ CHAR8 SystemId[26];\r
+ CHAR8 Unused[38];\r
+ UINT8 EltCatalog[4];\r
+ CHAR8 Unused2[5];\r
+ UINT32 VolSpaceSize[2];\r
+} CDROM_VOLUME_DESCRIPTOR;\r
+\r
+//\r
+// Catalog Entry\r
+//\r
+typedef union {\r
+ struct {\r
+ CHAR8 Reserved[0x20];\r
+ } Unknown;\r
+\r
+ //\r
+ // Catalog validation entry (Catalog header)\r
+ //\r
+ struct {\r
+ UINT8 Indicator;\r
+ UINT8 PlatformId;\r
+ UINT16 Reserved;\r
+ CHAR8 ManufacId[24];\r
+ UINT16 Checksum;\r
+ UINT16 Id55AA;\r
+ } Catalog;\r
+\r
+ //\r
+ // Initial/Default Entry or Section Entry\r
+ //\r
+ struct {\r
+ UINT8 Indicator;\r
+ UINT8 MediaType : 4;\r
+ UINT8 Reserved1 : 4;\r
+ UINT16 LoadSegment;\r
+ UINT8 SystemType;\r
+ UINT8 Reserved2;\r
+ UINT16 SectorCount;\r
+ UINT32 Lba;\r
+ } Boot;\r
+\r
+ //\r
+ // Section Header Entry\r
+ //\r
+ struct {\r
+ UINT8 Indicator;\r
+ UINT8 PlatformId;\r
+ UINT16 SectionEntries;\r
+ CHAR8 Id[28];\r
+ } Section;\r
+\r
+} ELTORITO_CATALOG;\r
+\r
+#pragma pack()\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Legacy Master Boot Record Format Definition.\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php\r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+--*/\r
+\r
+#ifndef _MBR_H_\r
+#define _MBR_H_\r
+\r
+#define MBR_SIGNATURE 0xaa55\r
+#define MIN_MBR_DEVICE_SIZE 0x80000\r
+#define MBR_ERRATA_PAD 0x40000 // 128 MB\r
+\r
+#define EXTENDED_DOS_PARTITION 0x05\r
+#define EXTENDED_WINDOWS_PARTITION 0x0F\r
+\r
+#define MAX_MBR_PARTITIONS 4\r
+\r
+#define PMBR_GPT_PARTITION 0xEE\r
+#define EFI_PARTITION 0xEF\r
+\r
+#define MBR_SIZE 512\r
+\r
+#pragma pack(1)\r
+//\r
+// MBR Partition Entry\r
+//\r
+typedef struct {\r
+ UINT8 BootIndicator;\r
+ UINT8 StartHead;\r
+ UINT8 StartSector;\r
+ UINT8 StartTrack;\r
+ UINT8 OSIndicator;\r
+ UINT8 EndHead;\r
+ UINT8 EndSector;\r
+ UINT8 EndTrack;\r
+ UINT8 StartingLBA[4];\r
+ UINT8 SizeInLBA[4];\r
+} MBR_PARTITION_RECORD;\r
+\r
+//\r
+// MBR Partition table\r
+//\r
+typedef struct {\r
+ UINT8 BootStrapCode[440];\r
+ UINT8 UniqueMbrSignature[4];\r
+ UINT8 Unknown[2];\r
+ MBR_PARTITION_RECORD Partition[MAX_MBR_PARTITIONS];\r
+ UINT16 Signature;\r
+} MASTER_BOOT_RECORD;\r
+\r
+#pragma pack()\r
+\r
+#endif\r
--- /dev/null
+\r
+/** @file\r
+ Support for The latest PCI standard.\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ Module Name: Pci.h\r
+\r
+**/\r
+\r
+#ifndef _PCI_H\r
+#define _PCI_H\r
+\r
+#include <IndustryStandard/Pci30.h>\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Support for PCI 2.2 standard.\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation \r
+ All rights reserved. This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ Module Name: pci22.h\r
+\r
+**/\r
+\r
+#ifndef _PCI22_H\r
+#define _PCI22_H\r
+\r
+#define PCI_MAX_SEGMENT 0\r
+\r
+#define PCI_MAX_BUS 255\r
+\r
+#define PCI_MAX_DEVICE 31\r
+#define PCI_MAX_FUNC 7\r
+\r
+//\r
+// Command\r
+//\r
+#define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20\r
+\r
+#pragma pack(push, 1)\r
+typedef struct {\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT8 RevisionID;\r
+ UINT8 ClassCode[3];\r
+ UINT8 CacheLineSize;\r
+ UINT8 LatencyTimer;\r
+ UINT8 HeaderType;\r
+ UINT8 BIST;\r
+} PCI_DEVICE_INDEPENDENT_REGION;\r
+\r
+typedef struct {\r
+ UINT32 Bar[6];\r
+ UINT32 CISPtr;\r
+ UINT16 SubsystemVendorID;\r
+ UINT16 SubsystemID;\r
+ UINT32 ExpansionRomBar;\r
+ UINT8 CapabilityPtr;\r
+ UINT8 Reserved1[3];\r
+ UINT32 Reserved2;\r
+ UINT8 InterruptLine;\r
+ UINT8 InterruptPin;\r
+ UINT8 MinGnt;\r
+ UINT8 MaxLat;\r
+} PCI_DEVICE_HEADER_TYPE_REGION;\r
+\r
+typedef struct {\r
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
+ PCI_DEVICE_HEADER_TYPE_REGION Device;\r
+} PCI_TYPE00;\r
+\r
+typedef struct {\r
+ UINT32 Bar[2];\r
+ UINT8 PrimaryBus;\r
+ UINT8 SecondaryBus;\r
+ UINT8 SubordinateBus;\r
+ UINT8 SecondaryLatencyTimer;\r
+ UINT8 IoBase;\r
+ UINT8 IoLimit;\r
+ UINT16 SecondaryStatus;\r
+ UINT16 MemoryBase;\r
+ UINT16 MemoryLimit;\r
+ UINT16 PrefetchableMemoryBase;\r
+ UINT16 PrefetchableMemoryLimit;\r
+ UINT32 PrefetchableBaseUpper32;\r
+ UINT32 PrefetchableLimitUpper32;\r
+ UINT16 IoBaseUpper16;\r
+ UINT16 IoLimitUpper16;\r
+ UINT8 CapabilityPtr;\r
+ UINT8 Reserved[3];\r
+ UINT32 ExpansionRomBAR;\r
+ UINT8 InterruptLine;\r
+ UINT8 InterruptPin;\r
+ UINT16 BridgeControl;\r
+} PCI_BRIDGE_CONTROL_REGISTER;\r
+\r
+typedef struct {\r
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
+ PCI_BRIDGE_CONTROL_REGISTER Bridge;\r
+} PCI_TYPE01;\r
+\r
+typedef union {\r
+ PCI_TYPE00 Device;\r
+ PCI_TYPE01 Bridge;\r
+} PCI_TYPE_GENERIC;\r
+\r
+typedef struct {\r
+ UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base\r
+ // Address Register\r
+ //\r
+ UINT16 Reserved;\r
+ UINT16 SecondaryStatus; // Secondary Status\r
+ UINT8 PciBusNumber; // PCI Bus Number\r
+ UINT8 CardBusBusNumber; // CardBus Bus Number\r
+ UINT8 SubordinateBusNumber; // Subordinate Bus Number\r
+ UINT8 CardBusLatencyTimer; // CardBus Latency Timer\r
+ UINT32 MemoryBase0; // Memory Base Register 0\r
+ UINT32 MemoryLimit0; // Memory Limit Register 0\r
+ UINT32 MemoryBase1;\r
+ UINT32 MemoryLimit1;\r
+ UINT32 IoBase0;\r
+ UINT32 IoLimit0; // I/O Base Register 0\r
+ UINT32 IoBase1; // I/O Limit Register 0\r
+ UINT32 IoLimit1;\r
+ UINT8 InterruptLine; // Interrupt Line\r
+ UINT8 InterruptPin; // Interrupt Pin\r
+ UINT16 BridgeControl; // Bridge Control\r
+} PCI_CARDBUS_CONTROL_REGISTER;\r
+\r
+//\r
+// Definitions of PCI class bytes and manipulation macros.\r
+//\r
+#define PCI_CLASS_OLD 0x00\r
+#define PCI_CLASS_OLD_OTHER 0x00\r
+#define PCI_CLASS_OLD_VGA 0x01\r
+\r
+#define PCI_CLASS_MASS_STORAGE 0x01\r
+#define PCI_CLASS_MASS_STORAGE_SCSI 0x00\r
+#define PCI_CLASS_MASS_STORAGE_IDE 0x01 // obsolete\r
+#define PCI_CLASS_IDE 0x01\r
+#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r
+#define PCI_CLASS_MASS_STORAGE_IPI 0x03\r
+#define PCI_CLASS_MASS_STORAGE_RAID 0x04\r
+#define PCI_CLASS_MASS_STORAGE_OTHER 0x80\r
+\r
+#define PCI_CLASS_NETWORK 0x02\r
+#define PCI_CLASS_NETWORK_ETHERNET 0x00\r
+#define PCI_CLASS_ETHERNET 0x00 // obsolete\r
+#define PCI_CLASS_NETWORK_TOKENRING 0x01\r
+#define PCI_CLASS_NETWORK_FDDI 0x02\r
+#define PCI_CLASS_NETWORK_ATM 0x03\r
+#define PCI_CLASS_NETWORK_ISDN 0x04\r
+#define PCI_CLASS_NETWORK_OTHER 0x80\r
+\r
+#define PCI_CLASS_DISPLAY 0x03\r
+#define PCI_CLASS_DISPLAY_CTRL 0x03 // obsolete\r
+#define PCI_CLASS_DISPLAY_VGA 0x00\r
+#define PCI_CLASS_VGA 0x00 // obsolete\r
+#define PCI_CLASS_DISPLAY_XGA 0x01\r
+#define PCI_CLASS_DISPLAY_3D 0x02\r
+#define PCI_CLASS_DISPLAY_OTHER 0x80\r
+#define PCI_CLASS_DISPLAY_GFX 0x80\r
+#define PCI_CLASS_GFX 0x80 // obsolete\r
+#define PCI_CLASS_BRIDGE 0x06\r
+#define PCI_CLASS_BRIDGE_HOST 0x00\r
+#define PCI_CLASS_BRIDGE_ISA 0x01\r
+#define PCI_CLASS_ISA 0x01 // obsolete\r
+#define PCI_CLASS_BRIDGE_EISA 0x02\r
+#define PCI_CLASS_BRIDGE_MCA 0x03\r
+#define PCI_CLASS_BRIDGE_P2P 0x04\r
+#define PCI_CLASS_BRIDGE_PCMCIA 0x05\r
+#define PCI_CLASS_BRIDGE_NUBUS 0x06\r
+#define PCI_CLASS_BRIDGE_CARDBUS 0x07\r
+#define PCI_CLASS_BRIDGE_RACEWAY 0x08\r
+#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r
+#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete\r
+\r
+#define PCI_CLASS_SCC 0x07 // Simple communications controllers \r
+#define PCI_SUBCLASS_SERIAL 0x00\r
+#define PCI_IF_GENERIC_XT 0x00\r
+#define PCI_IF_16450 0x01\r
+#define PCI_IF_16550 0x02\r
+#define PCI_IF_16650 0x03\r
+#define PCI_IF_16750 0x04\r
+#define PCI_IF_16850 0x05\r
+#define PCI_IF_16950 0x06\r
+#define PCI_SUBCLASS_PARALLEL 0x01\r
+#define PCI_IF_PARALLEL_PORT 0x00\r
+#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\r
+#define PCI_IF_ECP_PARALLEL_PORT 0x02\r
+#define PCI_IF_1284_CONTROLLER 0x03\r
+#define PCI_IF_1284_DEVICE 0xFE\r
+#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r
+#define PCI_SUBCLASS_MODEM 0x03\r
+#define PCI_IF_GENERIC_MODEM 0x00\r
+#define PCI_IF_16450_MODEM 0x01\r
+#define PCI_IF_16550_MODEM 0x02\r
+#define PCI_IF_16650_MODEM 0x03\r
+#define PCI_IF_16750_MODEM 0x04\r
+#define PCI_SUBCLASS_OTHER 0x80\r
+\r
+#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r
+#define PCI_SUBCLASS_PIC 0x00\r
+#define PCI_IF_8259_PIC 0x00\r
+#define PCI_IF_ISA_PIC 0x01\r
+#define PCI_IF_EISA_PIC 0x02\r
+#define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory. \r
+#define PCI_IF_APIC_CONTROLLER2 0x20 \r
+#define PCI_SUBCLASS_TIMER 0x02\r
+#define PCI_IF_8254_TIMER 0x00\r
+#define PCI_IF_ISA_TIMER 0x01\r
+#define PCI_EISA_TIMER 0x02\r
+#define PCI_SUBCLASS_RTC 0x03\r
+#define PCI_IF_GENERIC_RTC 0x00\r
+#define PCI_IF_ISA_RTC 0x00\r
+#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller\r
+\r
+#define PCI_CLASS_INPUT_DEVICE 0x09\r
+#define PCI_SUBCLASS_KEYBOARD 0x00\r
+#define PCI_SUBCLASS_PEN 0x01\r
+#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r
+#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r
+#define PCI_SUBCLASS_GAMEPORT 0x04\r
+\r
+#define PCI_CLASS_DOCKING_STATION 0x0A\r
+\r
+#define PCI_CLASS_PROCESSOR 0x0B\r
+#define PCI_SUBCLASS_PROC_386 0x00\r
+#define PCI_SUBCLASS_PROC_486 0x01\r
+#define PCI_SUBCLASS_PROC_PENTIUM 0x02\r
+#define PCI_SUBCLASS_PROC_ALPHA 0x10\r
+#define PCI_SUBCLASS_PROC_POWERPC 0x20\r
+#define PCI_SUBCLASS_PROC_MIPS 0x30\r
+#define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor\r
+\r
+#define PCI_CLASS_SERIAL 0x0C\r
+#define PCI_CLASS_SERIAL_FIREWIRE 0x00\r
+#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\r
+#define PCI_CLASS_SERIAL_SSA 0x02\r
+#define PCI_CLASS_SERIAL_USB 0x03\r
+#define PCI_IF_EHCI 0x20\r
+#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
+#define PCI_CLASS_SERIAL_SMB 0x05\r
+\r
+#define PCI_CLASS_WIRELESS 0x0D\r
+#define PCI_SUBCLASS_IRDA 0x00\r
+#define PCI_SUBCLASS_IR 0x01\r
+#define PCI_SUBCLASS_RF 0x02\r
+\r
+#define PCI_CLASS_INTELLIGENT_IO 0x0E\r
+\r
+#define PCI_CLASS_SATELLITE 0x0F\r
+#define PCI_SUBCLASS_TV 0x01\r
+#define PCI_SUBCLASS_AUDIO 0x02\r
+#define PCI_SUBCLASS_VOICE 0x03\r
+#define PCI_SUBCLASS_DATA 0x04\r
+\r
+#define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller\r
+#define PCI_SUBCLASS_NET_COMPUT 0x00\r
+#define PCI_SUBCLASS_ENTERTAINMENT 0x10 \r
+\r
+#define PCI_CLASS_DPIO 0x11\r
+\r
+#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r
+#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
+#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r
+\r
+#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r
+#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)\r
+#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)\r
+#define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)\r
+#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r
+#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r
+#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r
+#define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)\r
+#define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)\r
+#define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)\r
+#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)\r
+#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)\r
+#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
+#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r
+\r
+#define HEADER_TYPE_DEVICE 0x00\r
+#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r
+#define HEADER_TYPE_CARDBUS_BRIDGE 0x02\r
+\r
+#define HEADER_TYPE_MULTI_FUNCTION 0x80\r
+#define HEADER_LAYOUT_CODE 0x7f\r
+\r
+#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r
+#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r
+#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r
+\r
+#define PCI_DEVICE_ROMBAR 0x30\r
+#define PCI_BRIDGE_ROMBAR 0x38\r
+\r
+#define PCI_MAX_BAR 0x0006\r
+#define PCI_MAX_CONFIG_OFFSET 0x0100\r
+\r
+#define PCI_VENDOR_ID_OFFSET 0x00\r
+#define PCI_DEVICE_ID_OFFSET 0x02\r
+#define PCI_COMMAND_OFFSET 0x04\r
+#define PCI_PRIMARY_STATUS_OFFSET 0x06\r
+#define PCI_REVISION_ID_OFFSET 0x08\r
+#define PCI_CLASSCODE_OFFSET 0x09\r
+#define PCI_CACHELINE_SIZE_OFFSET 0x0C\r
+#define PCI_LATENCY_TIMER_OFFSET 0x0D\r
+#define PCI_HEADER_TYPE_OFFSET 0x0E\r
+#define PCI_BIST_OFFSET 0x0F\r
+#define PCI_BASE_ADDRESSREG_OFFSET 0x10\r
+#define PCI_CARDBUS_CIS_OFFSET 0x28\r
+#define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id\r
+#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\r
+#define PCI_SID_OFFSET 0x2E // SubSystem ID\r
+#define PCI_SUBSYSTEM_ID_OFFSET 0x2E\r
+#define PCI_EXPANSION_ROM_BASE 0x30\r
+#define PCI_CAPBILITY_POINTER_OFFSET 0x34\r
+#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register\r
+#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register\r
+#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register\r
+#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register\r
+\r
+#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E\r
+#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E\r
+\r
+#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18\r
+#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19\r
+#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a\r
+\r
+//\r
+// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r
+//\r
+#define PCI_INT_LINE_UNKNOWN 0xFF \r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 Reg : 8;\r
+ UINT32 Func : 3;\r
+ UINT32 Dev : 5;\r
+ UINT32 Bus : 8;\r
+ UINT32 Reserved : 7;\r
+ UINT32 Enable : 1;\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} PCI_CONFIG_ACCESS_CF8;\r
+\r
+#pragma pack()\r
+\r
+#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r
+#define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')\r
+#define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r
+#define PCI_CODE_TYPE_EFI_IMAGE 0x03\r
+#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001\r
+\r
+#define EFI_PCI_COMMAND_IO_SPACE 0x0001\r
+#define EFI_PCI_COMMAND_MEMORY_SPACE 0x0002\r
+#define EFI_PCI_COMMAND_BUS_MASTER 0x0004\r
+#define EFI_PCI_COMMAND_SPECIAL_CYCLE 0x0008\r
+#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE 0x0010\r
+#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP 0x0020\r
+#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND 0x0040\r
+#define EFI_PCI_COMMAND_STEPPING_CONTROL 0x0080\r
+#define EFI_PCI_COMMAND_SERR 0x0100\r
+#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK 0x0200\r
+\r
+#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE 0x0001\r
+#define EFI_PCI_BRIDGE_CONTROL_SERR 0x0002\r
+#define EFI_PCI_BRIDGE_CONTROL_ISA 0x0004\r
+#define EFI_PCI_BRIDGE_CONTROL_VGA 0x0008\r
+#define EFI_PCI_BRIDGE_CONTROL_VGA_16 0x0010\r
+#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT 0x0020\r
+#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS 0x0040\r
+#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK 0x0080\r
+#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER 0x0100\r
+#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER 0x0200\r
+#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS 0x0400\r
+#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR 0x0800\r
+\r
+//\r
+// Following are the PCI-CARDBUS bridge control bit\r
+//\r
+#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE 0x0080\r
+#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE 0x0100\r
+#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE 0x0200\r
+#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400\r
+\r
+//\r
+// Following are the PCI status control bit\r
+//\r
+#define EFI_PCI_STATUS_CAPABILITY 0x0010\r
+#define EFI_PCI_STATUS_66MZ_CAPABLE 0x0020\r
+#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE 0x0080\r
+#define EFI_PCI_MASTER_DATA_PARITY_ERROR 0x0100\r
+\r
+#define EFI_PCI_CAPABILITY_PTR 0x34\r
+#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+ UINT16 Signature; // 0xaa55\r
+ UINT8 Reserved[0x16];\r
+ UINT16 PcirOffset;\r
+} PCI_EXPANSION_ROM_HEADER;\r
+\r
+typedef struct {\r
+ UINT16 Signature; // 0xaa55\r
+ UINT8 Size512;\r
+ UINT8 InitEntryPoint[3];\r
+ UINT8 Reserved[0x12];\r
+ UINT16 PcirOffset;\r
+} EFI_LEGACY_EXPANSION_ROM_HEADER;\r
+\r
+typedef struct {\r
+ UINT32 Signature; // "PCIR"\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+ UINT16 Reserved0;\r
+ UINT16 Length;\r
+ UINT8 Revision;\r
+ UINT8 ClassCode[3];\r
+ UINT16 ImageLength;\r
+ UINT16 CodeRevision;\r
+ UINT8 CodeType;\r
+ UINT8 Indicator;\r
+ UINT16 Reserved1;\r
+} PCI_DATA_STRUCTURE;\r
+\r
+//\r
+// PCI Capability List IDs and records\r
+//\r
+#define EFI_PCI_CAPABILITY_ID_PMI 0x01\r
+#define EFI_PCI_CAPABILITY_ID_AGP 0x02\r
+#define EFI_PCI_CAPABILITY_ID_VPD 0x03\r
+#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r
+#define EFI_PCI_CAPABILITY_ID_MSI 0x05\r
+#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
+#define EFI_PCI_CAPABILITY_ID_PCIX 0x07\r
+\r
+typedef struct {\r
+ UINT8 CapabilityID;\r
+ UINT8 NextItemPtr;\r
+} EFI_PCI_CAPABILITY_HDR;\r
+\r
+//\r
+// Capability EFI_PCI_CAPABILITY_ID_PMI\r
+//\r
+typedef struct {\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT16 PMC;\r
+ UINT16 PMCSR;\r
+ UINT8 BridgeExtention;\r
+ UINT8 Data;\r
+} EFI_PCI_CAPABILITY_PMI;\r
+\r
+//\r
+// Capability EFI_PCI_CAPABILITY_ID_AGP\r
+//\r
+typedef struct {\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT8 Rev;\r
+ UINT8 Reserved;\r
+ UINT32 Status;\r
+ UINT32 Command;\r
+} EFI_PCI_CAPABILITY_AGP;\r
+\r
+//\r
+// Capability EFI_PCI_CAPABILITY_ID_VPD\r
+//\r
+typedef struct {\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT16 AddrReg;\r
+ UINT32 DataReg;\r
+} EFI_PCI_CAPABILITY_VPD;\r
+\r
+//\r
+// Capability EFI_PCI_CAPABILITY_ID_SLOTID\r
+//\r
+typedef struct {\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT8 ExpnsSlotReg;\r
+ UINT8 ChassisNo;\r
+} EFI_PCI_CAPABILITY_SLOTID;\r
+\r
+//\r
+// Capability EFI_PCI_CAPABILITY_ID_MSI\r
+//\r
+typedef struct {\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT16 MsgCtrlReg;\r
+ UINT32 MsgAddrReg;\r
+ UINT16 MsgDataReg;\r
+} EFI_PCI_CAPABILITY_MSI32;\r
+\r
+typedef struct {\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT16 MsgCtrlReg;\r
+ UINT32 MsgAddrRegLsdw;\r
+ UINT32 MsgAddrRegMsdw;\r
+ UINT16 MsgDataReg;\r
+} EFI_PCI_CAPABILITY_MSI64;\r
+\r
+//\r
+// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG\r
+//\r
+typedef struct {\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ //\r
+ // not finished - fields need to go here\r
+ //\r
+} EFI_PCI_CAPABILITY_HOTPLUG;\r
+\r
+//\r
+// Capability EFI_PCI_CAPABILITY_ID_PCIX\r
+//\r
+typedef struct {\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT16 CommandReg;\r
+ UINT32 StatusReg;\r
+} EFI_PCI_CAPABILITY_PCIX;\r
+\r
+typedef struct {\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT16 SecStatusReg;\r
+ UINT32 StatusReg;\r
+ UINT32 SplitTransCtrlRegUp;\r
+ UINT32 SplitTransCtrlRegDn;\r
+} EFI_PCI_CAPABILITY_PCIX_BRDG;\r
+\r
+#define DEVICE_ID_NOCARE 0xFFFF\r
+\r
+#define PCI_ACPI_UNUSED 0\r
+#define PCI_BAR_NOCHANGE 0\r
+#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL\r
+#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL\r
+#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL\r
+#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL\r
+\r
+#define PCI_BAR_IDX0 0x00\r
+#define PCI_BAR_IDX1 0x01\r
+#define PCI_BAR_IDX2 0x02\r
+#define PCI_BAR_IDX3 0x03\r
+#define PCI_BAR_IDX4 0x04\r
+#define PCI_BAR_IDX5 0x05\r
+#define PCI_BAR_ALL 0xFF\r
+\r
+#pragma pack(pop)\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Support for PCI 2.3 standard.\r
+\r
+ Copyright (c) 2006, Intel Corporation \r
+ All rights reserved. This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ Module Name: pci23.h\r
+\r
+**/\r
+\r
+#ifndef _PCI23_H\r
+#define _PCI23_H\r
+\r
+\r
+#define PCI_EXP_MAX_CONFIG_OFFSET 0x1000\r
+#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10\r
+\r
+#include <IndustryStandard/Pci22.h>\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Support for PCI 3.0 standard.\r
+\r
+ Copyright (c) 2006, Intel Corporation \r
+ All rights reserved. This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ Module Name: pci30.h\r
+\r
+**/\r
+\r
+#ifndef _PCI30_H\r
+#define _PCI30_H\r
+\r
+//#include "pci23.h"\r
+\r
+#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06\r
+\r
+#pragma pack(push, 1)\r
+\r
+typedef struct {\r
+ UINT32 Signature; // "PCIR"\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+ UINT16 DeviceListOffset;\r
+ UINT16 Length;\r
+ UINT8 Revision;\r
+ UINT8 ClassCode[3];\r
+ UINT16 ImageLength;\r
+ UINT16 CodeRevision;\r
+ UINT8 CodeType;\r
+ UINT8 Indicator;\r
+ UINT16 MaxRuntimeImageLength;\r
+ UINT16 ConfigUtilityCodeHeaderOffset;\r
+ UINT16 DMTFCLPEntryPointOffset;\r
+} PCI_3_0_DATA_STRUCTURE;\r
+\r
+#pragma pack(pop)\r
+\r
+\r
+#include <IndustryStandard/Pci23.h>\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ EFI image format for PE32 and PE32+. Please note some data structures are \r
+ different for PE32 and PE32+. EFI_IMAGE_NT_HEADERS32 is for PE32 and \r
+ EFI_IMAGE_NT_HEADERS64 is for PE32+. \r
+\r
+ This file is coded to the Visual Studio, Microsoft Portable Executable and \r
+ Common Object File Format Specification, Revision 8.0 - May 16, 2006. \r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ Module Name: PeImage.h\r
+\r
+**/\r
+\r
+#ifndef __EFI_IMAGE_H__\r
+#define __EFI_IMAGE_H__\r
+\r
+//\r
+// PE32+ Subsystem type for EFI images\r
+//\r
+#define EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION 10\r
+#define EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11\r
+#define EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12\r
+#define EFI_IMAGE_SUBSYSTEM_EFI_EFI_ROM 13\r
+\r
+#define EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER 13\r
+\r
+\r
+//\r
+// PE32+ Machine type for EFI images\r
+//\r
+#define IMAGE_FILE_MACHINE_I386 0x014c\r
+#define IMAGE_FILE_MACHINE_IA64 0x0200\r
+#define IMAGE_FILE_MACHINE_EBC 0x0EBC\r
+#define IMAGE_FILE_MACHINE_X64 0x8664\r
+//\r
+// Support old names for backward compatible\r
+//\r
+#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386 \r
+#define EFI_IMAGE_MACHINE_IA64 IMAGE_FILE_MACHINE_IA64 \r
+#define EFI_IMAGE_MACHINE_IPF IMAGE_FILE_MACHINE_IA64 \r
+#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC \r
+#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64\r
+\r
+#define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ\r
+#define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE\r
+#define EFI_IMAGE_OS2_SIGNATURE_LE 0x454C // LE\r
+#define EFI_IMAGE_NT_SIGNATURE 0x00004550 // PE00\r
+\r
+///\r
+/// PE images can start with an optional DOS header, so if an image is run\r
+/// under DOS it can print an error message.\r
+///\r
+typedef struct {\r
+ UINT16 e_magic; // Magic number\r
+ UINT16 e_cblp; // Bytes on last page of file\r
+ UINT16 e_cp; // Pages in file\r
+ UINT16 e_crlc; // Relocations\r
+ UINT16 e_cparhdr; // Size of header in paragraphs\r
+ UINT16 e_minalloc; // Minimum extra paragraphs needed\r
+ UINT16 e_maxalloc; // Maximum extra paragraphs needed\r
+ UINT16 e_ss; // Initial (relative) SS value\r
+ UINT16 e_sp; // Initial SP value\r
+ UINT16 e_csum; // Checksum\r
+ UINT16 e_ip; // Initial IP value\r
+ UINT16 e_cs; // Initial (relative) CS value\r
+ UINT16 e_lfarlc; // File address of relocation table\r
+ UINT16 e_ovno; // Overlay number\r
+ UINT16 e_res[4]; // Reserved words\r
+ UINT16 e_oemid; // OEM identifier (for e_oeminfo)\r
+ UINT16 e_oeminfo; // OEM information; e_oemid specific\r
+ UINT16 e_res2[10]; // Reserved words\r
+ UINT32 e_lfanew; // File address of new exe header\r
+} EFI_IMAGE_DOS_HEADER;\r
+\r
+///\r
+/// File header format.\r
+///\r
+typedef struct {\r
+ UINT16 Machine;\r
+ UINT16 NumberOfSections;\r
+ UINT32 TimeDateStamp;\r
+ UINT32 PointerToSymbolTable;\r
+ UINT32 NumberOfSymbols;\r
+ UINT16 SizeOfOptionalHeader;\r
+ UINT16 Characteristics;\r
+} EFI_IMAGE_FILE_HEADER;\r
+\r
+#define EFI_IMAGE_SIZEOF_FILE_HEADER 20\r
+\r
+#define EFI_IMAGE_FILE_RELOCS_STRIPPED 0x0001 // Relocation info stripped from file.\r
+#define EFI_IMAGE_FILE_EXECUTABLE_IMAGE 0x0002 // File is executable (i.e. no unresolved externel references).\r
+#define EFI_IMAGE_FILE_LINE_NUMS_STRIPPED 0x0004 // Line nunbers stripped from file.\r
+#define EFI_IMAGE_FILE_LOCAL_SYMS_STRIPPED 0x0008 // Local symbols stripped from file.\r
+#define EFI_IMAGE_FILE_BYTES_REVERSED_LO 0x0080 // Bytes of machine word are reversed.\r
+#define EFI_IMAGE_FILE_32BIT_MACHINE 0x0100 // 32 bit word machine.\r
+#define EFI_IMAGE_FILE_DEBUG_STRIPPED 0x0200 // Debugging info stripped from file in .DBG file\r
+#define EFI_IMAGE_FILE_SYSTEM 0x1000 // System File.\r
+#define EFI_IMAGE_FILE_DLL 0x2000 // File is a DLL.\r
+#define EFI_IMAGE_FILE_BYTES_REVERSED_HI 0x8000 // Bytes of machine word are reversed.\r
+#define EFI_IMAGE_FILE_MACHINE_UNKNOWN 0\r
+#define EFI_IMAGE_FILE_MACHINE_I386 0x14c // Intel 386.\r
+#define EFI_IMAGE_FILE_MACHINE_R3000 0x162 // MIPS* little-endian, 0540 big-endian\r
+#define EFI_IMAGE_FILE_MACHINE_R4000 0x166 // MIPS* little-endian\r
+#define EFI_IMAGE_FILE_MACHINE_ALPHA 0x184 // Alpha_AXP*\r
+#define EFI_IMAGE_FILE_MACHINE_POWERPC 0x1F0 // IBM* PowerPC Little-Endian\r
+#define EFI_IMAGE_FILE_MACHINE_TAHOE 0x7cc // Intel EM machine\r
+//\r
+// * Other names and brands may be claimed as the property of others.\r
+//\r
+\r
+///\r
+/// Directory format.\r
+///\r
+typedef struct {\r
+ UINT32 VirtualAddress;\r
+ UINT32 Size;\r
+} EFI_IMAGE_DATA_DIRECTORY;\r
+\r
+#define EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES 16\r
+\r
+typedef struct {\r
+ UINT16 Magic;\r
+ UINT8 MajorLinkerVersion;\r
+ UINT8 MinorLinkerVersion;\r
+ UINT32 SizeOfCode;\r
+ UINT32 SizeOfInitializedData;\r
+ UINT32 SizeOfUninitializedData;\r
+ UINT32 AddressOfEntryPoint;\r
+ UINT32 BaseOfCode;\r
+ UINT32 BaseOfData;\r
+ UINT32 BaseOfBss;\r
+ UINT32 GprMask;\r
+ UINT32 CprMask[4];\r
+ UINT32 GpValue;\r
+} EFI_IMAGE_ROM_OPTIONAL_HEADER;\r
+\r
+#define EFI_IMAGE_ROM_OPTIONAL_HDR_MAGIC 0x107\r
+#define EFI_IMAGE_SIZEOF_ROM_OPTIONAL_HEADER sizeof (EFI_IMAGE_ROM_OPTIONAL_HEADER)\r
+\r
+typedef struct {\r
+ EFI_IMAGE_FILE_HEADER FileHeader;\r
+ EFI_IMAGE_ROM_OPTIONAL_HEADER OptionalHeader;\r
+} EFI_IMAGE_ROM_HEADERS;\r
+\r
+///\r
+/// @attention\r
+/// EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC means PE32 and \r
+/// EFI_IMAGE_OPTIONAL_HEADER32 must be used. The data structures only vary\r
+/// after NT additional fields.\r
+///\r
+#define EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x10b\r
+\r
+typedef struct {\r
+ //\r
+ // Standard fields.\r
+ //\r
+ UINT16 Magic;\r
+ UINT8 MajorLinkerVersion;\r
+ UINT8 MinorLinkerVersion;\r
+ UINT32 SizeOfCode;\r
+ UINT32 SizeOfInitializedData;\r
+ UINT32 SizeOfUninitializedData;\r
+ UINT32 AddressOfEntryPoint;\r
+ UINT32 BaseOfCode;\r
+ UINT32 BaseOfData;\r
+ //\r
+ // NT additional fields.\r
+ //\r
+ UINT32 ImageBase;\r
+ UINT32 SectionAlignment;\r
+ UINT32 FileAlignment;\r
+ UINT16 MajorOperatingSystemVersion;\r
+ UINT16 MinorOperatingSystemVersion;\r
+ UINT16 MajorImageVersion;\r
+ UINT16 MinorImageVersion;\r
+ UINT16 MajorSubsystemVersion;\r
+ UINT16 MinorSubsystemVersion;\r
+ UINT32 Win32VersionValue;\r
+ UINT32 SizeOfImage;\r
+ UINT32 SizeOfHeaders;\r
+ UINT32 CheckSum;\r
+ UINT16 Subsystem;\r
+ UINT16 DllCharacteristics;\r
+ UINT32 SizeOfStackReserve;\r
+ UINT32 SizeOfStackCommit;\r
+ UINT32 SizeOfHeapReserve;\r
+ UINT32 SizeOfHeapCommit;\r
+ UINT32 LoaderFlags;\r
+ UINT32 NumberOfRvaAndSizes;\r
+ EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];\r
+} EFI_IMAGE_OPTIONAL_HEADER32;\r
+\r
+///\r
+/// @attention\r
+/// EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC means PE32+ and \r
+/// EFI_IMAGE_OPTIONAL_HEADER64 must be used. The data structures only vary\r
+/// after NT additional fields.\r
+///\r
+#define EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b\r
+\r
+typedef struct {\r
+ //\r
+ // Standard fields.\r
+ //\r
+ UINT16 Magic;\r
+ UINT8 MajorLinkerVersion;\r
+ UINT8 MinorLinkerVersion;\r
+ UINT32 SizeOfCode;\r
+ UINT32 SizeOfInitializedData;\r
+ UINT32 SizeOfUninitializedData;\r
+ UINT32 AddressOfEntryPoint;\r
+ UINT32 BaseOfCode;\r
+ //\r
+ // NT additional fields.\r
+ //\r
+ UINT64 ImageBase;\r
+ UINT32 SectionAlignment;\r
+ UINT32 FileAlignment;\r
+ UINT16 MajorOperatingSystemVersion;\r
+ UINT16 MinorOperatingSystemVersion;\r
+ UINT16 MajorImageVersion;\r
+ UINT16 MinorImageVersion;\r
+ UINT16 MajorSubsystemVersion;\r
+ UINT16 MinorSubsystemVersion;\r
+ UINT32 Win32VersionValue;\r
+ UINT32 SizeOfImage;\r
+ UINT32 SizeOfHeaders;\r
+ UINT32 CheckSum;\r
+ UINT16 Subsystem;\r
+ UINT16 DllCharacteristics;\r
+ UINT64 SizeOfStackReserve;\r
+ UINT64 SizeOfStackCommit;\r
+ UINT64 SizeOfHeapReserve;\r
+ UINT64 SizeOfHeapCommit;\r
+ UINT32 LoaderFlags;\r
+ UINT32 NumberOfRvaAndSizes;\r
+ EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];\r
+} EFI_IMAGE_OPTIONAL_HEADER64;\r
+\r
+\r
+///\r
+/// @attention\r
+/// EFI_IMAGE_NT_HEADERS32 and EFI_IMAGE_HEADERS64 are for use ONLY\r
+/// by tools. All proper EFI code MUST use EFI_IMAGE_NT_HEADERS ONLY!!!\r
+///\r
+typedef struct {\r
+ UINT32 Signature;\r
+ EFI_IMAGE_FILE_HEADER FileHeader;\r
+ EFI_IMAGE_OPTIONAL_HEADER32 OptionalHeader;\r
+} EFI_IMAGE_NT_HEADERS32;\r
+\r
+#define EFI_IMAGE_SIZEOF_NT_OPTIONAL32_HEADER sizeof (EFI_IMAGE_NT_HEADERS32)\r
+\r
+typedef struct {\r
+ UINT32 Signature;\r
+ EFI_IMAGE_FILE_HEADER FileHeader;\r
+ EFI_IMAGE_OPTIONAL_HEADER64 OptionalHeader;\r
+} EFI_IMAGE_NT_HEADERS64;\r
+\r
+#define EFI_IMAGE_SIZEOF_NT_OPTIONAL64_HEADER sizeof (EFI_IMAGE_NT_HEADERS64)\r
+\r
+\r
+//\r
+// Processor specific definition of EFI_IMAGE_OPTIONAL_HEADER so the\r
+// type name EFI_IMAGE_OPTIONAL_HEADER is appropriate to the build. Same for\r
+// EFI_IMAGE_NT_HEADERS. These definitions MUST be used by ALL EFI code.\r
+//\r
+#if defined (MDE_CPU_IA32)\r
+\r
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \\r
+ (((Machine) == EFI_IMAGE_MACHINE_IA32) || ((Machine) == EFI_IMAGE_MACHINE_EBC))\r
+\r
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_X64) \r
+\r
+//\r
+// @bug - Remove me when other package updated. \r
+//\r
+typedef EFI_IMAGE_NT_HEADERS32 EFI_IMAGE_NT_HEADERS;\r
+\r
+#elif defined (MDE_CPU_IPF)\r
+\r
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \\r
+ (((Machine) == EFI_IMAGE_MACHINE_IPF) || ((Machine) == EFI_IMAGE_MACHINE_EBC))\r
+\r
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) \r
+\r
+//\r
+// @bug - Remove me when other package updated. \r
+//\r
+typedef EFI_IMAGE_NT_HEADERS64 EFI_IMAGE_NT_HEADERS;\r
+\r
+#elif defined (MDE_CPU_X64)\r
+\r
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \\r
+ (((Machine) == EFI_IMAGE_MACHINE_X64) || ((Machine) == EFI_IMAGE_MACHINE_EBC))\r
+\r
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_IA32) \r
+\r
+//\r
+// @bug - Remove me when other package updated. \r
+//\r
+typedef EFI_IMAGE_NT_HEADERS32 EFI_IMAGE_NT_HEADERS;\r
+\r
+#elif defined (MDE_CPU_EBC)\r
+\r
+//\r
+// This is just to make sure you can cross compile with the EBC compiiler.\r
+// It does not make sense to have a PE loader coded in EBC. You need to \r
+// understand the basic \r
+//\r
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_EBC)\r
+\r
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) \r
+\r
+//\r
+// @bug - Remove me when other package updated. \r
+//\r
+typedef EFI_IMAGE_NT_HEADERS64 EFI_IMAGE_NT_HEADERS;\r
+\r
+#else\r
+#error Unknown Processor Type\r
+#endif\r
+\r
+\r
+#define EFI_IMAGE_FIRST_SECTION(ntheader) \\r
+ ( \\r
+ (EFI_IMAGE_SECTION_HEADER *) \\r
+ ( \\r
+ (UINT32) ntheader + \\r
+ FIELD_OFFSET (EFI_IMAGE_NT_HEADERS, OptionalHeader) + \\r
+ ((EFI_IMAGE_NT_HEADERS *) (ntheader))->FileHeader.SizeOfOptionalHeader \\r
+ ) \\r
+ )\r
+\r
+//\r
+// Subsystem Values\r
+//\r
+#define EFI_IMAGE_SUBSYSTEM_UNKNOWN 0\r
+#define EFI_IMAGE_SUBSYSTEM_NATIVE 1\r
+#define EFI_IMAGE_SUBSYSTEM_WINDOWS_GUI 2\r
+#define EFI_IMAGE_SUBSYSTEM_WINDOWS_CUI 3.\r
+#define EFI_IMAGE_SUBSYSTEM_OS2_CUI 5\r
+#define EFI_IMAGE_SUBSYSTEM_POSIX_CUI 7\r
+\r
+//\r
+// Directory Entries\r
+//\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_EXPORT 0\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_IMPORT 1\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE 2\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_EXCEPTION 3\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_SECURITY 4\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC 5\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_DEBUG 6\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_COPYRIGHT 7\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_GLOBALPTR 8\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_TLS 9\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG 10\r
+\r
+//\r
+// Section header format.\r
+//\r
+#define EFI_IMAGE_SIZEOF_SHORT_NAME 8\r
+\r
+typedef struct {\r
+ UINT8 Name[EFI_IMAGE_SIZEOF_SHORT_NAME];\r
+ union {\r
+ UINT32 PhysicalAddress;\r
+ UINT32 VirtualSize;\r
+ } Misc;\r
+ UINT32 VirtualAddress;\r
+ UINT32 SizeOfRawData;\r
+ UINT32 PointerToRawData;\r
+ UINT32 PointerToRelocations;\r
+ UINT32 PointerToLinenumbers;\r
+ UINT16 NumberOfRelocations;\r
+ UINT16 NumberOfLinenumbers;\r
+ UINT32 Characteristics;\r
+} EFI_IMAGE_SECTION_HEADER;\r
+\r
+#define EFI_IMAGE_SIZEOF_SECTION_HEADER 40\r
+\r
+#define EFI_IMAGE_SCN_TYPE_NO_PAD 0x00000008 // Reserved.\r
+#define EFI_IMAGE_SCN_CNT_CODE 0x00000020\r
+#define EFI_IMAGE_SCN_CNT_INITIALIZED_DATA 0x00000040\r
+#define EFI_IMAGE_SCN_CNT_UNINITIALIZED_DATA 0x00000080\r
+\r
+#define EFI_IMAGE_SCN_LNK_OTHER 0x00000100 // Reserved.\r
+#define EFI_IMAGE_SCN_LNK_INFO 0x00000200 // Section contains comments or some other type of information.\r
+#define EFI_IMAGE_SCN_LNK_REMOVE 0x00000800 // Section contents will not become part of image.\r
+#define EFI_IMAGE_SCN_LNK_COMDAT 0x00001000\r
+\r
+#define EFI_IMAGE_SCN_ALIGN_1BYTES 0x00100000\r
+#define EFI_IMAGE_SCN_ALIGN_2BYTES 0x00200000\r
+#define EFI_IMAGE_SCN_ALIGN_4BYTES 0x00300000\r
+#define EFI_IMAGE_SCN_ALIGN_8BYTES 0x00400000\r
+#define EFI_IMAGE_SCN_ALIGN_16BYTES 0x00500000\r
+#define EFI_IMAGE_SCN_ALIGN_32BYTES 0x00600000\r
+#define EFI_IMAGE_SCN_ALIGN_64BYTES 0x00700000\r
+\r
+#define EFI_IMAGE_SCN_MEM_DISCARDABLE 0x02000000\r
+#define EFI_IMAGE_SCN_MEM_NOT_CACHED 0x04000000\r
+#define EFI_IMAGE_SCN_MEM_NOT_PAGED 0x08000000\r
+#define EFI_IMAGE_SCN_MEM_SHARED 0x10000000\r
+#define EFI_IMAGE_SCN_MEM_EXECUTE 0x20000000\r
+#define EFI_IMAGE_SCN_MEM_READ 0x40000000\r
+#define EFI_IMAGE_SCN_MEM_WRITE 0x80000000\r
+\r
+///\r
+/// Symbol format.\r
+///\r
+#define EFI_IMAGE_SIZEOF_SYMBOL 18\r
+\r
+//\r
+// Section values.\r
+//\r
+// Symbols have a section number of the section in which they are\r
+// defined. Otherwise, section numbers have the following meanings:\r
+//\r
+#define EFI_IMAGE_SYM_UNDEFINED (UINT16) 0 // Symbol is undefined or is common.\r
+#define EFI_IMAGE_SYM_ABSOLUTE (UINT16) -1 // Symbol is an absolute value.\r
+#define EFI_IMAGE_SYM_DEBUG (UINT16) -2 // Symbol is a special debug item.\r
+//\r
+// Type (fundamental) values.\r
+//\r
+#define EFI_IMAGE_SYM_TYPE_NULL 0 // no type.\r
+#define EFI_IMAGE_SYM_TYPE_VOID 1 //\r
+#define EFI_IMAGE_SYM_TYPE_CHAR 2 // type character.\r
+#define EFI_IMAGE_SYM_TYPE_SHORT 3 // type short integer.\r
+#define EFI_IMAGE_SYM_TYPE_INT 4\r
+#define EFI_IMAGE_SYM_TYPE_LONG 5\r
+#define EFI_IMAGE_SYM_TYPE_FLOAT 6\r
+#define EFI_IMAGE_SYM_TYPE_DOUBLE 7\r
+#define EFI_IMAGE_SYM_TYPE_STRUCT 8\r
+#define EFI_IMAGE_SYM_TYPE_UNION 9\r
+#define EFI_IMAGE_SYM_TYPE_ENUM 10 // enumeration.\r
+#define EFI_IMAGE_SYM_TYPE_MOE 11 // member of enumeration.\r
+#define EFI_IMAGE_SYM_TYPE_BYTE 12\r
+#define EFI_IMAGE_SYM_TYPE_WORD 13\r
+#define EFI_IMAGE_SYM_TYPE_UINT 14\r
+#define EFI_IMAGE_SYM_TYPE_DWORD 15\r
+\r
+//\r
+// Type (derived) values.\r
+//\r
+#define EFI_IMAGE_SYM_DTYPE_NULL 0 // no derived type.\r
+#define EFI_IMAGE_SYM_DTYPE_POINTER 1\r
+#define EFI_IMAGE_SYM_DTYPE_FUNCTION 2\r
+#define EFI_IMAGE_SYM_DTYPE_ARRAY 3\r
+\r
+//\r
+// Storage classes.\r
+//\r
+#define EFI_IMAGE_SYM_CLASS_END_OF_FUNCTION (UINT8) -1\r
+#define EFI_IMAGE_SYM_CLASS_NULL 0\r
+#define EFI_IMAGE_SYM_CLASS_AUTOMATIC 1\r
+#define EFI_IMAGE_SYM_CLASS_EXTERNAL 2\r
+#define EFI_IMAGE_SYM_CLASS_STATIC 3\r
+#define EFI_IMAGE_SYM_CLASS_REGISTER 4\r
+#define EFI_IMAGE_SYM_CLASS_EXTERNAL_DEF 5\r
+#define EFI_IMAGE_SYM_CLASS_LABEL 6\r
+#define EFI_IMAGE_SYM_CLASS_UNDEFINED_LABEL 7\r
+#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_STRUCT 8\r
+#define EFI_IMAGE_SYM_CLASS_ARGUMENT 9\r
+#define EFI_IMAGE_SYM_CLASS_STRUCT_TAG 10\r
+#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_UNION 11\r
+#define EFI_IMAGE_SYM_CLASS_UNION_TAG 12\r
+#define EFI_IMAGE_SYM_CLASS_TYPE_DEFINITION 13\r
+#define EFI_IMAGE_SYM_CLASS_UNDEFINED_STATIC 14\r
+#define EFI_IMAGE_SYM_CLASS_ENUM_TAG 15\r
+#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_ENUM 16\r
+#define EFI_IMAGE_SYM_CLASS_REGISTER_PARAM 17\r
+#define EFI_IMAGE_SYM_CLASS_BIT_FIELD 18\r
+#define EFI_IMAGE_SYM_CLASS_BLOCK 100\r
+#define EFI_IMAGE_SYM_CLASS_FUNCTION 101\r
+#define EFI_IMAGE_SYM_CLASS_END_OF_STRUCT 102\r
+#define EFI_IMAGE_SYM_CLASS_FILE 103\r
+#define EFI_IMAGE_SYM_CLASS_SECTION 104\r
+#define EFI_IMAGE_SYM_CLASS_WEAK_EXTERNAL 105\r
+\r
+//\r
+// type packing constants\r
+//\r
+#define EFI_IMAGE_N_BTMASK 017\r
+#define EFI_IMAGE_N_TMASK 060\r
+#define EFI_IMAGE_N_TMASK1 0300\r
+#define EFI_IMAGE_N_TMASK2 0360\r
+#define EFI_IMAGE_N_BTSHFT 4\r
+#define EFI_IMAGE_N_TSHIFT 2\r
+\r
+//\r
+// Communal selection types.\r
+//\r
+#define EFI_IMAGE_COMDAT_SELECT_NODUPLICATES 1\r
+#define EFI_IMAGE_COMDAT_SELECT_ANY 2\r
+#define EFI_IMAGE_COMDAT_SELECT_SAME_SIZE 3\r
+#define EFI_IMAGE_COMDAT_SELECT_EXACT_MATCH 4\r
+#define EFI_IMAGE_COMDAT_SELECT_ASSOCIATIVE 5\r
+\r
+#define EFI_IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY 1\r
+#define EFI_IMAGE_WEAK_EXTERN_SEARCH_LIBRARY 2\r
+#define EFI_IMAGE_WEAK_EXTERN_SEARCH_ALIAS 3\r
+\r
+///\r
+/// Relocation format.\r
+///\r
+typedef struct {\r
+ UINT32 VirtualAddress;\r
+ UINT32 SymbolTableIndex;\r
+ UINT16 Type;\r
+} EFI_IMAGE_RELOCATION;\r
+\r
+#define EFI_IMAGE_SIZEOF_RELOCATION 10\r
+\r
+//\r
+// I386 relocation types.\r
+//\r
+#define EFI_IMAGE_REL_I386_ABSOLUTE 0x0000 // Reference is absolute, no relocation is necessary\r
+#define EFI_IMAGE_REL_I386_DIR16 0x0001 // Direct 16-bit reference to the symbols virtual address\r
+#define EFI_IMAGE_REL_I386_REL16 0x0002 // PC-relative 16-bit reference to the symbols virtual address\r
+#define EFI_IMAGE_REL_I386_DIR32 0x0006 // Direct 32-bit reference to the symbols virtual address\r
+#define EFI_IMAGE_REL_I386_DIR32NB 0x0007 // Direct 32-bit reference to the symbols virtual address, base not included\r
+#define EFI_IMAGE_REL_I386_SEG12 0x0009 // Direct 16-bit reference to the segment-selector bits of a 32-bit virtual address\r
+#define EFI_IMAGE_REL_I386_SECTION 0x001a\r
+#define EFI_IMAGE_REL_I386_SECREL 0x000b\r
+#define EFI_IMAGE_REL_I386_REL32 0x0014 // PC-relative 32-bit reference to the symbols virtual address\r
+\r
+//\r
+// x64 processor relocation types.\r
+//\r
+#define IMAGE_REL_AMD64_ABSOLUTE 0x0000\r
+#define IMAGE_REL_AMD64_ADDR64 0x0001\r
+#define IMAGE_REL_AMD64_ADDR32 0x0002\r
+#define IMAGE_REL_AMD64_ADDR32NB 0x0003\r
+#define IMAGE_REL_AMD64_REL32 0x0004\r
+#define IMAGE_REL_AMD64_REL32_1 0x0005\r
+#define IMAGE_REL_AMD64_REL32_2 0x0006\r
+#define IMAGE_REL_AMD64_REL32_3 0x0007\r
+#define IMAGE_REL_AMD64_REL32_4 0x0008\r
+#define IMAGE_REL_AMD64_REL32_5 0x0009\r
+#define IMAGE_REL_AMD64_SECTION 0x000A\r
+#define IMAGE_REL_AMD64_SECREL 0x000B\r
+#define IMAGE_REL_AMD64_SECREL7 0x000C\r
+#define IMAGE_REL_AMD64_TOKEN 0x000D\r
+#define IMAGE_REL_AMD64_SREL32 0x000E\r
+#define IMAGE_REL_AMD64_PAIR 0x000F\r
+#define IMAGE_REL_AMD64_SSPAN32 0x0010\r
+\r
+///\r
+/// Based relocation format.\r
+///\r
+typedef struct {\r
+ UINT32 VirtualAddress;\r
+ UINT32 SizeOfBlock;\r
+} EFI_IMAGE_BASE_RELOCATION;\r
+\r
+#define EFI_IMAGE_SIZEOF_BASE_RELOCATION 8\r
+\r
+//\r
+// Based relocation types.\r
+//\r
+#define EFI_IMAGE_REL_BASED_ABSOLUTE 0\r
+#define EFI_IMAGE_REL_BASED_HIGH 1\r
+#define EFI_IMAGE_REL_BASED_LOW 2\r
+#define EFI_IMAGE_REL_BASED_HIGHLOW 3\r
+#define EFI_IMAGE_REL_BASED_HIGHADJ 4\r
+#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5\r
+#define EFI_IMAGE_REL_BASED_IA64_IMM64 9\r
+#define EFI_IMAGE_REL_BASED_DIR64 10\r
+\r
+///\r
+/// Line number format.\r
+///\r
+typedef struct {\r
+ union {\r
+ UINT32 SymbolTableIndex; // Symbol table index of function name if Linenumber is 0.\r
+ UINT32 VirtualAddress; // Virtual address of line number.\r
+ } Type;\r
+ UINT16 Linenumber; // Line number.\r
+} EFI_IMAGE_LINENUMBER;\r
+\r
+#define EFI_IMAGE_SIZEOF_LINENUMBER 6\r
+\r
+//\r
+// Archive format.\r
+//\r
+#define EFI_IMAGE_ARCHIVE_START_SIZE 8\r
+#define EFI_IMAGE_ARCHIVE_START "!<arch>\n"\r
+#define EFI_IMAGE_ARCHIVE_END "`\n"\r
+#define EFI_IMAGE_ARCHIVE_PAD "\n"\r
+#define EFI_IMAGE_ARCHIVE_LINKER_MEMBER "/ "\r
+#define EFI_IMAGE_ARCHIVE_LONGNAMES_MEMBER "// "\r
+\r
+typedef struct {\r
+ UINT8 Name[16]; // File member name - `/' terminated.\r
+ UINT8 Date[12]; // File member date - decimal.\r
+ UINT8 UserID[6]; // File member user id - decimal.\r
+ UINT8 GroupID[6]; // File member group id - decimal.\r
+ UINT8 Mode[8]; // File member mode - octal.\r
+ UINT8 Size[10]; // File member size - decimal.\r
+ UINT8 EndHeader[2]; // String to end header.\r
+} EFI_IMAGE_ARCHIVE_MEMBER_HEADER;\r
+\r
+#define EFI_IMAGE_SIZEOF_ARCHIVE_MEMBER_HDR 60\r
+\r
+//\r
+// DLL support.\r
+//\r
+\r
+///\r
+/// DLL Export Format\r
+///\r
+typedef struct {\r
+ UINT32 Characteristics;\r
+ UINT32 TimeDateStamp;\r
+ UINT16 MajorVersion;\r
+ UINT16 MinorVersion;\r
+ UINT32 Name;\r
+ UINT32 Base;\r
+ UINT32 NumberOfFunctions;\r
+ UINT32 NumberOfNames;\r
+ UINT32 AddressOfFunctions;\r
+ UINT32 AddressOfNames;\r
+ UINT32 AddressOfNameOrdinals;\r
+} EFI_IMAGE_EXPORT_DIRECTORY;\r
+\r
+///\r
+/// DLL support.\r
+/// Import Format\r
+///\r
+typedef struct {\r
+ UINT16 Hint;\r
+ UINT8 Name[1];\r
+} EFI_IMAGE_IMPORT_BY_NAME;\r
+\r
+typedef struct {\r
+ union {\r
+ UINT32 Function;\r
+ UINT32 Ordinal;\r
+ EFI_IMAGE_IMPORT_BY_NAME *AddressOfData;\r
+ } u1;\r
+} EFI_IMAGE_THUNK_DATA;\r
+\r
+#define EFI_IMAGE_ORDINAL_FLAG 0x80000000\r
+#define EFI_IMAGE_SNAP_BY_ORDINAL(Ordinal) ((Ordinal & EFI_IMAGE_ORDINAL_FLAG) != 0)\r
+#define EFI_IMAGE_ORDINAL(Ordinal) (Ordinal & 0xffff)\r
+\r
+typedef struct {\r
+ UINT32 Characteristics;\r
+ UINT32 TimeDateStamp;\r
+ UINT32 ForwarderChain;\r
+ UINT32 Name;\r
+ EFI_IMAGE_THUNK_DATA *FirstThunk;\r
+} EFI_IMAGE_IMPORT_DESCRIPTOR;\r
+\r
+///\r
+/// Debug Format\r
+///\r
+#define EFI_IMAGE_DEBUG_TYPE_CODEVIEW 2\r
+\r
+typedef struct {\r
+ UINT32 Characteristics;\r
+ UINT32 TimeDateStamp;\r
+ UINT16 MajorVersion;\r
+ UINT16 MinorVersion;\r
+ UINT32 Type;\r
+ UINT32 SizeOfData;\r
+ UINT32 RVA;\r
+ UINT32 FileOffset;\r
+} EFI_IMAGE_DEBUG_DIRECTORY_ENTRY;\r
+\r
+#define CODEVIEW_SIGNATURE_NB10 0x3031424E // "NB10"\r
+typedef struct {\r
+ UINT32 Signature; // "NB10"\r
+ UINT32 Unknown;\r
+ UINT32 Unknown2;\r
+ UINT32 Unknown3;\r
+ //\r
+ // Filename of .PDB goes here\r
+ //\r
+} EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY;\r
+\r
+#define CODEVIEW_SIGNATURE_RSDS 0x53445352 // "RSDS"\r
+typedef struct {\r
+ UINT32 Signature; // "RSDS"\r
+ UINT32 Unknown;\r
+ UINT32 Unknown2;\r
+ UINT32 Unknown3;\r
+ UINT32 Unknown4;\r
+ UINT32 Unknown5;\r
+ //\r
+ // Filename of .PDB goes here\r
+ //\r
+} EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY;\r
+\r
+///\r
+/// Header format for TE images\r
+///\r
+typedef struct {\r
+ UINT16 Signature; // signature for TE format = "VZ"\r
+ UINT16 Machine; // from the original file header\r
+ UINT8 NumberOfSections; // from the original file header\r
+ UINT8 Subsystem; // from original optional header\r
+ UINT16 StrippedSize; // how many bytes we removed from the header\r
+ UINT32 AddressOfEntryPoint; // offset to entry point -- from original optional header\r
+ UINT32 BaseOfCode; // from original image -- required for ITP debug\r
+ UINT64 ImageBase; // from original file header\r
+ EFI_IMAGE_DATA_DIRECTORY DataDirectory[2]; // only base relocation and debug directory\r
+} EFI_TE_IMAGE_HEADER;\r
+\r
+#define EFI_TE_IMAGE_HEADER_SIGNATURE 0x5A56 // "VZ"\r
+\r
+//\r
+// Data directory indexes in our TE image header\r
+//\r
+#define EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC 0\r
+#define EFI_TE_IMAGE_DIRECTORY_ENTRY_DEBUG 1\r
+\r
+\r
+//\r
+// Union of PE32, PE32+, and TE headers\r
+//\r
+typedef union {\r
+ EFI_IMAGE_NT_HEADERS32 Pe32;\r
+ EFI_IMAGE_NT_HEADERS64 Pe32Plus;\r
+ EFI_TE_IMAGE_HEADER Te;\r
+} EFI_IMAGE_OPTIONAL_HEADER_UNION;\r
+\r
+typedef union {\r
+ EFI_IMAGE_NT_HEADERS32 *Pe32;\r
+ EFI_IMAGE_NT_HEADERS64 *Pe32Plus;\r
+ EFI_TE_IMAGE_HEADER *Te;\r
+ EFI_IMAGE_OPTIONAL_HEADER_UNION *Union;\r
+} EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ support for SCSI-2 standard\r
+\r
+ Copyright (c) 2006, Intel Corporation \r
+ All rights reserved. This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ Module Name: scsi.h\r
+\r
+**/\r
+\r
+#ifndef _SCSI_H\r
+#define _SCSI_H\r
+\r
+//\r
+// SCSI command OP Code\r
+//\r
+//\r
+// Commands for all device types\r
+//\r
+#define EFI_SCSI_OP_CHANGE_DEFINITION 0x40\r
+#define EFI_SCSI_OP_COMPARE 0x39\r
+#define EFI_SCSI_OP_COPY 0x18\r
+#define EFI_SCSI_OP_COPY_VERIFY 0x3a\r
+#define EFI_SCSI_OP_INQUIRY 0x12\r
+#define EFI_SCSI_OP_LOG_SELECT 0x4c\r
+#define EFI_SCSI_OP_LOG_SENSE 0x4d\r
+#define EFI_SCSI_OP_MODE_SEL6 0x15\r
+#define EFI_SCSI_OP_MODE_SEL10 0x55\r
+#define EFI_SCSI_OP_MODE_SEN6 0x1a\r
+#define EFI_SCSI_OP_MODE_SEN10 0x5a\r
+#define EFI_SCSI_OP_READ_BUFFER 0x3c\r
+#define EFI_SCSI_OP_REQUEST_SENSE 0x03\r
+#define EFI_SCSI_OP_SEND_DIAG 0x1d\r
+#define EFI_SCSI_OP_TEST_UNIT_READY 0x00\r
+#define EFI_SCSI_OP_WRITE_BUFF 0x3b\r
+\r
+//\r
+// Commands unique to Direct Access Devices\r
+//\r
+#define EFI_SCSI_OP_COMPARE 0x39\r
+#define EFI_SCSI_OP_FORMAT 0x04\r
+#define EFI_SCSI_OP_LOCK_UN_CACHE 0x36\r
+#define EFI_SCSI_OP_PREFETCH 0x34\r
+#define EFI_SCSI_OP_MEDIA_REMOVAL 0x1e\r
+#define EFI_SCSI_OP_READ6 0x08\r
+#define EFI_SCSI_OP_READ10 0x28\r
+#define EFI_SCSI_OP_READ_CAPACITY 0x25\r
+#define EFI_SCSI_OP_READ_DEFECT 0x37\r
+#define EFI_SCSI_OP_READ_LONG 0x3e\r
+#define EFI_SCSI_OP_REASSIGN_BLK 0x07\r
+#define EFI_SCSI_OP_RECEIVE_DIAG 0x1c\r
+#define EFI_SCSI_OP_RELEASE 0x17\r
+#define EFI_SCSI_OP_REZERO 0x01\r
+#define EFI_SCSI_OP_SEARCH_DATA_E 0x31\r
+#define EFI_SCSI_OP_SEARCH_DATA_H 0x30\r
+#define EFI_SCSI_OP_SEARCH_DATA_L 0x32\r
+#define EFI_SCSI_OP_SEEK6 0x0b\r
+#define EFI_SCSI_OP_SEEK10 0x2b\r
+#define EFI_SCSI_OP_SEND_DIAG 0x1d\r
+#define EFI_SCSI_OP_SET_LIMIT 0x33\r
+#define EFI_SCSI_OP_START_STOP_UNIT 0x1b\r
+#define EFI_SCSI_OP_SYNC_CACHE 0x35\r
+#define EFI_SCSI_OP_VERIFY 0x2f\r
+#define EFI_SCSI_OP_WRITE6 0x0a\r
+#define EFI_SCSI_OP_WRITE10 0x2a\r
+#define EFI_SCSI_OP_WRITE_VERIFY 0x2e\r
+#define EFI_SCSI_OP_WRITE_LONG 0x3f\r
+#define EFI_SCSI_OP_WRITE_SAME 0x41\r
+\r
+//\r
+// Commands unique to Sequential Access Devices\r
+//\r
+#define EFI_SCSI_OP_ERASE 0x19\r
+#define EFI_SCSI_OP_LOAD_UNLOAD 0x1b\r
+#define EFI_SCSI_OP_LOCATE 0x2b\r
+#define EFI_SCSI_OP_READ_BLOCK_LIMIT 0x05\r
+#define EFI_SCSI_OP_READ_POS 0x34\r
+#define EFI_SCSI_OP_READ_REVERSE 0x0f\r
+#define EFI_SCSI_OP_RECOVER_BUF_DATA 0x14\r
+#define EFI_SCSI_OP_RESERVE_UNIT 0x16\r
+#define EFI_SCSI_OP_REWIND 0x01\r
+#define EFI_SCSI_OP_SPACE 0x11\r
+#define EFI_SCSI_OP_VERIFY_TAPE 0x13\r
+#define EFI_SCSI_OP_WRITE_FILEMARK 0x10\r
+\r
+//\r
+// Commands unique to Printer Devices\r
+//\r
+#define EFI_SCSI_OP_PRINT 0x0a\r
+#define EFI_SCSI_OP_SLEW_PRINT 0x0b\r
+#define EFI_SCSI_OP_STOP_PRINT 0x1b\r
+#define EFI_SCSI_OP_SYNC_BUFF 0x10\r
+\r
+//\r
+// Commands unique to Processor Devices\r
+//\r
+#define EFI_SCSI_OP_RECEIVE 0x08\r
+#define EFI_SCSI_OP_SEND 0x0a\r
+\r
+//\r
+// Commands unique to Write-Once Devices\r
+//\r
+#define EFI_SCSI_OP_MEDIUM_SCAN 0x38\r
+#define EFI_SCSI_OP_SEARCH_DAT_E10 0x31\r
+#define EFI_SCSI_OP_SEARCH_DAT_E12 0xb1\r
+#define EFI_SCSI_OP_SEARCH_DAT_H10 0x30\r
+#define EFI_SCSI_OP_SEARCH_DAT_H12 0xb0\r
+#define EFI_SCSI_OP_SEARCH_DAT_L10 0x32\r
+#define EFI_SCSI_OP_SEARCH_DAT_L12 0xb2\r
+#define EFI_SCSI_OP_SET_LIMIT10 0x33\r
+#define EFI_SCSI_OP_SET_LIMIT12 0xb3\r
+#define EFI_SCSI_OP_VERIFY10 0x2f\r
+#define EFI_SCSI_OP_VERIFY12 0xaf\r
+#define EFI_SCSI_OP_WRITE12 0xaa\r
+#define EFI_SCSI_OP_WRITE_VERIFY10 0x2e\r
+#define EFI_SCSI_OP_WRITE_VERIFY12 0xae\r
+\r
+//\r
+// Commands unique to CD-ROM Devices\r
+//\r
+#define EFI_SCSI_OP_PLAY_AUD_10 0x45\r
+#define EFI_SCSI_OP_PLAY_AUD_12 0xa5\r
+#define EFI_SCSI_OP_PLAY_AUD_MSF 0x47\r
+#define EFI_SCSI_OP_PLAY_AUD_TKIN 0x48\r
+#define EFI_SCSI_OP_PLAY_TK_REL10 0x49\r
+#define EFI_SCSI_OP_PLAY_TK_REL12 0xa9\r
+#define EFI_SCSI_OP_READ_CD_CAPACITY 0x25\r
+#define EFI_SCSI_OP_READ_HEADER 0x44\r
+#define EFI_SCSI_OP_READ_SUB_CHANNEL 0x42\r
+#define EFI_SCSI_OP_READ_TOC 0x43\r
+\r
+//\r
+// Commands unique to Scanner Devices\r
+//\r
+#define EFI_SCSI_OP_GET_DATABUFF_STAT 0x34\r
+#define EFI_SCSI_OP_GET_WINDOW 0x25\r
+#define EFI_SCSI_OP_OBJECT_POS 0x31\r
+#define EFI_SCSI_OP_SCAN 0x1b\r
+#define EFI_SCSI_OP_SET_WINDOW 0x24\r
+\r
+//\r
+// Commands unique to Optical Memory Devices\r
+//\r
+#define EFI_SCSI_OP_UPDATE_BLOCK 0x3d\r
+\r
+//\r
+// Commands unique to Medium Changer Devices\r
+//\r
+#define EFI_SCSI_OP_EXCHANGE_MEDIUM 0xa6\r
+#define EFI_SCSI_OP_INIT_ELEMENT_STAT 0x07\r
+#define EFI_SCSI_OP_POS_TO_ELEMENT 0x2b\r
+#define EFI_SCSI_OP_REQUEST_VE_ADDR 0xb5\r
+#define EFI_SCSI_OP_SEND_VOL_TAG 0xb6\r
+\r
+//\r
+// Commands unique to Communition Devices\r
+//\r
+#define EFI_SCSI_OP_GET_MESSAGE6 0x08\r
+#define EFI_SCSI_OP_GET_MESSAGE10 0x28\r
+#define EFI_SCSI_OP_GET_MESSAGE12 0xa8\r
+#define EFI_SCSI_OP_SEND_MESSAGE6 0x0a\r
+#define EFI_SCSI_OP_SEND_MESSAGE10 0x2a\r
+#define EFI_SCSI_OP_SEND_MESSAGE12 0xaa\r
+\r
+//\r
+// SCSI Data Transfer Direction\r
+//\r
+#define EFI_SCSI_DATA_IN 0\r
+#define EFI_SCSI_DATA_OUT 1\r
+\r
+//\r
+// Peripheral Device Type Definitions\r
+//\r
+#define EFI_SCSI_TYPE_DISK 0x00 // Disk device\r
+#define EFI_SCSI_TYPE_TAPE 0x01 // Tape device\r
+#define EFI_SCSI_TYPE_PRINTER 0x02 // Printer\r
+#define EFI_SCSI_TYPE_PROCESSOR 0x03 // Processor\r
+#define EFI_SCSI_TYPE_WORM 0x04 // Write-once read-multiple\r
+#define EFI_SCSI_TYPE_CDROM 0x05 // CD-ROM device\r
+#define EFI_SCSI_TYPE_SCANNER 0x06 // Scanner device\r
+#define EFI_SCSI_TYPE_OPTICAL 0x07 // Optical memory device\r
+#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08 // Medium Changer device\r
+#define EFI_SCSI_TYPE_COMMUNICATION 0x09 // Communications device\r
+#define EFI_SCSI_TYPE_RESERVED_LOW 0x0A // Reserved (low)\r
+#define EFI_SCSI_TYPE_RESERVED_HIGH 0x1E // Reserved (high)\r
+#define EFI_SCSI_TYPE_UNKNOWN 0x1F // Unknown or no device type\r
+#pragma pack(1)\r
+//\r
+// Data structures for scsi command use\r
+//\r
+typedef struct {\r
+ UINT8 Peripheral_Type : 5;\r
+ UINT8 Peripheral_Qualifier : 3;\r
+ UINT8 DeviceType_Modifier : 7;\r
+ UINT8 RMB : 1;\r
+ UINT8 Version;\r
+ UINT8 Response_Data_Format;\r
+ UINT8 Addnl_Length;\r
+ UINT8 Reserved_5_95[95 - 5 + 1];\r
+} EFI_SCSI_INQUIRY_DATA;\r
+\r
+typedef struct {\r
+ UINT8 Error_Code : 7;\r
+ UINT8 Valid : 1;\r
+ UINT8 Segment_Number;\r
+ UINT8 Sense_Key : 4;\r
+ UINT8 Reserved_21 : 1;\r
+ UINT8 ILI : 1;\r
+ UINT8 Reserved_22 : 2;\r
+ UINT8 Information_3_6[4];\r
+ UINT8 Addnl_Sense_Length; // n - 7\r
+ UINT8 Vendor_Specific_8_11[4];\r
+ UINT8 Addnl_Sense_Code; // mandatory\r
+ UINT8 Addnl_Sense_Code_Qualifier; // mandatory\r
+ UINT8 Field_Replaceable_Unit_Code; // optional\r
+ UINT8 Reserved_15_17[3];\r
+} EFI_SCSI_SENSE_DATA;\r
+\r
+typedef struct {\r
+ UINT8 LastLba3;\r
+ UINT8 LastLba2;\r
+ UINT8 LastLba1;\r
+ UINT8 LastLba0;\r
+ UINT8 BlockSize3;\r
+ UINT8 BlockSize2;\r
+ UINT8 BlockSize1;\r
+ UINT8 BlockSize0;\r
+} EFI_SCSI_DISK_CAPACITY_DATA;\r
+\r
+#pragma pack()\r
+//\r
+// Sense Key\r
+//\r
+#define EFI_SCSI_REQUEST_SENSE_ERROR (0x70)\r
+#define EFI_SCSI_SK_NO_SENSE (0x0)\r
+#define EFI_SCSI_SK_RECOVERY_ERROR (0x1)\r
+#define EFI_SCSI_SK_NOT_READY (0x2)\r
+#define EFI_SCSI_SK_MEDIUM_ERROR (0x3)\r
+#define EFI_SCSI_SK_HARDWARE_ERROR (0x4)\r
+#define EFI_SCSI_SK_ILLEGAL_REQUEST (0x5)\r
+#define EFI_SCSI_SK_UNIT_ATTENTION (0x6)\r
+#define EFI_SCSI_SK_DATA_PROTECT (0x7)\r
+#define EFI_SCSI_SK_BLANK_CHECK (0x8)\r
+#define EFI_SCSI_SK_VENDOR_SPECIFIC (0x9)\r
+#define EFI_SCSI_SK_RESERVED_A (0xA)\r
+#define EFI_SCSI_SK_ABORT (0xB)\r
+#define EFI_SCSI_SK_RESERVED_C (0xC)\r
+#define EFI_SCSI_SK_OVERFLOW (0xD)\r
+#define EFI_SCSI_SK_MISCOMPARE (0xE)\r
+#define EFI_SCSI_SK_RESERVED_F (0xF)\r
+\r
+//\r
+// Additional Sense Codes\r
+//\r
+#define EFI_SCSI_ASC_NOT_READY (0x04)\r
+#define EFI_SCSI_ASC_MEDIA_ERR1 (0x10)\r
+#define EFI_SCSI_ASC_MEDIA_ERR2 (0x11)\r
+#define EFI_SCSI_ASC_MEDIA_ERR3 (0x14)\r
+#define EFI_SCSI_ASC_MEDIA_ERR4 (0x30)\r
+#define EFI_SCSI_ASC_MEDIA_UPSIDE_DOWN (0x06)\r
+#define EFI_SCSI_ASC_INVALID_CMD (0x20)\r
+#define EFI_SCSI_ASC_LBA_OUT_OF_RANGE (0x21)\r
+#define EFI_SCSI_ASC_INVALID_FIELD (0x24)\r
+#define EFI_SCSI_ASC_WRITE_PROTECTED (0x27)\r
+#define EFI_SCSI_ASC_MEDIA_CHANGE (0x28)\r
+#define EFI_SCSI_ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */\r
+#define EFI_SCSI_ASC_ILLEGAL_FIELD (0x26)\r
+#define EFI_SCSI_ASC_NO_MEDIA (0x3A)\r
+#define EFI_SCSI_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)\r
+\r
+//\r
+// Additional Sense Code Qualifier\r
+//\r
+#define EFI_SCSI_ASCQ_IN_PROGRESS (0x01)\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Industry Standard Definitions of SMBIOS tables.\r
+\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation All rights\r
+ reserved. This program and the accompanying materials are\r
+ licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ Module Name: SmBios.h\r
+\r
+ @par Revision Reference: SMBIOS 2.0\r
+ \r
+**/\r
+\r
+#ifndef __SMBIOS_STANDARD_H__\r
+#define __SMBIOS_STANDARD_H__\r
+//\r
+// Smbios Table Entry Point Structure\r
+//\r
+#pragma pack(1)\r
+typedef struct {\r
+ UINT8 AnchorString[4];\r
+ UINT8 EntryPointStructureChecksum;\r
+ UINT8 EntryPointLength;\r
+ UINT8 MajorVersion;\r
+ UINT8 MinorVersion;\r
+ UINT16 MaxStructureSize;\r
+ UINT8 EntryPointRevision;\r
+ UINT8 FormattedArea[5];\r
+ UINT8 IntermediateAnchorString[5];\r
+ UINT8 IntermediateChecksum;\r
+ UINT16 TableLength;\r
+ UINT32 TableAddress;\r
+ UINT16 NumberOfSmbiosStructures;\r
+ UINT8 SmbiosBcdRevision;\r
+} SMBIOS_TABLE_ENTRY_POINT;\r
+\r
+//\r
+// The Smbios structure header\r
+//\r
+typedef struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Handle;\r
+} SMBIOS_STRUCTURE;\r
+\r
+#pragma pack()\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ This file declares the SMBus definitions defined in SmBus Specifciation\r
+ V2.0.\r
+\r
+ Copyright (c) 2007, Intel Corporation \r
+ All rights reserved. This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ @par Revision Reference:\r
+ These definitions are defined in System Management Bus (SmBus) Specification V2.0.\r
+\r
+**/\r
+\r
+#ifndef _SMBUS_H_\r
+#define _SMBUS_H_\r
+\r
+\r
+//\r
+// UDID of SMBUS device.\r
+//\r
+typedef struct {\r
+ UINT32 VendorSpecificId;\r
+ UINT16 SubsystemDeviceId;\r
+ UINT16 SubsystemVendorId;\r
+ UINT16 Interface;\r
+ UINT16 DeviceId;\r
+ UINT16 VendorId;\r
+ UINT8 VendorRevision;\r
+ UINT8 DeviceCapabilities;\r
+} EFI_SMBUS_UDID;\r
+\r
+//\r
+// Smbus Device Address, Smbus Device Command, Smbus Operations\r
+//\r
+typedef struct {\r
+ UINTN SmbusDeviceAddress : 7;\r
+} EFI_SMBUS_DEVICE_ADDRESS;\r
+\r
+typedef UINTN EFI_SMBUS_DEVICE_COMMAND;\r
+\r
+typedef enum _EFI_SMBUS_OPERATION\r
+{\r
+ EfiSmbusQuickRead,\r
+ EfiSmbusQuickWrite,\r
+ EfiSmbusReceiveByte,\r
+ EfiSmbusSendByte,\r
+ EfiSmbusReadByte,\r
+ EfiSmbusWriteByte,\r
+ EfiSmbusReadWord,\r
+ EfiSmbusWriteWord,\r
+ EfiSmbusReadBlock,\r
+ EfiSmbusWriteBlock,\r
+ EfiSmbusProcessCall,\r
+ EfiSmbusBWBRProcessCall\r
+} EFI_SMBUS_OPERATION;\r
+\r
+#endif\r
+\r
--- /dev/null
+/** @file\r
+ Support for USB 1.1 standard.\r
+\r
+ Copyright (c) 2006, Intel Corporation \r
+ All rights reserved. This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ Module Name: Usb.h\r
+\r
+**/\r
+\r
+#ifndef __USB_H__\r
+#define __USB_H__\r
+\r
+//\r
+// USB Descriptor types\r
+//\r
+#define USB_DT_DEVICE 0x01\r
+#define USB_DT_CONFIG 0x02\r
+#define USB_DT_STRING 0x03\r
+#define USB_DT_INTERFACE 0x04\r
+#define USB_DT_ENDPOINT 0x05\r
+#define USB_DT_HUB 0x29\r
+#define USB_DT_HID 0x21\r
+\r
+//\r
+// USB request type\r
+//\r
+#define USB_TYPE_STANDARD (0x00 << 5)\r
+#define USB_TYPE_CLASS (0x01 << 5)\r
+#define USB_TYPE_VENDOR (0x02 << 5)\r
+#define USB_TYPE_RESERVED (0x03 << 5)\r
+\r
+//\r
+// USB request targer device\r
+//\r
+#define USB_RECIP_DEVICE 0x00\r
+#define USB_RECIP_INTERFACE 0x01\r
+#define USB_RECIP_ENDPOINT 0x02\r
+#define USB_RECIP_OTHER 0x03\r
+\r
+//\r
+// Request target types.\r
+//\r
+#define USB_RT_DEVICE 0x00\r
+#define USB_RT_INTERFACE 0x01\r
+#define USB_RT_ENDPOINT 0x02\r
+#define USB_RT_HUB (USB_TYPE_CLASS | USB_RECIP_DEVICE)\r
+#define USB_RT_PORT (USB_TYPE_CLASS | USB_RECIP_OTHER)\r
+\r
+//\r
+// USB Transfer Results\r
+//\r
+#define EFI_USB_NOERROR 0x00\r
+#define EFI_USB_ERR_NOTEXECUTE 0x01\r
+#define EFI_USB_ERR_STALL 0x02\r
+#define EFI_USB_ERR_BUFFER 0x04\r
+#define EFI_USB_ERR_BABBLE 0x08\r
+#define EFI_USB_ERR_NAK 0x10\r
+#define EFI_USB_ERR_CRC 0x20\r
+#define EFI_USB_ERR_TIMEOUT 0x40\r
+#define EFI_USB_ERR_BITSTUFF 0x80\r
+#define EFI_USB_ERR_SYSTEM 0x100\r
+\r
+//\r
+//Use 200 ms to increase the error handling response time\r
+//\r
+#define EFI_USB_INTERRUPT_DELAY 2000000\r
+\r
+//\r
+// USB transation direction\r
+//\r
+typedef enum {\r
+ EfiUsbDataIn,\r
+ EfiUsbDataOut,\r
+ EfiUsbNoData\r
+} EFI_USB_DATA_DIRECTION;\r
+\r
+//\r
+// Usb Data recipient type\r
+//\r
+typedef enum {\r
+ EfiUsbDevice,\r
+ EfiUsbInterface,\r
+ EfiUsbEndpoint\r
+} EFI_USB_RECIPIENT;\r
+\r
+typedef enum {\r
+ EfiUsbEndpointHalt,\r
+ EfiUsbDeviceRemoteWakeup\r
+} EFI_USB_STANDARD_FEATURE_SELECTOR;\r
+\r
+#pragma pack(1)\r
+//\r
+// Usb device request structure\r
+//\r
+typedef struct {\r
+ UINT8 RequestType;\r
+ UINT8 Request;\r
+ UINT16 Value;\r
+ UINT16 Index;\r
+ UINT16 Length;\r
+} EFI_USB_DEVICE_REQUEST;\r
+\r
+//\r
+// Standard USB request\r
+//\r
+#define USB_DEV_GET_STATUS 0x00\r
+\r
+#define USB_DEV_CLEAR_FEATURE 0x01\r
+\r
+#define USB_DEV_SET_FEATURE 0x03\r
+\r
+#define USB_DEV_SET_ADDRESS 0x05\r
+#define USB_DEV_SET_ADDRESS_REQ_TYPE 0x00\r
+\r
+#define USB_DEV_GET_DESCRIPTOR 0x06\r
+#define USB_DEV_GET_DESCRIPTOR_REQ_TYPE 0x80\r
+\r
+#define USB_DEV_SET_DESCRIPTOR 0x07\r
+#define USB_DEV_SET_DESCRIPTOR_REQ_TYPE 0x00\r
+\r
+#define USB_DEV_GET_CONFIGURATION 0x08\r
+#define USB_DEV_GET_CONFIGURATION_REQ_TYPE 0x80\r
+\r
+#define USB_DEV_SET_CONFIGURATION 0x09\r
+#define USB_DEV_SET_CONFIGURATION_REQ_TYPE 0x00\r
+\r
+#define USB_DEV_GET_INTERFACE 0x0A\r
+#define USB_DEV_GET_INTERFACE_REQ_TYPE 0x81\r
+\r
+#define USB_DEV_SET_INTERFACE 0x0B\r
+#define USB_DEV_SET_INTERFACE_REQ_TYPE 0x01\r
+\r
+#define USB_DEV_SYNCH_FRAME 0x0C\r
+#define USB_DEV_SYNCH_FRAME_REQ_TYPE 0x82\r
+\r
+//\r
+// Device descriptor. refer USB1.1\r
+//\r
+typedef struct usb_device_descriptor {\r
+ UINT8 Length;\r
+ UINT8 DescriptorType;\r
+ UINT16 BcdUSB;\r
+ UINT8 DeviceClass;\r
+ UINT8 DeviceSubClass;\r
+ UINT8 DeviceProtocol;\r
+ UINT8 MaxPacketSize0;\r
+ UINT16 IdVendor;\r
+ UINT16 IdProduct;\r
+ UINT16 BcdDevice;\r
+ UINT8 StrManufacturer;\r
+ UINT8 StrProduct;\r
+ UINT8 StrSerialNumber;\r
+ UINT8 NumConfigurations;\r
+} EFI_USB_DEVICE_DESCRIPTOR;\r
+\r
+//\r
+// Endpoint descriptor\r
+//\r
+typedef struct {\r
+ UINT8 Length;\r
+ UINT8 DescriptorType;\r
+ UINT8 EndpointAddress;\r
+ UINT8 Attributes;\r
+ UINT16 MaxPacketSize;\r
+ UINT8 Interval;\r
+} EFI_USB_ENDPOINT_DESCRIPTOR;\r
+\r
+//\r
+// Interface descriptor\r
+//\r
+typedef struct {\r
+ UINT8 Length;\r
+ UINT8 DescriptorType;\r
+ UINT8 InterfaceNumber;\r
+ UINT8 AlternateSetting;\r
+ UINT8 NumEndpoints;\r
+ UINT8 InterfaceClass;\r
+ UINT8 InterfaceSubClass;\r
+ UINT8 InterfaceProtocol;\r
+ UINT8 Interface;\r
+} EFI_USB_INTERFACE_DESCRIPTOR;\r
+\r
+//\r
+// USB alternate setting\r
+//\r
+typedef struct {\r
+ EFI_USB_INTERFACE_DESCRIPTOR *Interface;\r
+} USB_ALT_SETTING;\r
+\r
+//\r
+// Configuration descriptor\r
+//\r
+typedef struct {\r
+ UINT8 Length;\r
+ UINT8 DescriptorType;\r
+ UINT16 TotalLength;\r
+ UINT8 NumInterfaces;\r
+ UINT8 ConfigurationValue;\r
+ UINT8 Configuration;\r
+ UINT8 Attributes;\r
+ UINT8 MaxPower;\r
+} EFI_USB_CONFIG_DESCRIPTOR;\r
+\r
+//\r
+// Supported String Languages\r
+//\r
+typedef struct {\r
+ UINT8 Length;\r
+ UINT8 DescriptorType;\r
+ UINT16 SupportedLanID[1];\r
+} EFI_USB_SUPPORTED_LANGUAGES;\r
+\r
+//\r
+// String descriptor\r
+//\r
+typedef struct {\r
+ UINT8 Length;\r
+ UINT8 DescriptorType;\r
+ CHAR16 String[1];\r
+} EFI_USB_STRING_DESCRIPTOR;\r
+\r
+//\r
+// Hub descriptor\r
+//\r
+#define MAXBYTES 8\r
+typedef struct {\r
+ UINT8 Length;\r
+ UINT8 DescriptorType;\r
+ UINT8 NbrPorts;\r
+ UINT8 HubCharacteristics[2];\r
+ UINT8 PwrOn2PwrGood;\r
+ UINT8 HubContrCurrent;\r
+ UINT8 Filler[MAXBYTES];\r
+} EFI_USB_HUB_DESCRIPTOR;\r
+\r
+typedef struct {\r
+ UINT16 PortStatus;\r
+ UINT16 PortChangeStatus;\r
+} EFI_USB_PORT_STATUS;\r
+\r
+//\r
+// Constant value for Port Status & Port Change Status\r
+//\r
+#define USB_PORT_STAT_CONNECTION 0x0001\r
+#define USB_PORT_STAT_ENABLE 0x0002\r
+#define USB_PORT_STAT_SUSPEND 0x0004\r
+#define USB_PORT_STAT_OVERCURRENT 0x0008\r
+#define USB_PORT_STAT_RESET 0x0010\r
+#define USB_PORT_STAT_POWER 0x0100\r
+#define USB_PORT_STAT_LOW_SPEED 0x0200\r
+#define USB_PORT_STAT_HIGH_SPEED 0x0400\r
+#define USB_PORT_STAT_OWNER 0x0800\r
+\r
+#define USB_PORT_STAT_C_CONNECTION 0x0001\r
+#define USB_PORT_STAT_C_ENABLE 0x0002\r
+#define USB_PORT_STAT_C_SUSPEND 0x0004\r
+#define USB_PORT_STAT_C_OVERCURRENT 0x0008\r
+#define USB_PORT_STAT_C_RESET 0x0010\r
+\r
+//\r
+// Used for set/clear port feature request\r
+//\r
+typedef enum {\r
+ EfiUsbPortEnable = 1,\r
+ EfiUsbPortSuspend = 2,\r
+ EfiUsbPortReset = 4,\r
+ EfiUsbPortPower = 8,\r
+ EfiUsbPortOwner = 13,\r
+ EfiUsbPortConnectChange = 16,\r
+ EfiUsbPortEnableChange = 17,\r
+ EfiUsbPortSuspendChange = 18,\r
+ EfiUsbPortOverCurrentChange = 19,\r
+ EfiUsbPortResetChange = 20\r
+} EFI_USB_PORT_FEATURE;\r
+\r
+#pragma pack()\r
+\r
+#endif\r
projects / mirror_edk2.git / commitdiff