--- /dev/null
+//\r
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <Base.h>\r
+#include <AutoGen.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmPlatformSecBootAction)\r
+GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)\r
+\r
+/**\r
+ Call at the beginning of the platform boot up\r
+\r
+ This function allows the firmware platform to do extra actions at the early\r
+ stage of the platform power up.\r
+\r
+ Note: This function must be implemented in assembler as there is no stack set up yet\r
+\r
+**/\r
+ASM_PFX(ArmPlatformSecBootAction):\r
+ bx lr\r
+\r
+/**\r
+ Initialize the memory where the initial stacks will reside\r
+\r
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
+ In some platform, this region is already initialized and the implementation of this function can\r
+ do nothing. This memory can also represent the Secure RAM.\r
+ This function is called before the satck has been set up. Its implementation must ensure the stack\r
+ pointer is not used (probably required to use assembly language)\r
+\r
+**/\r
+ASM_PFX(ArmPlatformSecBootMemoryInit):\r
+ // The SMC does not need to be initialized for RTSM\r
+ bx lr\r
--- /dev/null
+//\r
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <Base.h>\r
+#include <AutoGen.h>\r
+\r
+ EXPORT ArmPlatformSecBootAction\r
+ EXPORT ArmPlatformSecBootMemoryInit\r
+\r
+ PRESERVE8\r
+ AREA ArmPlatformSecLibBoot, CODE, READONLY\r
+\r
+/**\r
+ Call at the beginning of the platform boot up\r
+\r
+ This function allows the firmware platform to do extra actions at the early\r
+ stage of the platform power up.\r
+\r
+ Note: This function must be implemented in assembler as there is no stack set up yet\r
+\r
+**/\r
+ArmPlatformSecBootAction\r
+ bx lr\r
+\r
+/**\r
+ Initialize the memory where the initial stacks will reside\r
+\r
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
+ In some platform, this region is already initialized and the implementation of this function can\r
+ do nothing. This memory can also represent the Secure RAM.\r
+ This function is called before the satck has been set up. Its implementation must ensure the stack\r
+ pointer is not used (probably required to use assembly language)\r
+\r
+**/\r
+ArmPlatformSecBootMemoryInit\r
+ // The SMC does not need to be initialized for RTSM\r
+ bx lr\r
+\r
+ END\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <Base.h>\r
-#include <AutoGen.h>\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(ArmPlatformSecBootAction)\r
-GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)\r
-\r
-/**\r
- Call at the beginning of the platform boot up\r
-\r
- This function allows the firmware platform to do extra actions at the early\r
- stage of the platform power up.\r
-\r
- Note: This function must be implemented in assembler as there is no stack set up yet\r
-\r
-**/\r
-ASM_PFX(ArmPlatformSecBootAction):\r
- bx lr\r
-\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ASM_PFX(ArmPlatformSecBootMemoryInit):\r
- // The SMC does not need to be initialized for RTSM\r
- bx lr\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <Base.h>\r
-#include <AutoGen.h>\r
-\r
- EXPORT ArmPlatformSecBootAction\r
- EXPORT ArmPlatformSecBootMemoryInit\r
-\r
- PRESERVE8\r
- AREA ArmPlatformSecLibBoot, CODE, READONLY\r
-\r
-/**\r
- Call at the beginning of the platform boot up\r
-\r
- This function allows the firmware platform to do extra actions at the early\r
- stage of the platform power up.\r
-\r
- Note: This function must be implemented in assembler as there is no stack set up yet\r
-\r
-**/\r
-ArmPlatformSecBootAction\r
- bx lr\r
-\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ArmPlatformSecBootMemoryInit\r
- // The SMC does not need to be initialized for RTSM\r
- bx lr\r
-\r
- END\r
ArmPlatformLibNullSec.c\r
\r
[Sources.ARM]\r
- ArmPlatformLibNullBoot.asm | RVCT\r
- ArmPlatformLibNullBoot.S | GCC\r
+ Arm/ArmPlatformLibNullBoot.asm | RVCT\r
+ Arm/ArmPlatformLibNullBoot.S | GCC\r
\r
[FixedPcd]\r
gArmTokenSpaceGuid.PcdFvBaseAddress\r
--- /dev/null
+//\r
+// Copyright (c) 2012, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <AutoGen.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmPlatformStackSet)\r
+GCC_ASM_EXPORT(ArmPlatformStackSetPrimary)\r
+GCC_ASM_EXPORT(ArmPlatformStackSetSecondary)\r
+\r
+GCC_ASM_IMPORT(ArmPlatformGetCorePosition)\r
+\r
+GCC_ASM_IMPORT(gPcd_FixedAtBuild_PcdCoreCount)\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
+\r
+//VOID\r
+//ArmPlatformStackSet (\r
+// IN UINTN StackBase,\r
+// IN UINTN MpId,\r
+// IN UINTN PrimaryStackSize,\r
+// IN UINTN SecondaryStackSize\r
+// );\r
+ASM_PFX(ArmPlatformStackSet):\r
+ // Identify Stack\r
+ // Mask for ClusterId|CoreId\r
+ LoadConstantToReg (0xFFFF, r4)\r
+ and r1, r1, r4\r
+ // Is it the Primary Core ?\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r4)\r
+ ldr r4, [r4]\r
+ cmp r1, r4\r
+ beq ASM_PFX(ArmPlatformStackSetPrimary)\r
+ bne ASM_PFX(ArmPlatformStackSetSecondary)\r
+\r
+//VOID\r
+//ArmPlatformStackSetPrimary (\r
+// IN UINTN StackBase,\r
+// IN UINTN MpId,\r
+// IN UINTN PrimaryStackSize,\r
+// IN UINTN SecondaryStackSize\r
+// );\r
+ASM_PFX(ArmPlatformStackSetPrimary):\r
+ mov r4, lr\r
+\r
+ // Add stack of primary stack to StackBase\r
+ add r0, r0, r2\r
+\r
+ // Compute SecondaryCoresCount * SecondaryCoreStackSize\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdCoreCount, r1)\r
+ ldr r1, [r1]\r
+ sub r1, #1\r
+ mul r3, r3, r1\r
+\r
+ // Set Primary Stack ((StackBase + PrimaryStackSize) + (SecondaryCoresCount * SecondaryCoreStackSize))\r
+ add sp, r0, r3\r
+\r
+ bx r4\r
+\r
+//VOID\r
+//ArmPlatformStackSetSecondary (\r
+// IN UINTN StackBase,\r
+// IN UINTN MpId,\r
+// IN UINTN PrimaryStackSize,\r
+// IN UINTN SecondaryStackSize\r
+// );\r
+ASM_PFX(ArmPlatformStackSetSecondary):\r
+ mov r4, lr\r
+ mov sp, r0\r
+\r
+ // Get Core Position\r
+ mov r0, r1\r
+ bl ASM_PFX(ArmPlatformGetCorePosition)\r
+ mov r5, r0\r
+\r
+ // Get Primary Core Position\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
+ ldr r0, [r0]\r
+ bl ASM_PFX(ArmPlatformGetCorePosition)\r
+\r
+ // Get Secondary Core Position. We should get consecutive secondary stack number from 1...(CoreCount-1)\r
+ cmp r5, r0\r
+ subhi r5, r5, #1\r
+ add r5, r5, #1\r
+\r
+ // Compute top of the secondary stack\r
+ mul r3, r3, r5\r
+\r
+ // Set stack\r
+ add sp, sp, r3\r
+\r
+ bx r4\r
+\r
--- /dev/null
+//\r
+// Copyright (c) 2012, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+ EXPORT ArmPlatformStackSet\r
+ EXPORT ArmPlatformStackSetPrimary\r
+ EXPORT ArmPlatformStackSetSecondary\r
+\r
+ IMPORT ArmPlatformGetCorePosition\r
+\r
+ IMPORT _gPcd_FixedAtBuild_PcdCoreCount\r
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore\r
+\r
+ PRESERVE8\r
+ AREA ArmPlatformStackLib, CODE, READONLY\r
+\r
+//VOID\r
+//ArmPlatformStackSet (\r
+// IN UINTN StackBase,\r
+// IN UINTN MpId,\r
+// IN UINTN PrimaryStackSize,\r
+// IN UINTN SecondaryStackSize\r
+// );\r
+ArmPlatformStackSet FUNCTION\r
+ // Identify Stack\r
+ // Mask for ClusterId|CoreId\r
+ LoadConstantToReg (0xFFFF, r4)\r
+ and r1, r1, r4\r
+ // Is it the Primary Core ?\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r4)\r
+ ldr r4, [r4]\r
+ cmp r1, r4\r
+ beq ArmPlatformStackSetPrimary\r
+ bne ArmPlatformStackSetSecondary\r
+ ENDFUNC\r
+\r
+//VOID\r
+//ArmPlatformStackSetPrimary (\r
+// IN UINTN StackBase,\r
+// IN UINTN MpId,\r
+// IN UINTN PrimaryStackSize,\r
+// IN UINTN SecondaryStackSize\r
+// );\r
+ArmPlatformStackSetPrimary FUNCTION\r
+ mov r4, lr\r
+\r
+ // Add stack of primary stack to StackBase\r
+ add r0, r0, r2\r
+\r
+ // Compute SecondaryCoresCount * SecondaryCoreStackSize\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdCoreCount, r1)\r
+ ldr r1, [r1]\r
+ sub r1, #1\r
+ mul r3, r3, r1\r
+\r
+ // Set Primary Stack ((StackBase + PrimaryStackSize) + (SecondaryCoresCount * SecondaryCoreStackSize))\r
+ add sp, r0, r3\r
+\r
+ bx r4\r
+ ENDFUNC\r
+\r
+//VOID\r
+//ArmPlatformStackSetSecondary (\r
+// IN UINTN StackBase,\r
+// IN UINTN MpId,\r
+// IN UINTN PrimaryStackSize,\r
+// IN UINTN SecondaryStackSize\r
+// );\r
+ArmPlatformStackSetSecondary FUNCTION\r
+ mov r4, lr\r
+ mov sp, r0\r
+\r
+ // Get Core Position\r
+ mov r0, r1\r
+ bl ArmPlatformGetCorePosition\r
+ mov r5, r0\r
+\r
+ // Get Primary Core Position\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
+ ldr r0, [r0]\r
+ bl ArmPlatformGetCorePosition\r
+\r
+ // Get Secondary Core Position. We should get consecutive secondary stack number from 1...(CoreCount-1)\r
+ cmp r5, r0\r
+ subhi r5, r5, #1\r
+ add r5, r5, #1\r
+\r
+ // Compute top of the secondary stack\r
+ mul r3, r3, r5\r
+\r
+ // Set stack\r
+ add sp, sp, r3\r
+\r
+ bx r4\r
+ ENDFUNC\r
+\r
+ END\r
+++ /dev/null
-//\r
-// Copyright (c) 2012, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <AutoGen.h>\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(ArmPlatformStackSet)\r
-GCC_ASM_EXPORT(ArmPlatformStackSetPrimary)\r
-GCC_ASM_EXPORT(ArmPlatformStackSetSecondary)\r
-\r
-GCC_ASM_IMPORT(ArmPlatformGetCorePosition)\r
-\r
-GCC_ASM_IMPORT(gPcd_FixedAtBuild_PcdCoreCount)\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
-\r
-//VOID\r
-//ArmPlatformStackSet (\r
-// IN UINTN StackBase,\r
-// IN UINTN MpId,\r
-// IN UINTN PrimaryStackSize,\r
-// IN UINTN SecondaryStackSize\r
-// );\r
-ASM_PFX(ArmPlatformStackSet):\r
- // Identify Stack\r
- // Mask for ClusterId|CoreId\r
- LoadConstantToReg (0xFFFF, r4)\r
- and r1, r1, r4\r
- // Is it the Primary Core ?\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r4)\r
- ldr r4, [r4]\r
- cmp r1, r4\r
- beq ASM_PFX(ArmPlatformStackSetPrimary)\r
- bne ASM_PFX(ArmPlatformStackSetSecondary)\r
-\r
-//VOID\r
-//ArmPlatformStackSetPrimary (\r
-// IN UINTN StackBase,\r
-// IN UINTN MpId,\r
-// IN UINTN PrimaryStackSize,\r
-// IN UINTN SecondaryStackSize\r
-// );\r
-ASM_PFX(ArmPlatformStackSetPrimary):\r
- mov r4, lr\r
-\r
- // Add stack of primary stack to StackBase\r
- add r0, r0, r2\r
-\r
- // Compute SecondaryCoresCount * SecondaryCoreStackSize\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdCoreCount, r1)\r
- ldr r1, [r1]\r
- sub r1, #1\r
- mul r3, r3, r1\r
-\r
- // Set Primary Stack ((StackBase + PrimaryStackSize) + (SecondaryCoresCount * SecondaryCoreStackSize))\r
- add sp, r0, r3\r
-\r
- bx r4\r
-\r
-//VOID\r
-//ArmPlatformStackSetSecondary (\r
-// IN UINTN StackBase,\r
-// IN UINTN MpId,\r
-// IN UINTN PrimaryStackSize,\r
-// IN UINTN SecondaryStackSize\r
-// );\r
-ASM_PFX(ArmPlatformStackSetSecondary):\r
- mov r4, lr\r
- mov sp, r0\r
-\r
- // Get Core Position\r
- mov r0, r1\r
- bl ASM_PFX(ArmPlatformGetCorePosition)\r
- mov r5, r0\r
-\r
- // Get Primary Core Position\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
- ldr r0, [r0]\r
- bl ASM_PFX(ArmPlatformGetCorePosition)\r
-\r
- // Get Secondary Core Position. We should get consecutive secondary stack number from 1...(CoreCount-1)\r
- cmp r5, r0\r
- subhi r5, r5, #1\r
- add r5, r5, #1\r
-\r
- // Compute top of the secondary stack\r
- mul r3, r3, r5\r
-\r
- // Set stack\r
- add sp, sp, r3\r
-\r
- bx r4\r
-\r
+++ /dev/null
-//\r
-// Copyright (c) 2012, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <AutoGen.h>\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
- EXPORT ArmPlatformStackSet\r
- EXPORT ArmPlatformStackSetPrimary\r
- EXPORT ArmPlatformStackSetSecondary\r
-\r
- IMPORT ArmPlatformGetCorePosition\r
-\r
- IMPORT _gPcd_FixedAtBuild_PcdCoreCount\r
- IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore\r
-\r
- PRESERVE8\r
- AREA ArmPlatformStackLib, CODE, READONLY\r
-\r
-//VOID\r
-//ArmPlatformStackSet (\r
-// IN UINTN StackBase,\r
-// IN UINTN MpId,\r
-// IN UINTN PrimaryStackSize,\r
-// IN UINTN SecondaryStackSize\r
-// );\r
-ArmPlatformStackSet FUNCTION\r
- // Identify Stack\r
- // Mask for ClusterId|CoreId\r
- LoadConstantToReg (0xFFFF, r4)\r
- and r1, r1, r4\r
- // Is it the Primary Core ?\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r4)\r
- ldr r4, [r4]\r
- cmp r1, r4\r
- beq ArmPlatformStackSetPrimary\r
- bne ArmPlatformStackSetSecondary\r
- ENDFUNC\r
-\r
-//VOID\r
-//ArmPlatformStackSetPrimary (\r
-// IN UINTN StackBase,\r
-// IN UINTN MpId,\r
-// IN UINTN PrimaryStackSize,\r
-// IN UINTN SecondaryStackSize\r
-// );\r
-ArmPlatformStackSetPrimary FUNCTION\r
- mov r4, lr\r
-\r
- // Add stack of primary stack to StackBase\r
- add r0, r0, r2\r
-\r
- // Compute SecondaryCoresCount * SecondaryCoreStackSize\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdCoreCount, r1)\r
- ldr r1, [r1]\r
- sub r1, #1\r
- mul r3, r3, r1\r
-\r
- // Set Primary Stack ((StackBase + PrimaryStackSize) + (SecondaryCoresCount * SecondaryCoreStackSize))\r
- add sp, r0, r3\r
-\r
- bx r4\r
- ENDFUNC\r
-\r
-//VOID\r
-//ArmPlatformStackSetSecondary (\r
-// IN UINTN StackBase,\r
-// IN UINTN MpId,\r
-// IN UINTN PrimaryStackSize,\r
-// IN UINTN SecondaryStackSize\r
-// );\r
-ArmPlatformStackSetSecondary FUNCTION\r
- mov r4, lr\r
- mov sp, r0\r
-\r
- // Get Core Position\r
- mov r0, r1\r
- bl ArmPlatformGetCorePosition\r
- mov r5, r0\r
-\r
- // Get Primary Core Position\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
- ldr r0, [r0]\r
- bl ArmPlatformGetCorePosition\r
-\r
- // Get Secondary Core Position. We should get consecutive secondary stack number from 1...(CoreCount-1)\r
- cmp r5, r0\r
- subhi r5, r5, #1\r
- add r5, r5, #1\r
-\r
- // Compute top of the secondary stack\r
- mul r3, r3, r5\r
-\r
- // Set stack\r
- add sp, sp, r3\r
-\r
- bx r4\r
- ENDFUNC\r
-\r
- END\r
ArmPkg/ArmPkg.dec\r
ArmPlatformPkg/ArmPlatformPkg.dec\r
\r
-[Sources.common]\r
- ArmPlatformStackLib.asm | RVCT\r
- ArmPlatformStackLib.S | GCC\r
+[Sources.ARM]\r
+ Arm/ArmPlatformStackLib.asm | RVCT\r
+ Arm/ArmPlatformStackLib.S | GCC\r
\r
[FixedPcd]\r
gArmPlatformTokenSpaceGuid.PcdCoreCount\r
)\r
{\r
// Ensure the Monitor Table is 32bit aligned\r
- ASSERT (IS_ALIGNED(MonitorVectorTable, BIT5));\r
+ ASSERT (((UINTN)&MonitorVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
\r
// Write the Monitor Mode Vector Table Address\r
ArmWriteMVBar ((UINTN) &MonitorVectorTable);\r
}\r
+\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <PiDxe.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/ArmLib.h>\r
+#include <Chipset/ArmV7.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
+#include <Library/EblCmdLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+#define GET_TT_ATTRIBUTES(TTEntry) ((TTEntry) & ~(TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK))\r
+#define GET_TT_PAGE_ATTRIBUTES(TTEntry) ((TTEntry) & 0xFFF)\r
+#define GET_TT_LARGEPAGE_ATTRIBUTES(TTEntry) ((TTEntry) & 0xFFFF)\r
+\r
+// Section\r
+#define TT_DESCRIPTOR_SECTION_STRONGLY_ORDER (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \\r
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED)\r
+\r
+// Small Page\r
+#define TT_DESCRIPTOR_PAGE_STRONGLY_ORDER (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
+ TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED)\r
+\r
+// Large Page\r
+#define TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \\r
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)\r
+#define TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \\r
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)\r
+#define TT_DESCRIPTOR_LARGEPAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \\r
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)\r
+#define TT_DESCRIPTOR_LARGEPAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \\r
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)\r
+\r
+\r
+typedef enum { Level0, Level1,Level2 } MMU_LEVEL;\r
+\r
+typedef struct {\r
+ MMU_LEVEL Level;\r
+ UINT32 Value;\r
+ UINT32 Index;\r
+ UINT32* Table;\r
+} MMU_ENTRY;\r
+\r
+MMU_ENTRY\r
+MmuEntryCreate (\r
+ IN MMU_LEVEL Level,\r
+ IN UINT32* Table,\r
+ IN UINT32 Index\r
+ )\r
+{\r
+ MMU_ENTRY Entry;\r
+ Entry.Level = Level;\r
+ Entry.Value = Table[Index];\r
+ Entry.Table = Table;\r
+ Entry.Index = Index;\r
+ return Entry;\r
+}\r
+\r
+UINT32\r
+MmuEntryIsValidAddress (\r
+ IN MMU_LEVEL Level,\r
+ IN UINT32 Entry\r
+ )\r
+{\r
+ if (Level == Level0) {\r
+ return 0;\r
+ } else if (Level == Level1) {\r
+ if ((Entry & 0x3) == 0) { // Ignored\r
+ return 0;\r
+ } else if ((Entry & 0x3) == 2) { // Section Type\r
+ return 1;\r
+ } else { // Page Type\r
+ return 0;\r
+ }\r
+ } else if (Level == Level2){\r
+ if ((Entry & 0x3) == 0) { // Ignored\r
+ return 0;\r
+ } else { // Page Type\r
+ return 1;\r
+ }\r
+ } else {\r
+ DEBUG((EFI_D_ERROR,"MmuEntryIsValidAddress: Level:%d Entry:0x%X\n",(UINT32)Level,(UINT32)Entry));\r
+ ASSERT(0);\r
+ return 0;\r
+ }\r
+}\r
+\r
+UINT32\r
+MmuEntryGetAddress (\r
+ IN MMU_ENTRY Entry\r
+ )\r
+{\r
+ if (Entry.Level == Level1) {\r
+ if ((Entry.Value & 0x3) == 0) {\r
+ return 0;\r
+ } else if ((Entry.Value & 0x3) == 2) { // Section Type\r
+ return Entry.Value & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK;\r
+ } else if ((Entry.Value & 0x3) == 1) { // Level2 Table\r
+ MMU_ENTRY Level2Entry = MmuEntryCreate (Level2,(UINT32*)(Entry.Value & 0xFFFFC000),0);\r
+ return MmuEntryGetAddress (Level2Entry);\r
+ } else { // Page Type\r
+ return 0;\r
+ }\r
+ } else if (Entry.Level == Level2) {\r
+ if ((Entry.Value & 0x3) == 0) { // Ignored\r
+ return 0;\r
+ } else if ((Entry.Value & 0x3) == 1) { // Large Page\r
+ return Entry.Value & 0xFFFF0000;\r
+ } else if ((Entry.Value & 0x2) == 2) { // Small Page\r
+ return Entry.Value & 0xFFFFF000;\r
+ } else {\r
+ return 0;\r
+ }\r
+ } else {\r
+ ASSERT(0);\r
+ return 0;\r
+ }\r
+}\r
+\r
+UINT32\r
+MmuEntryGetSize (\r
+ IN MMU_ENTRY Entry\r
+ )\r
+{\r
+ if (Entry.Level == Level1) {\r
+ if ((Entry.Value & 0x3) == 0) {\r
+ return 0;\r
+ } else if ((Entry.Value & 0x3) == 2) {\r
+ if (Entry.Value & (1 << 18))\r
+ return 16*SIZE_1MB;\r
+ else\r
+ return SIZE_1MB;\r
+ } else if ((Entry.Value & 0x3) == 1) { // Level2 Table split 1MB section\r
+ return SIZE_1MB;\r
+ } else {\r
+ DEBUG((EFI_D_ERROR, "MmuEntryGetSize: Value:0x%X",Entry.Value));\r
+ ASSERT(0);\r
+ return 0;\r
+ }\r
+ } else if (Entry.Level == Level2) {\r
+ if ((Entry.Value & 0x3) == 0) { // Ignored\r
+ return 0;\r
+ } else if ((Entry.Value & 0x3) == 1) { // Large Page\r
+ return SIZE_64KB;\r
+ } else if ((Entry.Value & 0x2) == 2) { // Small Page\r
+ return SIZE_4KB;\r
+ } else {\r
+ ASSERT(0);\r
+ return 0;\r
+ }\r
+ } else {\r
+ ASSERT(0);\r
+ return 0;\r
+ }\r
+}\r
+\r
+CONST CHAR8*\r
+MmuEntryGetAttributesName (\r
+ IN MMU_ENTRY Entry\r
+ )\r
+{\r
+ UINT32 Value;\r
+\r
+ if (Entry.Level == Level1) {\r
+ Value = GET_TT_ATTRIBUTES(Entry.Value) | TT_DESCRIPTOR_SECTION_NS_MASK;\r
+ if (Value == TT_DESCRIPTOR_SECTION_WRITE_BACK(0))\r
+ return "TT_DESCRIPTOR_SECTION_WRITE_BACK";\r
+ else if (Value == TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0))\r
+ return "TT_DESCRIPTOR_SECTION_WRITE_THROUGH";\r
+ else if (Value == TT_DESCRIPTOR_SECTION_DEVICE(0))\r
+ return "TT_DESCRIPTOR_SECTION_DEVICE";\r
+ else if (Value == TT_DESCRIPTOR_SECTION_UNCACHED(0))\r
+ return "TT_DESCRIPTOR_SECTION_UNCACHED";\r
+ else if (Value == TT_DESCRIPTOR_SECTION_STRONGLY_ORDER)\r
+ return "TT_DESCRIPTOR_SECTION_STRONGLY_ORDERED";\r
+ else {\r
+ return "SectionUnknown";\r
+ }\r
+ } else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page\r
+ Value = GET_TT_PAGE_ATTRIBUTES(Entry.Value);\r
+ if (Value == TT_DESCRIPTOR_PAGE_WRITE_BACK)\r
+ return "TT_DESCRIPTOR_PAGE_WRITE_BACK";\r
+ else if (Value == TT_DESCRIPTOR_PAGE_WRITE_THROUGH)\r
+ return "TT_DESCRIPTOR_PAGE_WRITE_THROUGH";\r
+ else if (Value == TT_DESCRIPTOR_PAGE_DEVICE)\r
+ return "TT_DESCRIPTOR_PAGE_DEVICE";\r
+ else if (Value == TT_DESCRIPTOR_PAGE_UNCACHED)\r
+ return "TT_DESCRIPTOR_PAGE_UNCACHED";\r
+ else if (Value == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER)\r
+ return "TT_DESCRIPTOR_PAGE_STRONGLY_ORDERED";\r
+ else {\r
+ return "PageUnknown";\r
+ }\r
+ } else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page\r
+ Value = GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value);\r
+ if (Value == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK)\r
+ return "TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK";\r
+ else if (Value == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH)\r
+ return "TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH";\r
+ else if (Value == TT_DESCRIPTOR_LARGEPAGE_DEVICE)\r
+ return "TT_DESCRIPTOR_LARGEPAGE_DEVICE";\r
+ else if (Value == TT_DESCRIPTOR_LARGEPAGE_UNCACHED)\r
+ return "TT_DESCRIPTOR_LARGEPAGE_UNCACHED";\r
+ else {\r
+ return "LargePageUnknown";\r
+ }\r
+ } else {\r
+ ASSERT(0);\r
+ return "";\r
+ }\r
+}\r
+\r
+UINT32\r
+MmuEntryGetAttributes (\r
+ IN MMU_ENTRY Entry\r
+ )\r
+{\r
+ if (Entry.Level == Level1) {\r
+ if ((Entry.Value & 0x3) == 0) {\r
+ return 0;\r
+ } else if ((Entry.Value & 0x3) == 2) {\r
+ return GET_TT_ATTRIBUTES(Entry.Value);\r
+ } else {\r
+ return 0;\r
+ }\r
+ } else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page\r
+ if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_BACK)\r
+ return TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
+ else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_THROUGH)\r
+ return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);\r
+ else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_DEVICE)\r
+ return TT_DESCRIPTOR_SECTION_DEVICE(0);\r
+ else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_UNCACHED)\r
+ return TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
+ else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER)\r
+ return TT_DESCRIPTOR_SECTION_STRONGLY_ORDER;\r
+ else {\r
+ return 0;\r
+ }\r
+ } else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page\r
+ if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK)\r
+ return TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
+ else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH)\r
+ return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);\r
+ else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_DEVICE)\r
+ return TT_DESCRIPTOR_SECTION_DEVICE(0);\r
+ else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_UNCACHED)\r
+ return TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
+ else {\r
+ return 0;\r
+ }\r
+ } else {\r
+ return 0;\r
+ }\r
+}\r
+\r
+\r
+MMU_ENTRY\r
+DumpMmuLevel (\r
+ IN MMU_LEVEL Level,\r
+ IN UINT32* Table,\r
+ IN MMU_ENTRY PreviousEntry\r
+ )\r
+{\r
+ UINT32 Index = 0, Count;\r
+ MMU_ENTRY LastEntry, Entry;\r
+\r
+ ASSERT((Level == Level1) || (Level == Level2));\r
+\r
+ if (Level == Level1) Count = 4096;\r
+ else Count = 256;\r
+\r
+ // At Level1, we will get into this function because PreviousEntry is not valid\r
+ if (!MmuEntryIsValidAddress((MMU_LEVEL)(Level-1),PreviousEntry.Value)) {\r
+ // Find the first valid address\r
+ for (; (Index < Count) && (!MmuEntryIsValidAddress(Level,Table[Index])); Index++);\r
+\r
+ LastEntry = MmuEntryCreate(Level,Table,Index);\r
+ Index++;\r
+ } else {\r
+ LastEntry = PreviousEntry;\r
+ }\r
+\r
+ for (; Index < Count; Index++) {\r
+ Entry = MmuEntryCreate(Level,Table,Index);\r
+ if ((Level == Level1) && ((Entry.Value & 0x3) == 1)) { // We have got a Level2 table redirection\r
+ LastEntry = DumpMmuLevel(Level2,(UINT32*)(Entry.Value & 0xFFFFFC00),LastEntry);\r
+ } else if (!MmuEntryIsValidAddress(Level,Table[Index])) {\r
+ if (MmuEntryIsValidAddress(LastEntry.Level,LastEntry.Value)) {\r
+ AsciiPrint("0x%08X-0x%08X\t%a\n",\r
+ MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,\r
+ MmuEntryGetAttributesName(LastEntry));\r
+ }\r
+ LastEntry = Entry;\r
+ } else {\r
+ if (MmuEntryGetAttributes(LastEntry) != MmuEntryGetAttributes(Entry)) {\r
+ if (MmuEntryIsValidAddress(Level,LastEntry.Value)) {\r
+ AsciiPrint("0x%08X-0x%08X\t%a\n",\r
+ MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,\r
+ MmuEntryGetAttributesName(LastEntry));\r
+ }\r
+ LastEntry = Entry;\r
+ } else {\r
+ ASSERT(LastEntry.Value != 0);\r
+ }\r
+ }\r
+ PreviousEntry = Entry;\r
+ }\r
+\r
+ if ((Level == Level1) && (LastEntry.Index != Index) && MmuEntryIsValidAddress(Level,LastEntry.Value)) {\r
+ AsciiPrint("0x%08X-0x%08X\t%a\n",\r
+ MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,\r
+ MmuEntryGetAttributesName(LastEntry));\r
+ }\r
+\r
+ return LastEntry;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+EblDumpMmu (\r
+ IN UINTN Argc,\r
+ IN CHAR8 **Argv\r
+ )\r
+{\r
+ UINT32 *TTEntry;\r
+ MMU_ENTRY NoEntry;\r
+\r
+ TTEntry = ArmGetTTBR0BaseAddress();\r
+\r
+ AsciiPrint ("\nTranslation Table:0x%X\n",TTEntry);\r
+ AsciiPrint ("Address Range\t\tAttributes\n");\r
+ AsciiPrint ("____________________________________________________\n");\r
+\r
+ NoEntry.Level = (MMU_LEVEL)200;\r
+ DumpMmuLevel(Level1,TTEntry,NoEntry);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
\r
[Sources.common]\r
EblCmdLib.c\r
- EblCmdMmu.c\r
EblCmdFdt.c\r
\r
+[Sources.ARM]\r
+ Arm/EblCmdMmu.c\r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
MdeModulePkg/MdeModulePkg.dec\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-*\r
-**/\r
-\r
-#include <PiDxe.h>\r
-#include <Library/UefiLib.h>\r
-#include <Library/ArmLib.h>\r
-#include <Chipset/ArmV7.h>\r
-#include <Library/CacheMaintenanceLib.h>\r
-#include <Library/EblCmdLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-#define GET_TT_ATTRIBUTES(TTEntry) ((TTEntry) & ~(TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK))\r
-#define GET_TT_PAGE_ATTRIBUTES(TTEntry) ((TTEntry) & 0xFFF)\r
-#define GET_TT_LARGEPAGE_ATTRIBUTES(TTEntry) ((TTEntry) & 0xFFFF)\r
-\r
-// Section\r
-#define TT_DESCRIPTOR_SECTION_STRONGLY_ORDER (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \\r
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED)\r
-\r
-// Small Page\r
-#define TT_DESCRIPTOR_PAGE_STRONGLY_ORDER (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
- TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
- TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
- TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED)\r
-\r
-// Large Page\r
-#define TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \\r
- TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
- TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)\r
-#define TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \\r
- TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
- TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)\r
-#define TT_DESCRIPTOR_LARGEPAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \\r
- TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
- TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)\r
-#define TT_DESCRIPTOR_LARGEPAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \\r
- TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
- TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)\r
-\r
-\r
-typedef enum { Level0, Level1,Level2 } MMU_LEVEL;\r
-\r
-typedef struct {\r
- MMU_LEVEL Level;\r
- UINT32 Value;\r
- UINT32 Index;\r
- UINT32* Table;\r
-} MMU_ENTRY;\r
-\r
-MMU_ENTRY\r
-MmuEntryCreate (\r
- IN MMU_LEVEL Level,\r
- IN UINT32* Table,\r
- IN UINT32 Index\r
- )\r
-{\r
- MMU_ENTRY Entry;\r
- Entry.Level = Level;\r
- Entry.Value = Table[Index];\r
- Entry.Table = Table;\r
- Entry.Index = Index;\r
- return Entry;\r
-}\r
-\r
-UINT32\r
-MmuEntryIsValidAddress (\r
- IN MMU_LEVEL Level,\r
- IN UINT32 Entry\r
- )\r
-{\r
- if (Level == Level0) {\r
- return 0;\r
- } else if (Level == Level1) {\r
- if ((Entry & 0x3) == 0) { // Ignored\r
- return 0;\r
- } else if ((Entry & 0x3) == 2) { // Section Type\r
- return 1;\r
- } else { // Page Type\r
- return 0;\r
- }\r
- } else if (Level == Level2){\r
- if ((Entry & 0x3) == 0) { // Ignored\r
- return 0;\r
- } else { // Page Type\r
- return 1;\r
- }\r
- } else {\r
- DEBUG((EFI_D_ERROR,"MmuEntryIsValidAddress: Level:%d Entry:0x%X\n",(UINT32)Level,(UINT32)Entry));\r
- ASSERT(0);\r
- return 0;\r
- }\r
-}\r
-\r
-UINT32\r
-MmuEntryGetAddress (\r
- IN MMU_ENTRY Entry\r
- )\r
-{\r
- if (Entry.Level == Level1) {\r
- if ((Entry.Value & 0x3) == 0) {\r
- return 0;\r
- } else if ((Entry.Value & 0x3) == 2) { // Section Type\r
- return Entry.Value & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK;\r
- } else if ((Entry.Value & 0x3) == 1) { // Level2 Table\r
- MMU_ENTRY Level2Entry = MmuEntryCreate (Level2,(UINT32*)(Entry.Value & 0xFFFFC000),0);\r
- return MmuEntryGetAddress (Level2Entry);\r
- } else { // Page Type\r
- return 0;\r
- }\r
- } else if (Entry.Level == Level2) {\r
- if ((Entry.Value & 0x3) == 0) { // Ignored\r
- return 0;\r
- } else if ((Entry.Value & 0x3) == 1) { // Large Page\r
- return Entry.Value & 0xFFFF0000;\r
- } else if ((Entry.Value & 0x2) == 2) { // Small Page\r
- return Entry.Value & 0xFFFFF000;\r
- } else {\r
- return 0;\r
- }\r
- } else {\r
- ASSERT(0);\r
- return 0;\r
- }\r
-}\r
-\r
-UINT32\r
-MmuEntryGetSize (\r
- IN MMU_ENTRY Entry\r
- )\r
-{\r
- if (Entry.Level == Level1) {\r
- if ((Entry.Value & 0x3) == 0) {\r
- return 0;\r
- } else if ((Entry.Value & 0x3) == 2) {\r
- if (Entry.Value & (1 << 18))\r
- return 16*SIZE_1MB;\r
- else\r
- return SIZE_1MB;\r
- } else if ((Entry.Value & 0x3) == 1) { // Level2 Table split 1MB section\r
- return SIZE_1MB;\r
- } else {\r
- DEBUG((EFI_D_ERROR, "MmuEntryGetSize: Value:0x%X",Entry.Value));\r
- ASSERT(0);\r
- return 0;\r
- }\r
- } else if (Entry.Level == Level2) {\r
- if ((Entry.Value & 0x3) == 0) { // Ignored\r
- return 0;\r
- } else if ((Entry.Value & 0x3) == 1) { // Large Page\r
- return SIZE_64KB;\r
- } else if ((Entry.Value & 0x2) == 2) { // Small Page\r
- return SIZE_4KB;\r
- } else {\r
- ASSERT(0);\r
- return 0;\r
- }\r
- } else {\r
- ASSERT(0);\r
- return 0;\r
- }\r
-}\r
-\r
-CONST CHAR8*\r
-MmuEntryGetAttributesName (\r
- IN MMU_ENTRY Entry\r
- )\r
-{\r
- UINT32 Value;\r
-\r
- if (Entry.Level == Level1) {\r
- Value = GET_TT_ATTRIBUTES(Entry.Value) | TT_DESCRIPTOR_SECTION_NS_MASK;\r
- if (Value == TT_DESCRIPTOR_SECTION_WRITE_BACK(0))\r
- return "TT_DESCRIPTOR_SECTION_WRITE_BACK";\r
- else if (Value == TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0))\r
- return "TT_DESCRIPTOR_SECTION_WRITE_THROUGH";\r
- else if (Value == TT_DESCRIPTOR_SECTION_DEVICE(0))\r
- return "TT_DESCRIPTOR_SECTION_DEVICE";\r
- else if (Value == TT_DESCRIPTOR_SECTION_UNCACHED(0))\r
- return "TT_DESCRIPTOR_SECTION_UNCACHED";\r
- else if (Value == TT_DESCRIPTOR_SECTION_STRONGLY_ORDER)\r
- return "TT_DESCRIPTOR_SECTION_STRONGLY_ORDERED";\r
- else {\r
- return "SectionUnknown";\r
- }\r
- } else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page\r
- Value = GET_TT_PAGE_ATTRIBUTES(Entry.Value);\r
- if (Value == TT_DESCRIPTOR_PAGE_WRITE_BACK)\r
- return "TT_DESCRIPTOR_PAGE_WRITE_BACK";\r
- else if (Value == TT_DESCRIPTOR_PAGE_WRITE_THROUGH)\r
- return "TT_DESCRIPTOR_PAGE_WRITE_THROUGH";\r
- else if (Value == TT_DESCRIPTOR_PAGE_DEVICE)\r
- return "TT_DESCRIPTOR_PAGE_DEVICE";\r
- else if (Value == TT_DESCRIPTOR_PAGE_UNCACHED)\r
- return "TT_DESCRIPTOR_PAGE_UNCACHED";\r
- else if (Value == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER)\r
- return "TT_DESCRIPTOR_PAGE_STRONGLY_ORDERED";\r
- else {\r
- return "PageUnknown";\r
- }\r
- } else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page\r
- Value = GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value);\r
- if (Value == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK)\r
- return "TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK";\r
- else if (Value == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH)\r
- return "TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH";\r
- else if (Value == TT_DESCRIPTOR_LARGEPAGE_DEVICE)\r
- return "TT_DESCRIPTOR_LARGEPAGE_DEVICE";\r
- else if (Value == TT_DESCRIPTOR_LARGEPAGE_UNCACHED)\r
- return "TT_DESCRIPTOR_LARGEPAGE_UNCACHED";\r
- else {\r
- return "LargePageUnknown";\r
- }\r
- } else {\r
- ASSERT(0);\r
- return "";\r
- }\r
-}\r
-\r
-UINT32\r
-MmuEntryGetAttributes (\r
- IN MMU_ENTRY Entry\r
- )\r
-{\r
- if (Entry.Level == Level1) {\r
- if ((Entry.Value & 0x3) == 0) {\r
- return 0;\r
- } else if ((Entry.Value & 0x3) == 2) {\r
- return GET_TT_ATTRIBUTES(Entry.Value);\r
- } else {\r
- return 0;\r
- }\r
- } else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page\r
- if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_BACK)\r
- return TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
- else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_THROUGH)\r
- return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);\r
- else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_DEVICE)\r
- return TT_DESCRIPTOR_SECTION_DEVICE(0);\r
- else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_UNCACHED)\r
- return TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
- else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER)\r
- return TT_DESCRIPTOR_SECTION_STRONGLY_ORDER;\r
- else {\r
- return 0;\r
- }\r
- } else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page\r
- if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK)\r
- return TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
- else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH)\r
- return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);\r
- else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_DEVICE)\r
- return TT_DESCRIPTOR_SECTION_DEVICE(0);\r
- else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_UNCACHED)\r
- return TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
- else {\r
- return 0;\r
- }\r
- } else {\r
- return 0;\r
- }\r
-}\r
-\r
-\r
-MMU_ENTRY\r
-DumpMmuLevel (\r
- IN MMU_LEVEL Level,\r
- IN UINT32* Table,\r
- IN MMU_ENTRY PreviousEntry\r
- )\r
-{\r
- UINT32 Index = 0, Count;\r
- MMU_ENTRY LastEntry, Entry;\r
-\r
- ASSERT((Level == Level1) || (Level == Level2));\r
-\r
- if (Level == Level1) Count = 4096;\r
- else Count = 256;\r
-\r
- // At Level1, we will get into this function because PreviousEntry is not valid\r
- if (!MmuEntryIsValidAddress((MMU_LEVEL)(Level-1),PreviousEntry.Value)) {\r
- // Find the first valid address\r
- for (; (Index < Count) && (!MmuEntryIsValidAddress(Level,Table[Index])); Index++);\r
-\r
- LastEntry = MmuEntryCreate(Level,Table,Index);\r
- Index++;\r
- } else {\r
- LastEntry = PreviousEntry;\r
- }\r
-\r
- for (; Index < Count; Index++) {\r
- Entry = MmuEntryCreate(Level,Table,Index);\r
- if ((Level == Level1) && ((Entry.Value & 0x3) == 1)) { // We have got a Level2 table redirection\r
- LastEntry = DumpMmuLevel(Level2,(UINT32*)(Entry.Value & 0xFFFFFC00),LastEntry);\r
- } else if (!MmuEntryIsValidAddress(Level,Table[Index])) {\r
- if (MmuEntryIsValidAddress(LastEntry.Level,LastEntry.Value)) {\r
- AsciiPrint("0x%08X-0x%08X\t%a\n",\r
- MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,\r
- MmuEntryGetAttributesName(LastEntry));\r
- }\r
- LastEntry = Entry;\r
- } else {\r
- if (MmuEntryGetAttributes(LastEntry) != MmuEntryGetAttributes(Entry)) {\r
- if (MmuEntryIsValidAddress(Level,LastEntry.Value)) {\r
- AsciiPrint("0x%08X-0x%08X\t%a\n",\r
- MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,\r
- MmuEntryGetAttributesName(LastEntry));\r
- }\r
- LastEntry = Entry;\r
- } else {\r
- ASSERT(LastEntry.Value != 0);\r
- }\r
- }\r
- PreviousEntry = Entry;\r
- }\r
-\r
- if ((Level == Level1) && (LastEntry.Index != Index) && MmuEntryIsValidAddress(Level,LastEntry.Value)) {\r
- AsciiPrint("0x%08X-0x%08X\t%a\n",\r
- MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,\r
- MmuEntryGetAttributesName(LastEntry));\r
- }\r
-\r
- return LastEntry;\r
-}\r
-\r
-\r
-EFI_STATUS\r
-EblDumpMmu (\r
- IN UINTN Argc,\r
- IN CHAR8 **Argv\r
- )\r
-{\r
- UINT32 *TTEntry;\r
- MMU_ENTRY NoEntry;\r
-\r
- TTEntry = ArmGetTTBR0BaseAddress();\r
-\r
- AsciiPrint ("\nTranslation Table:0x%X\n",TTEntry);\r
- AsciiPrint ("Address Range\t\tAttributes\n");\r
- AsciiPrint ("____________________________________________________\n");\r
-\r
- NoEntry.Level = (MMU_LEVEL)200;\r
- DumpMmuLevel(Level1,TTEntry,NoEntry);\r
-\r
- return EFI_SUCCESS;\r
-}\r
--- /dev/null
+/** @file\r
+* Main file supporting the transition to PEI Core in Normal World for Versatile Express\r
+*\r
+* Copyright (c) 2012, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <Library/PrintLib.h>\r
+#include <Library/SerialPortLib.h>\r
+\r
+#include "PrePeiCore.h"\r
+\r
+VOID\r
+PeiCommonExceptionEntry (\r
+ IN UINT32 Entry,\r
+ IN UINTN LR\r
+ )\r
+{\r
+ CHAR8 Buffer[100];\r
+ UINTN CharCount;\r
+\r
+ switch (Entry) {\r
+ case 0:\r
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR);\r
+ break;\r
+ case 1:\r
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR);\r
+ break;\r
+ case 2:\r
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR);\r
+ break;\r
+ case 3:\r
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR);\r
+ break;\r
+ case 4:\r
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR);\r
+ break;\r
+ case 5:\r
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR);\r
+ break;\r
+ case 6:\r
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR);\r
+ break;\r
+ case 7:\r
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR);\r
+ break;\r
+ default:\r
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR);\r
+ break;\r
+ }\r
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
+ while(1);\r
+}\r
+\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <AutoGen.h>\r
+\r
+#start of the code section\r
+.text\r
+.align 5\r
+\r
+# IMPORT\r
+GCC_ASM_IMPORT(PeiCommonExceptionEntry)\r
+\r
+# EXPORT\r
+GCC_ASM_EXPORT(PeiVectorTable)\r
+\r
+//============================================================\r
+//Default Exception Handlers\r
+//============================================================\r
+ \r
+ \r
+ASM_PFX(PeiVectorTable):\r
+ b _DefaultResetHandler\r
+ b _DefaultUndefined\r
+ b _DefaultSWI\r
+ b _DefaultPrefetchAbort\r
+ b _DefaultDataAbort\r
+ b _DefaultReserved\r
+ b _DefaultIrq\r
+ b _DefaultFiq\r
+\r
+//\r
+// Default Exception handlers: There is no plan to return from any of these exceptions.\r
+// No context saving at all.\r
+//\r
+_DefaultResetHandler:\r
+ mov r1, lr\r
+ # Switch to SVC for common stack\r
+ cps #0x13\r
+ mov r0, #0\r
+ blx ASM_PFX(PeiCommonExceptionEntry)\r
+\r
+_DefaultUndefined:\r
+ sub r1, LR, #4\r
+ # Switch to SVC for common stack\r
+ cps #0x13\r
+ mov r0, #1\r
+ blx ASM_PFX(PeiCommonExceptionEntry)\r
+\r
+_DefaultSWI:\r
+ sub r1, LR, #4\r
+ # Switch to SVC for common stack\r
+ cps #0x13\r
+ mov r0, #2\r
+ blx ASM_PFX(PeiCommonExceptionEntry)\r
+\r
+_DefaultPrefetchAbort:\r
+ sub r1, LR, #4\r
+ # Switch to SVC for common stack\r
+ cps #0x13\r
+ mov r0, #3\r
+ blx ASM_PFX(PeiCommonExceptionEntry)\r
+\r
+_DefaultDataAbort:\r
+ sub r1, LR, #8\r
+ # Switch to SVC for common stack\r
+ cps #0x13\r
+ mov r0, #4\r
+ blx ASM_PFX(PeiCommonExceptionEntry)\r
+\r
+_DefaultReserved:\r
+ mov r1, lr\r
+ # Switch to SVC for common stack\r
+ cps #0x13\r
+ mov r0, #5\r
+ blx ASM_PFX(PeiCommonExceptionEntry)\r
+\r
+_DefaultIrq:\r
+ sub r1, LR, #4\r
+ # Switch to SVC for common stack\r
+ cps #0x13\r
+ mov r0, #6\r
+ blx ASM_PFX(PeiCommonExceptionEntry)\r
+\r
+_DefaultFiq:\r
+ sub r1, LR, #4\r
+ # Switch to SVC for common stack\r
+ cps #0x13\r
+ mov r0, #7\r
+ blx ASM_PFX(PeiCommonExceptionEntry)\r
+\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <AutoGen.h>\r
+\r
+ IMPORT PeiCommonExceptionEntry\r
+ EXPORT PeiVectorTable\r
+ \r
+ PRESERVE8\r
+ AREA PrePeiCoreException, CODE, READONLY, CODEALIGN, ALIGN=5\r
+\r
+//============================================================\r
+//Default Exception Handlers\r
+//============================================================\r
+ \r
+ \r
+PeiVectorTable\r
+ b _DefaultResetHandler\r
+ b _DefaultUndefined\r
+ b _DefaultSWI\r
+ b _DefaultPrefetchAbort\r
+ b _DefaultDataAbort\r
+ b _DefaultReserved\r
+ b _DefaultIrq\r
+ b _DefaultFiq\r
+\r
+//\r
+// Default Exception handlers: There is no plan to return from any of these exceptions.\r
+// No context saving at all.\r
+//\r
+_DefaultResetHandler\r
+ mov r1, lr\r
+ cps #0x13 ; Switch to SVC for common stack\r
+ mov r0, #0\r
+ blx PeiCommonExceptionEntry\r
+\r
+_DefaultUndefined\r
+ sub r1, LR, #4\r
+ cps #0x13 ; Switch to SVC for common stack\r
+ mov r0, #1\r
+ blx PeiCommonExceptionEntry\r
+\r
+_DefaultSWI\r
+ sub r1, LR, #4\r
+ cps #0x13 ; Switch to SVC for common stack\r
+ mov r0, #2\r
+ blx PeiCommonExceptionEntry\r
+\r
+_DefaultPrefetchAbort\r
+ sub r1, LR, #4\r
+ cps #0x13 ; Switch to SVC for common stack\r
+ mov r0, #3\r
+ blx PeiCommonExceptionEntry\r
+\r
+_DefaultDataAbort\r
+ sub r1, LR, #8\r
+ cps #0x13 ; Switch to SVC for common stack\r
+ mov r0, #4\r
+ blx PeiCommonExceptionEntry\r
+\r
+_DefaultReserved\r
+ mov r1, lr\r
+ cps #0x13 ; Switch to SVC for common stack\r
+ mov r0, #5\r
+ blx PeiCommonExceptionEntry\r
+ \r
+_DefaultIrq\r
+ sub r1, LR, #4\r
+ cps #0x13 ; Switch to SVC for common stack\r
+ mov r0, #6\r
+ blx PeiCommonExceptionEntry\r
+\r
+_DefaultFiq\r
+ sub r1, LR, #4\r
+ cps #0x13 ; Switch to SVC for common stack\r
+ mov r0, #7\r
+ blx PeiCommonExceptionEntry\r
+\r
+ END\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_IMPORT(CEntryPoint)\r
+GCC_ASM_IMPORT(ArmReadMpidr)\r
+GCC_ASM_EXPORT(_ModuleEntryPoint)\r
+\r
+StartupAddr: .word CEntryPoint\r
+\r
+ASM_PFX(_ModuleEntryPoint):\r
+ // Identify CPU ID\r
+ bl ASM_PFX(ArmReadMpidr)\r
+ // Get ID of this CPU in Multicore system\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
+ and r5, r0, r1\r
+ \r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
+ add r1, r1, r2\r
+\r
+ // Is it the Primary Core ?\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
+ cmp r5, r3\r
+ beq _SetupPrimaryCoreStack\r
+\r
+_SetupSecondaryCoreStack:\r
+ // r1 contains the base of the secondary stacks\r
+\r
+ // Get the Core Position (ClusterId * 4) + CoreId\r
+ GetCorePositionFromMpId(r0, r5, r2)\r
+ // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
+ add r0, r0, #1\r
+\r
+ // StackOffset = CorePos * StackSize\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r2)\r
+ mul r0, r0, r2\r
+ // SP = StackBase + StackOffset\r
+ add sp, r1, r0\r
+\r
+_PrepareArguments:\r
+ // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r
+ LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), r2)\r
+ add r2, r2, #4\r
+ ldr r1, [r2]\r
+\r
+ // Move sec startup address into a data register\r
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ ldr r3, StartupAddr\r
+ \r
+ // Jump to PrePeiCore C code\r
+ // r0 = mp_id\r
+ // r1 = pei_core_address\r
+ mov r0, r5\r
+ blx r3\r
+\r
+_SetupPrimaryCoreStack:\r
+ // r1 contains the top of the primary stack\r
+ LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r2)\r
+\r
+ // The reserved space for global variable must be 8-bytes aligned for pushing\r
+ // 64-bit variable on the stack\r
+ SetPrimaryStack (r1, r2, r3)\r
+ b _PrepareArguments\r
+\r
+_NeverReturn:\r
+ b _NeverReturn\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+ \r
+ IMPORT CEntryPoint\r
+ IMPORT ArmReadMpidr\r
+ EXPORT _ModuleEntryPoint\r
+ \r
+ PRESERVE8\r
+ AREA PrePeiCoreEntryPoint, CODE, READONLY\r
+ \r
+StartupAddr DCD CEntryPoint\r
+\r
+_ModuleEntryPoint\r
+ // Identify CPU ID\r
+ bl ArmReadMpidr\r
+ // Get ID of this CPU in Multicore system\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
+ and r5, r0, r1\r
+ \r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
+ add r1, r1, r2\r
+\r
+ // Is it the Primary Core ?\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
+ cmp r5, r3\r
+ beq _SetupPrimaryCoreStack\r
+\r
+_SetupSecondaryCoreStack\r
+ // r1 contains the base of the secondary stacks\r
+\r
+ // Get the Core Position (ClusterId * 4) + CoreId\r
+ GetCorePositionFromMpId(r0, r5, r2)\r
+ // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
+ add r0, r0, #1\r
+\r
+ // StackOffset = CorePos * StackSize\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r2)\r
+ mul r0, r0, r2\r
+ // SP = StackBase + StackOffset\r
+ add sp, r1, r0\r
+\r
+_PrepareArguments\r
+ // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r
+ LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), r2)\r
+ add r2, r2, #4\r
+ ldr r1, [r2]\r
+\r
+ // Move sec startup address into a data register\r
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ ldr r3, StartupAddr\r
+ \r
+ // Jump to PrePeiCore C code\r
+ // r0 = mp_id\r
+ // r1 = pei_core_address\r
+ mov r0, r5\r
+ blx r3\r
+\r
+_SetupPrimaryCoreStack\r
+ // r1 contains the top of the primary stack\r
+ LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r2)\r
+\r
+ // The reserved space for global variable must be 8-bytes aligned for pushing\r
+ // 64-bit variable on the stack\r
+ SetPrimaryStack (r1, r2, r3)\r
+ b _PrepareArguments\r
+\r
+_NeverReturn\r
+ b _NeverReturn\r
+\r
+ END\r
--- /dev/null
+#------------------------------------------------------------------------------ \r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+ \r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(SecSwitchStack)\r
+\r
+\r
+ \r
+#/**\r
+# This allows the caller to switch the stack and return\r
+#\r
+# @param StackDelta Signed amount by which to modify the stack pointer\r
+#\r
+# @return Nothing. Goes to the Entry Point passing in the new parameters\r
+#\r
+#**/\r
+#VOID\r
+#EFIAPI\r
+#SecSwitchStack (\r
+# VOID *StackDelta\r
+# )#\r
+#\r
+ASM_PFX(SecSwitchStack): \r
+ mov R1, R13\r
+ add R1, R0, R1\r
+ mov R13, R1\r
+ bx LR\r
+ \r
+ \r
+ \r
--- /dev/null
+;------------------------------------------------------------------------------ \r
+;\r
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+ \r
+ EXPORT SecSwitchStack\r
+ \r
+ AREA Switch_Stack, CODE, READONLY\r
+ \r
+;/**\r
+; This allows the caller to switch the stack and return\r
+;\r
+; @param StackDelta Signed amount by which to modify the stack pointer\r
+;\r
+; @return Nothing. Goes to the Entry Point passing in the new parameters\r
+;\r
+;**/\r
+;VOID\r
+;EFIAPI\r
+;SecSwitchStack (\r
+; VOID *StackDelta\r
+; );\r
+;\r
+SecSwitchStack \r
+ MOV R1, SP\r
+ ADD R1, R0, R1\r
+ MOV SP, R1\r
+ BX LR\r
+ END\r
+++ /dev/null
-//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-// \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <AutoGen.h>\r
-\r
-#start of the code section\r
-.text\r
-.align 5\r
-\r
-# IMPORT\r
-GCC_ASM_IMPORT(PeiCommonExceptionEntry)\r
-\r
-# EXPORT\r
-GCC_ASM_EXPORT(PeiVectorTable)\r
-\r
-//============================================================\r
-//Default Exception Handlers\r
-//============================================================\r
- \r
- \r
-ASM_PFX(PeiVectorTable):\r
- b _DefaultResetHandler\r
- b _DefaultUndefined\r
- b _DefaultSWI\r
- b _DefaultPrefetchAbort\r
- b _DefaultDataAbort\r
- b _DefaultReserved\r
- b _DefaultIrq\r
- b _DefaultFiq\r
-\r
-//\r
-// Default Exception handlers: There is no plan to return from any of these exceptions.\r
-// No context saving at all.\r
-//\r
-_DefaultResetHandler:\r
- mov r1, lr\r
- # Switch to SVC for common stack\r
- cps #0x13\r
- mov r0, #0\r
- blx ASM_PFX(PeiCommonExceptionEntry)\r
-\r
-_DefaultUndefined:\r
- sub r1, LR, #4\r
- # Switch to SVC for common stack\r
- cps #0x13\r
- mov r0, #1\r
- blx ASM_PFX(PeiCommonExceptionEntry)\r
-\r
-_DefaultSWI:\r
- sub r1, LR, #4\r
- # Switch to SVC for common stack\r
- cps #0x13\r
- mov r0, #2\r
- blx ASM_PFX(PeiCommonExceptionEntry)\r
-\r
-_DefaultPrefetchAbort:\r
- sub r1, LR, #4\r
- # Switch to SVC for common stack\r
- cps #0x13\r
- mov r0, #3\r
- blx ASM_PFX(PeiCommonExceptionEntry)\r
-\r
-_DefaultDataAbort:\r
- sub r1, LR, #8\r
- # Switch to SVC for common stack\r
- cps #0x13\r
- mov r0, #4\r
- blx ASM_PFX(PeiCommonExceptionEntry)\r
-\r
-_DefaultReserved:\r
- mov r1, lr\r
- # Switch to SVC for common stack\r
- cps #0x13\r
- mov r0, #5\r
- blx ASM_PFX(PeiCommonExceptionEntry)\r
-\r
-_DefaultIrq:\r
- sub r1, LR, #4\r
- # Switch to SVC for common stack\r
- cps #0x13\r
- mov r0, #6\r
- blx ASM_PFX(PeiCommonExceptionEntry)\r
-\r
-_DefaultFiq:\r
- sub r1, LR, #4\r
- # Switch to SVC for common stack\r
- cps #0x13\r
- mov r0, #7\r
- blx ASM_PFX(PeiCommonExceptionEntry)\r
-\r
+++ /dev/null
-//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-// \r
-// This program and the accompanying materials \r
-// are licensed and made available under the terms and conditions of the BSD License \r
-// which accompanies this distribution. The full text of the license may be found at \r
-// http://opensource.org/licenses/bsd-license.php \r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <AutoGen.h>\r
-\r
- IMPORT PeiCommonExceptionEntry\r
- EXPORT PeiVectorTable\r
- \r
- PRESERVE8\r
- AREA PrePeiCoreException, CODE, READONLY, CODEALIGN, ALIGN=5\r
-\r
-//============================================================\r
-//Default Exception Handlers\r
-//============================================================\r
- \r
- \r
-PeiVectorTable\r
- b _DefaultResetHandler\r
- b _DefaultUndefined\r
- b _DefaultSWI\r
- b _DefaultPrefetchAbort\r
- b _DefaultDataAbort\r
- b _DefaultReserved\r
- b _DefaultIrq\r
- b _DefaultFiq\r
-\r
-//\r
-// Default Exception handlers: There is no plan to return from any of these exceptions.\r
-// No context saving at all.\r
-//\r
-_DefaultResetHandler\r
- mov r1, lr\r
- cps #0x13 ; Switch to SVC for common stack\r
- mov r0, #0\r
- blx PeiCommonExceptionEntry\r
-\r
-_DefaultUndefined\r
- sub r1, LR, #4\r
- cps #0x13 ; Switch to SVC for common stack\r
- mov r0, #1\r
- blx PeiCommonExceptionEntry\r
-\r
-_DefaultSWI\r
- sub r1, LR, #4\r
- cps #0x13 ; Switch to SVC for common stack\r
- mov r0, #2\r
- blx PeiCommonExceptionEntry\r
-\r
-_DefaultPrefetchAbort\r
- sub r1, LR, #4\r
- cps #0x13 ; Switch to SVC for common stack\r
- mov r0, #3\r
- blx PeiCommonExceptionEntry\r
-\r
-_DefaultDataAbort\r
- sub r1, LR, #8\r
- cps #0x13 ; Switch to SVC for common stack\r
- mov r0, #4\r
- blx PeiCommonExceptionEntry\r
-\r
-_DefaultReserved\r
- mov r1, lr\r
- cps #0x13 ; Switch to SVC for common stack\r
- mov r0, #5\r
- blx PeiCommonExceptionEntry\r
- \r
-_DefaultIrq\r
- sub r1, LR, #4\r
- cps #0x13 ; Switch to SVC for common stack\r
- mov r0, #6\r
- blx PeiCommonExceptionEntry\r
-\r
-_DefaultFiq\r
- sub r1, LR, #4\r
- cps #0x13 ; Switch to SVC for common stack\r
- mov r0, #7\r
- blx PeiCommonExceptionEntry\r
-\r
- END\r
/** @file\r
* Main file supporting the transition to PEI Core in Normal World for Versatile Express\r
*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
* \r
* This program and the accompanying materials \r
* are licensed and made available under the terms and conditions of the BSD License \r
\r
#include <Library/BaseLib.h>\r
#include <Library/DebugAgentLib.h>\r
-#include <Library/PrintLib.h>\r
#include <Library/ArmLib.h>\r
-#include <Library/SerialPortLib.h>\r
\r
#include <Ppi/ArmGlobalVariable.h>\r
\r
)\r
{\r
//Clean Data cache\r
- ArmCleanInvalidateDataCache();\r
+ ArmCleanInvalidateDataCache ();\r
\r
//Invalidate instruction cache\r
- ArmInvalidateInstructionCache();\r
+ ArmInvalidateInstructionCache ();\r
\r
// Enable Instruction & Data caches\r
ArmEnableDataCache ();\r
// as Non-secure interface is already enabled in Secure world.\r
//\r
\r
- // Write VBAR - The Vector table must be 32-byte aligned\r
- ASSERT(((UINT32)PeiVectorTable & ((1 << 5)-1)) == 0);\r
- ArmWriteVBar((UINT32)PeiVectorTable);\r
+ // Write VBAR - The Exception Vector table must be aligned to its requirement\r
+ ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
+ ArmWriteVBar ((UINTN)PeiVectorTable);\r
\r
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r
\r
return EFI_SUCCESS;\r
}\r
\r
-VOID\r
-PeiCommonExceptionEntry (\r
- IN UINT32 Entry,\r
- IN UINT32 LR\r
- )\r
-{\r
- CHAR8 Buffer[100];\r
- UINTN CharCount;\r
-\r
- switch (Entry) {\r
- case 0:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR);\r
- break;\r
- case 1:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR);\r
- break;\r
- case 2:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR);\r
- break;\r
- case 3:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR);\r
- break;\r
- case 4:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR);\r
- break;\r
- case 5:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR);\r
- break;\r
- case 6:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR);\r
- break;\r
- case 7:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR);\r
- break;\r
- default:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR);\r
- break;\r
- }\r
- SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
- while(1);\r
-}\r
IN UINTN MpId\r
);\r
\r
+VOID\r
+PeiCommonExceptionEntry (\r
+ IN UINT32 Entry,\r
+ IN UINTN LR\r
+ );\r
+\r
#endif\r
+++ /dev/null
-//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-// \r
-// This program and the accompanying materials \r
-// are licensed and made available under the terms and conditions of the BSD License \r
-// which accompanies this distribution. The full text of the license may be found at \r
-// http://opensource.org/licenses/bsd-license.php \r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_IMPORT(CEntryPoint)\r
-GCC_ASM_IMPORT(ArmReadMpidr)\r
-GCC_ASM_EXPORT(_ModuleEntryPoint)\r
-\r
-StartupAddr: .word CEntryPoint\r
-\r
-ASM_PFX(_ModuleEntryPoint):\r
- // Identify CPU ID\r
- bl ASM_PFX(ArmReadMpidr)\r
- // Get ID of this CPU in Multicore system\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
- and r5, r0, r1\r
- \r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
- add r1, r1, r2\r
-\r
- // Is it the Primary Core ?\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
- cmp r5, r3\r
- beq _SetupPrimaryCoreStack\r
-\r
-_SetupSecondaryCoreStack:\r
- // r1 contains the base of the secondary stacks\r
-\r
- // Get the Core Position (ClusterId * 4) + CoreId\r
- GetCorePositionFromMpId(r0, r5, r2)\r
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
- add r0, r0, #1\r
-\r
- // StackOffset = CorePos * StackSize\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r2)\r
- mul r0, r0, r2\r
- // SP = StackBase + StackOffset\r
- add sp, r1, r0\r
-\r
-_PrepareArguments:\r
- // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r
- LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), r2)\r
- add r2, r2, #4\r
- ldr r1, [r2]\r
-\r
- // Move sec startup address into a data register\r
- // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
- ldr r3, StartupAddr\r
- \r
- // Jump to PrePeiCore C code\r
- // r0 = mp_id\r
- // r1 = pei_core_address\r
- mov r0, r5\r
- blx r3\r
-\r
-_SetupPrimaryCoreStack:\r
- // r1 contains the top of the primary stack\r
- LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r2)\r
-\r
- // The reserved space for global variable must be 8-bytes aligned for pushing\r
- // 64-bit variable on the stack\r
- SetPrimaryStack (r1, r2, r3)\r
- b _PrepareArguments\r
-\r
-_NeverReturn:\r
- b _NeverReturn\r
+++ /dev/null
-//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-// \r
-// This program and the accompanying materials \r
-// are licensed and made available under the terms and conditions of the BSD License \r
-// which accompanies this distribution. The full text of the license may be found at \r
-// http://opensource.org/licenses/bsd-license.php \r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
- \r
- IMPORT CEntryPoint\r
- IMPORT ArmReadMpidr\r
- EXPORT _ModuleEntryPoint\r
- \r
- PRESERVE8\r
- AREA PrePeiCoreEntryPoint, CODE, READONLY\r
- \r
-StartupAddr DCD CEntryPoint\r
-\r
-_ModuleEntryPoint\r
- // Identify CPU ID\r
- bl ArmReadMpidr\r
- // Get ID of this CPU in Multicore system\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
- and r5, r0, r1\r
- \r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
- add r1, r1, r2\r
-\r
- // Is it the Primary Core ?\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
- cmp r5, r3\r
- beq _SetupPrimaryCoreStack\r
-\r
-_SetupSecondaryCoreStack\r
- // r1 contains the base of the secondary stacks\r
-\r
- // Get the Core Position (ClusterId * 4) + CoreId\r
- GetCorePositionFromMpId(r0, r5, r2)\r
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
- add r0, r0, #1\r
-\r
- // StackOffset = CorePos * StackSize\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r2)\r
- mul r0, r0, r2\r
- // SP = StackBase + StackOffset\r
- add sp, r1, r0\r
-\r
-_PrepareArguments\r
- // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r
- LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), r2)\r
- add r2, r2, #4\r
- ldr r1, [r2]\r
-\r
- // Move sec startup address into a data register\r
- // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
- ldr r3, StartupAddr\r
- \r
- // Jump to PrePeiCore C code\r
- // r0 = mp_id\r
- // r1 = pei_core_address\r
- mov r0, r5\r
- blx r3\r
-\r
-_SetupPrimaryCoreStack\r
- // r1 contains the top of the primary stack\r
- LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r2)\r
-\r
- // The reserved space for global variable must be 8-bytes aligned for pushing\r
- // 64-bit variable on the stack\r
- SetPrimaryStack (r1, r2, r3)\r
- b _PrepareArguments\r
-\r
-_NeverReturn\r
- b _NeverReturn\r
-\r
- END\r
MODULE_TYPE = SEC\r
VERSION_STRING = 1.0\r
\r
-[Sources.ARM]\r
- PrePeiCoreEntryPoint.asm | RVCT\r
- PrePeiCoreEntryPoint.S | GCC\r
- PrePeiCore.c\r
+[Sources.common]\r
MainMPCore.c\r
- SwitchStack.asm | RVCT\r
- SwitchStack.S | GCC\r
- Exception.asm | RVCT\r
- Exception.S | GCC\r
- \r
+ PrePeiCore.c\r
+\r
+[Sources.ARM]\r
+ Arm/ArchPrePeiCore.c\r
+ Arm/PrePeiCoreEntryPoint.asm | RVCT\r
+ Arm/PrePeiCoreEntryPoint.S | GCC\r
+ Arm/SwitchStack.asm | RVCT\r
+ Arm/SwitchStack.S | GCC\r
+ Arm/Exception.asm | RVCT\r
+ Arm/Exception.S | GCC\r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
MdeModulePkg/MdeModulePkg.dec\r
MODULE_TYPE = SEC\r
VERSION_STRING = 1.0\r
\r
-[Sources.ARM]\r
- PrePeiCoreEntryPoint.asm | RVCT\r
- PrePeiCoreEntryPoint.S | GCC\r
+[Sources.common]\r
PrePeiCore.c\r
MainUniCore.c\r
- SwitchStack.asm | RVCT\r
- SwitchStack.S | GCC\r
- Exception.asm | RVCT\r
- Exception.S | GCC\r
+\r
+[Sources.ARM]\r
+ Arm/ArchPrePeiCore.c\r
+ Arm/PrePeiCoreEntryPoint.asm | RVCT\r
+ Arm/PrePeiCoreEntryPoint.S | GCC\r
+ Arm/SwitchStack.asm | RVCT\r
+ Arm/SwitchStack.S | GCC\r
+ Arm/Exception.asm | RVCT\r
+ Arm/Exception.S | GCC\r
\r
[Packages]\r
MdePkg/MdePkg.dec\r
+++ /dev/null
-#------------------------------------------------------------------------------ \r
-#\r
-# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
-# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#------------------------------------------------------------------------------\r
- \r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(SecSwitchStack)\r
-\r
-\r
- \r
-#/**\r
-# This allows the caller to switch the stack and return\r
-#\r
-# @param StackDelta Signed amount by which to modify the stack pointer\r
-#\r
-# @return Nothing. Goes to the Entry Point passing in the new parameters\r
-#\r
-#**/\r
-#VOID\r
-#EFIAPI\r
-#SecSwitchStack (\r
-# VOID *StackDelta\r
-# )#\r
-#\r
-ASM_PFX(SecSwitchStack): \r
- mov R1, R13\r
- add R1, R0, R1\r
- mov R13, R1\r
- bx LR\r
- \r
- \r
- \r
+++ /dev/null
-;------------------------------------------------------------------------------ \r
-;\r
-; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
-; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-;------------------------------------------------------------------------------\r
- \r
- EXPORT SecSwitchStack\r
- \r
- AREA Switch_Stack, CODE, READONLY\r
- \r
-;/**\r
-; This allows the caller to switch the stack and return\r
-;\r
-; @param StackDelta Signed amount by which to modify the stack pointer\r
-;\r
-; @return Nothing. Goes to the Entry Point passing in the new parameters\r
-;\r
-;**/\r
-;VOID\r
-;EFIAPI\r
-;SecSwitchStack (\r
-; VOID *StackDelta\r
-; );\r
-;\r
-SecSwitchStack \r
- MOV R1, SP\r
- ADD R1, R0, R1\r
- MOV SP, R1\r
- BX LR\r
- END\r
--- /dev/null
+//\r
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+\r
+#include <Chipset/ArmV7.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_IMPORT(CEntryPoint)\r
+GCC_ASM_IMPORT(ArmReadMpidr)\r
+GCC_ASM_IMPORT(ArmPlatformStackSet)\r
+GCC_ASM_EXPORT(_ModuleEntryPoint)\r
+\r
+StartupAddr: .word CEntryPoint\r
+\r
+\r
+ASM_PFX(_ModuleEntryPoint):\r
+ // Get ID of this CPU in Multicore system\r
+ bl ASM_PFX(ArmReadMpidr)\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
+ and r6, r0, r1\r
+\r
+_SetSVCMode:\r
+ // Enter SVC mode, Disable FIQ and IRQ\r
+ mov r1, #(CPSR_MODE_SVC | CPSR_IRQ | CPSR_FIQ)\r
+ msr CPSR_c, r1\r
+\r
+// Check if we can install the stack at the top of the System Memory or if we need\r
+// to install the stacks at the bottom of the Firmware Device (case the FD is located\r
+// at the top of the DRAM)\r
+_SetupStackPosition:\r
+ // Compute Top of System Memory\r
+ LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), r2)\r
+ sub r2, r2, #1\r
+ add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize\r
+\r
+ // Calculate Top of the Firmware Device\r
+ LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), r2)\r
+ LoadConstantToReg (FixedPcdGet32(PcdFdSize), r3)\r
+ sub r3, r3, #1\r
+ add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize\r
+\r
+ // UEFI Memory Size (stacks are allocated in this region)\r
+ LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4)\r
+\r
+ //\r
+ // Reserve the memory for the UEFI region (contain stacks on its top)\r
+ //\r
+\r
+ // Calculate how much space there is between the top of the Firmware and the Top of the System Memory\r
+ subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop\r
+ bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM\r
+ cmp r0, r4\r
+ bge _SetupStack\r
+\r
+ // Case the top of stacks is the FdBaseAddress\r
+ mov r1, r2\r
+\r
+_SetupStack:\r
+ // r1 contains the top of the stack (and the UEFI Memory)\r
+\r
+ // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment\r
+ // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the\r
+ // top of the memory space)\r
+ adds r7, r1, #1\r
+ bcs _SetupOverflowStack\r
+\r
+_SetupAlignedStack:\r
+ mov r1, r7\r
+ b _GetBaseUefiMemory\r
+\r
+_SetupOverflowStack:\r
+ // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE\r
+ // aligned (4KB)\r
+ LoadConstantToReg (EFI_PAGE_MASK, r7)\r
+ and r7, r7, r1\r
+ sub r1, r1, r7\r
+\r
+_GetBaseUefiMemory:\r
+ // Calculate the Base of the UEFI Memory\r
+ sub r7, r1, r4\r
+\r
+_GetStackBase:\r
+ // r1 = The top of the Mpcore Stacks\r
+ // Stack for the primary core = PrimaryCoreStack\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
+ sub r8, r1, r2\r
+\r
+ // Stack for the secondary core = Number of Cores - 1\r
+ LoadConstantToReg (FixedPcdGet32(PcdCoreCount), r0)\r
+ sub r0, r0, #1\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r1)\r
+ mul r1, r1, r0\r
+ sub r8, r8, r1\r
+\r
+ // r8 = The base of the MpCore Stacks (primary stack & secondary stacks)\r
+ mov r0, r8\r
+ mov r1, r6\r
+ //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3)\r
+ bl ASM_PFX(ArmPlatformStackSet)\r
+\r
+ // Is it the Primary Core ?\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r4)\r
+ cmp r6, r4\r
+ bne _PrepareArguments\r
+\r
+_ReserveGlobalVariable:\r
+ LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r0)\r
+ // InitializePrimaryStack($GlobalVariableSize, $Tmp1)\r
+ InitializePrimaryStack(r0, r1)\r
+\r
+_PrepareArguments:\r
+ mov r0, r6\r
+ mov r1, r7\r
+ mov r2, r8\r
+ mov r3, sp\r
+\r
+ // Move sec startup address into a data register\r
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ ldr r4, StartupAddr\r
+\r
+ // Jump to PrePiCore C code\r
+ // r0 = MpId\r
+ // r1 = UefiMemoryBase\r
+ // r2 = StacksBase\r
+ // r3 = GlobalVariableBase\r
+ blx r4\r
+\r
+_NeverReturn:\r
+ b _NeverReturn\r
+\r
--- /dev/null
+//\r
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+\r
+#include <Chipset/ArmV7.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+ \r
+ IMPORT CEntryPoint\r
+ IMPORT ArmReadMpidr\r
+ IMPORT ArmPlatformStackSet\r
+ \r
+ EXPORT _ModuleEntryPoint\r
+\r
+ PRESERVE8\r
+ AREA PrePiCoreEntryPoint, CODE, READONLY\r
+ \r
+StartupAddr DCD CEntryPoint\r
+\r
+_ModuleEntryPoint\r
+ // Get ID of this CPU in Multicore system\r
+ bl ArmReadMpidr\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
+ and r6, r0, r1\r
+\r
+_SetSVCMode\r
+ // Enter SVC mode, Disable FIQ and IRQ\r
+ mov r1, #(CPSR_MODE_SVC :OR: CPSR_IRQ :OR: CPSR_FIQ)\r
+ msr CPSR_c, r1\r
+\r
+// Check if we can install the stack at the top of the System Memory or if we need\r
+// to install the stacks at the bottom of the Firmware Device (case the FD is located\r
+// at the top of the DRAM)\r
+_SetupStackPosition\r
+ // Compute Top of System Memory\r
+ LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), r2)\r
+ sub r2, r2, #1\r
+ add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize\r
+\r
+ // Calculate Top of the Firmware Device\r
+ LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), r2)\r
+ LoadConstantToReg (FixedPcdGet32(PcdFdSize), r3)\r
+ sub r3, r3, #1\r
+ add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize\r
+\r
+ // UEFI Memory Size (stacks are allocated in this region)\r
+ LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4)\r
+\r
+ //\r
+ // Reserve the memory for the UEFI region (contain stacks on its top)\r
+ //\r
+\r
+ // Calculate how much space there is between the top of the Firmware and the Top of the System Memory\r
+ subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop\r
+ bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM\r
+ cmp r0, r4\r
+ bge _SetupStack\r
+\r
+ // Case the top of stacks is the FdBaseAddress\r
+ mov r1, r2\r
+\r
+_SetupStack\r
+ // r1 contains the top of the stack (and the UEFI Memory)\r
+\r
+ // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment\r
+ // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the\r
+ // top of the memory space)\r
+ adds r7, r1, #1\r
+ bcs _SetupOverflowStack\r
+\r
+_SetupAlignedStack\r
+ mov r1, r7\r
+ b _GetBaseUefiMemory\r
+\r
+_SetupOverflowStack\r
+ // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE\r
+ // aligned (4KB)\r
+ LoadConstantToReg (EFI_PAGE_MASK, r7)\r
+ and r7, r7, r1\r
+ sub r1, r1, r7\r
+\r
+_GetBaseUefiMemory\r
+ // Calculate the Base of the UEFI Memory\r
+ sub r7, r1, r4\r
+\r
+_GetStackBase\r
+ // r1 = The top of the Mpcore Stacks\r
+ // Stack for the primary core = PrimaryCoreStack\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
+ sub r8, r1, r2\r
+\r
+ // Stack for the secondary core = Number of Cores - 1\r
+ LoadConstantToReg (FixedPcdGet32(PcdCoreCount), r0)\r
+ sub r0, r0, #1\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r1)\r
+ mul r1, r1, r0\r
+ sub r8, r8, r1\r
+\r
+ // r8 = The base of the MpCore Stacks (primary stack & secondary stacks)\r
+ mov r0, r8\r
+ mov r1, r6\r
+ //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3)\r
+ bl ArmPlatformStackSet\r
+\r
+ // Is it the Primary Core ?\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r4)\r
+ cmp r6, r4\r
+ bne _PrepareArguments\r
+\r
+_ReserveGlobalVariable\r
+ LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r0)\r
+ // InitializePrimaryStack($GlobalVariableSize, $Tmp1)\r
+ InitializePrimaryStack r0, r1\r
+\r
+_PrepareArguments\r
+ mov r0, r6\r
+ mov r1, r7\r
+ mov r2, r8\r
+ mov r3, sp\r
+\r
+ // Move sec startup address into a data register\r
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ ldr r4, StartupAddr\r
+\r
+ // Jump to PrePiCore C code\r
+ // r0 = MpId\r
+ // r1 = UefiMemoryBase\r
+ // r2 = StacksBase\r
+ // r3 = GlobalVariableBase\r
+ blx r4\r
+\r
+_NeverReturn\r
+ b _NeverReturn\r
+\r
+ END\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
-\r
-#include <Chipset/ArmV7.h>\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_IMPORT(CEntryPoint)\r
-GCC_ASM_IMPORT(ArmReadMpidr)\r
-GCC_ASM_IMPORT(ArmPlatformStackSet)\r
-GCC_ASM_EXPORT(_ModuleEntryPoint)\r
-\r
-StartupAddr: .word CEntryPoint\r
-\r
-\r
-ASM_PFX(_ModuleEntryPoint):\r
- // Get ID of this CPU in Multicore system\r
- bl ASM_PFX(ArmReadMpidr)\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
- and r6, r0, r1\r
-\r
-_SetSVCMode:\r
- // Enter SVC mode, Disable FIQ and IRQ\r
- mov r1, #(CPSR_MODE_SVC | CPSR_IRQ | CPSR_FIQ)\r
- msr CPSR_c, r1\r
-\r
-// Check if we can install the stack at the top of the System Memory or if we need\r
-// to install the stacks at the bottom of the Firmware Device (case the FD is located\r
-// at the top of the DRAM)\r
-_SetupStackPosition:\r
- // Compute Top of System Memory\r
- LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), r2)\r
- sub r2, r2, #1\r
- add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize\r
-\r
- // Calculate Top of the Firmware Device\r
- LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), r2)\r
- LoadConstantToReg (FixedPcdGet32(PcdFdSize), r3)\r
- sub r3, r3, #1\r
- add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize\r
-\r
- // UEFI Memory Size (stacks are allocated in this region)\r
- LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4)\r
-\r
- //\r
- // Reserve the memory for the UEFI region (contain stacks on its top)\r
- //\r
-\r
- // Calculate how much space there is between the top of the Firmware and the Top of the System Memory\r
- subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop\r
- bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM\r
- cmp r0, r4\r
- bge _SetupStack\r
-\r
- // Case the top of stacks is the FdBaseAddress\r
- mov r1, r2\r
-\r
-_SetupStack:\r
- // r1 contains the top of the stack (and the UEFI Memory)\r
-\r
- // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment\r
- // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the\r
- // top of the memory space)\r
- adds r7, r1, #1\r
- bcs _SetupOverflowStack\r
-\r
-_SetupAlignedStack:\r
- mov r1, r7\r
- b _GetBaseUefiMemory\r
-\r
-_SetupOverflowStack:\r
- // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE\r
- // aligned (4KB)\r
- LoadConstantToReg (EFI_PAGE_MASK, r7)\r
- and r7, r7, r1\r
- sub r1, r1, r7\r
-\r
-_GetBaseUefiMemory:\r
- // Calculate the Base of the UEFI Memory\r
- sub r7, r1, r4\r
-\r
-_GetStackBase:\r
- // r1 = The top of the Mpcore Stacks\r
- // Stack for the primary core = PrimaryCoreStack\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
- sub r8, r1, r2\r
-\r
- // Stack for the secondary core = Number of Cores - 1\r
- LoadConstantToReg (FixedPcdGet32(PcdCoreCount), r0)\r
- sub r0, r0, #1\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r1)\r
- mul r1, r1, r0\r
- sub r8, r8, r1\r
-\r
- // r8 = The base of the MpCore Stacks (primary stack & secondary stacks)\r
- mov r0, r8\r
- mov r1, r6\r
- //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3)\r
- bl ASM_PFX(ArmPlatformStackSet)\r
-\r
- // Is it the Primary Core ?\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r4)\r
- cmp r6, r4\r
- bne _PrepareArguments\r
-\r
-_ReserveGlobalVariable:\r
- LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r0)\r
- // InitializePrimaryStack($GlobalVariableSize, $Tmp1)\r
- InitializePrimaryStack(r0, r1)\r
-\r
-_PrepareArguments:\r
- mov r0, r6\r
- mov r1, r7\r
- mov r2, r8\r
- mov r3, sp\r
-\r
- // Move sec startup address into a data register\r
- // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
- ldr r4, StartupAddr\r
-\r
- // Jump to PrePiCore C code\r
- // r0 = MpId\r
- // r1 = UefiMemoryBase\r
- // r2 = StacksBase\r
- // r3 = GlobalVariableBase\r
- blx r4\r
-\r
-_NeverReturn:\r
- b _NeverReturn\r
-\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
-\r
-#include <Chipset/ArmV7.h>\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
- \r
- IMPORT CEntryPoint\r
- IMPORT ArmReadMpidr\r
- IMPORT ArmPlatformStackSet\r
- \r
- EXPORT _ModuleEntryPoint\r
-\r
- PRESERVE8\r
- AREA PrePiCoreEntryPoint, CODE, READONLY\r
- \r
-StartupAddr DCD CEntryPoint\r
-\r
-_ModuleEntryPoint\r
- // Get ID of this CPU in Multicore system\r
- bl ArmReadMpidr\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
- and r6, r0, r1\r
-\r
-_SetSVCMode\r
- // Enter SVC mode, Disable FIQ and IRQ\r
- mov r1, #(CPSR_MODE_SVC :OR: CPSR_IRQ :OR: CPSR_FIQ)\r
- msr CPSR_c, r1\r
-\r
-// Check if we can install the stack at the top of the System Memory or if we need\r
-// to install the stacks at the bottom of the Firmware Device (case the FD is located\r
-// at the top of the DRAM)\r
-_SetupStackPosition\r
- // Compute Top of System Memory\r
- LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), r2)\r
- sub r2, r2, #1\r
- add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize\r
-\r
- // Calculate Top of the Firmware Device\r
- LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), r2)\r
- LoadConstantToReg (FixedPcdGet32(PcdFdSize), r3)\r
- sub r3, r3, #1\r
- add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize\r
-\r
- // UEFI Memory Size (stacks are allocated in this region)\r
- LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4)\r
-\r
- //\r
- // Reserve the memory for the UEFI region (contain stacks on its top)\r
- //\r
-\r
- // Calculate how much space there is between the top of the Firmware and the Top of the System Memory\r
- subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop\r
- bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM\r
- cmp r0, r4\r
- bge _SetupStack\r
-\r
- // Case the top of stacks is the FdBaseAddress\r
- mov r1, r2\r
-\r
-_SetupStack\r
- // r1 contains the top of the stack (and the UEFI Memory)\r
-\r
- // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment\r
- // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the\r
- // top of the memory space)\r
- adds r7, r1, #1\r
- bcs _SetupOverflowStack\r
-\r
-_SetupAlignedStack\r
- mov r1, r7\r
- b _GetBaseUefiMemory\r
-\r
-_SetupOverflowStack\r
- // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE\r
- // aligned (4KB)\r
- LoadConstantToReg (EFI_PAGE_MASK, r7)\r
- and r7, r7, r1\r
- sub r1, r1, r7\r
-\r
-_GetBaseUefiMemory\r
- // Calculate the Base of the UEFI Memory\r
- sub r7, r1, r4\r
-\r
-_GetStackBase\r
- // r1 = The top of the Mpcore Stacks\r
- // Stack for the primary core = PrimaryCoreStack\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
- sub r8, r1, r2\r
-\r
- // Stack for the secondary core = Number of Cores - 1\r
- LoadConstantToReg (FixedPcdGet32(PcdCoreCount), r0)\r
- sub r0, r0, #1\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r1)\r
- mul r1, r1, r0\r
- sub r8, r8, r1\r
-\r
- // r8 = The base of the MpCore Stacks (primary stack & secondary stacks)\r
- mov r0, r8\r
- mov r1, r6\r
- //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3)\r
- bl ArmPlatformStackSet\r
-\r
- // Is it the Primary Core ?\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r4)\r
- cmp r6, r4\r
- bne _PrepareArguments\r
-\r
-_ReserveGlobalVariable\r
- LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r0)\r
- // InitializePrimaryStack($GlobalVariableSize, $Tmp1)\r
- InitializePrimaryStack r0, r1\r
-\r
-_PrepareArguments\r
- mov r0, r6\r
- mov r1, r7\r
- mov r2, r8\r
- mov r3, sp\r
-\r
- // Move sec startup address into a data register\r
- // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
- ldr r4, StartupAddr\r
-\r
- // Jump to PrePiCore C code\r
- // r0 = MpId\r
- // r1 = UefiMemoryBase\r
- // r2 = StacksBase\r
- // r3 = GlobalVariableBase\r
- blx r4\r
-\r
-_NeverReturn\r
- b _NeverReturn\r
-\r
- END\r
MODULE_TYPE = SEC\r
VERSION_STRING = 1.0\r
\r
-[Sources.ARM]\r
+[Sources]\r
PrePi.c\r
- ModuleEntryPoint.S | GCC\r
- ModuleEntryPoint.asm | RVCT\r
MainMPCore.c\r
+\r
+[Sources.ARM]\r
+ Arm/ModuleEntryPoint.S | GCC\r
+ Arm/ModuleEntryPoint.asm | RVCT\r
\r
[Packages]\r
MdePkg/MdePkg.dec\r
MODULE_TYPE = SEC\r
VERSION_STRING = 1.0\r
\r
-[Sources.ARM]\r
+[Sources]\r
PrePi.c\r
- ModuleEntryPoint.S | GCC\r
- ModuleEntryPoint.asm | RVCT\r
MainUniCore.c\r
+\r
+[Sources.ARM]\r
+ Arm/ModuleEntryPoint.S | GCC\r
+ Arm/ModuleEntryPoint.asm | RVCT\r
\r
[Packages]\r
MdePkg/MdePkg.dec\r
--- /dev/null
+#========================================================================================\r
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http:#opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#=======================================================================================\r
+\r
+#start of the code section\r
+.text \r
+.align 3\r
+\r
+GCC_ASM_EXPORT(return_from_exception)\r
+GCC_ASM_EXPORT(enter_monitor_mode)\r
+GCC_ASM_EXPORT(copy_cpsr_into_spsr)\r
+GCC_ASM_EXPORT(set_non_secure_mode)\r
+\r
+# r0: Monitor World EntryPoint\r
+# r1: MpId\r
+# r2: SecBootMode\r
+# r3: Secure Monitor mode stack\r
+ASM_PFX(enter_monitor_mode):\r
+ cmp r3, #0 @ If a Secure Monitor stack base has not been defined then use the Secure stack\r
+ moveq r3, sp\r
+\r
+ mrs r4, cpsr @ Save current mode (SVC) in r4\r
+ bic r5, r4, #0x1f @ Clear all mode bits\r
+ orr r5, r5, #0x16 @ Set bits for Monitor mode\r
+ msr cpsr_cxsf, r5 @ We are now in Monitor Mode\r
+\r
+ mov sp, r3 @ Set the stack of the Monitor Mode\r
+\r
+ mov lr, r0 @ Use the pass entrypoint as lr\r
+ \r
+ msr spsr_cxsf, r4 @ Use saved mode for the MOVS jump to the kernel\r
+\r
+ mov r4, r0 @ Swap EntryPoint and MpId registers\r
+ mov r0, r1\r
+ mov r1, r2\r
+ mov r2, r3\r
+\r
+ bx r4\r
+\r
+# We cannot use the instruction 'movs pc, lr' because the caller can be written either in ARM or Thumb2 assembler.\r
+# When we will jump into this function, we will set the CPSR flag to ARM assembler. By copying directly 'lr' into\r
+# 'pc'; we will not change the CPSR flag and it will crash.\r
+# The way to fix this limitation is to do the movs into the ARM assmbler code and then do a 'bx'.\r
+ASM_PFX(return_from_exception):\r
+ ldr lr, returned_exception\r
+\r
+ #The following instruction breaks the code.\r
+ #movs pc, lr\r
+ mrs r2, cpsr\r
+ bic r2, r2, #0x1f\r
+ orr r2, r2, #0x13\r
+ msr cpsr_c, r2\r
+\r
+returned_exception: @ We are now in non-secure state\r
+ bx r0\r
+\r
+# Save the current Program Status Register (PSR) into the Saved PSR\r
+ASM_PFX(copy_cpsr_into_spsr):\r
+ mrs r0, cpsr\r
+ msr spsr_cxsf, r0\r
+ bx lr\r
+\r
+# Set the Non Secure Mode\r
+ASM_PFX(set_non_secure_mode):\r
+ push { r1 }\r
+ and r0, r0, #0x1f @ Keep only the mode bits\r
+ mrs r1, spsr @ Read the spsr\r
+ bic r1, r1, #0x1f @ Clear all mode bits\r
+ orr r1, r1, r0\r
+ msr spsr_cxsf, r1 @ write back spsr (may have caused a mode switch)\r
+ isb\r
+ pop { r1 }\r
+ bx lr @ return (hopefully thumb-safe!)\r
+\r
+dead:\r
+ b dead\r
+ \r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
--- /dev/null
+//\r
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+ EXPORT return_from_exception\r
+ EXPORT enter_monitor_mode\r
+ EXPORT copy_cpsr_into_spsr\r
+ EXPORT set_non_secure_mode\r
+ \r
+ AREA Helper, CODE, READONLY\r
+\r
+// r0: Monitor World EntryPoint\r
+// r1: MpId\r
+// r2: SecBootMode\r
+// r3: Secure Monitor mode stack\r
+enter_monitor_mode FUNCTION\r
+ cmp r3, #0 // If a Secure Monitor stack base has not been defined then use the Secure stack\r
+ moveq r3, sp\r
+\r
+ mrs r4, cpsr // Save current mode (SVC) in r4\r
+ bic r5, r4, #0x1f // Clear all mode bits\r
+ orr r5, r5, #0x16 // Set bits for Monitor mode\r
+ msr cpsr_cxsf, r5 // We are now in Monitor Mode\r
+\r
+ mov sp, r3 // Set the stack of the Monitor Mode\r
+\r
+ mov lr, r0 // Use the pass entrypoint as lr\r
+ \r
+ msr spsr_cxsf, r4 // Use saved mode for the MOVS jump to the kernel\r
+\r
+ mov r4, r0 // Swap EntryPoint and MpId registers\r
+ mov r0, r1\r
+ mov r1, r2\r
+ mov r2, r3\r
+\r
+ bx r4\r
+ ENDFUNC\r
+\r
+// We cannot use the instruction 'movs pc, lr' because the caller can be written either in ARM or Thumb2 assembler.\r
+// When we will jump into this function, we will set the CPSR flag to ARM assembler. By copying directly 'lr' into\r
+// 'pc'; we will not change the CPSR flag and it will crash.\r
+// The way to fix this limitation is to do the movs into the ARM assmbler code and then do a 'bx'.\r
+return_from_exception\r
+ adr lr, returned_exception\r
+ movs pc, lr\r
+returned_exception // We are now in non-secure state\r
+ bx r0\r
+\r
+// Save the current Program Status Register (PSR) into the Saved PSR\r
+copy_cpsr_into_spsr\r
+ mrs r0, cpsr\r
+ msr spsr_cxsf, r0\r
+ bx lr\r
+\r
+// Set the Non Secure Mode\r
+set_non_secure_mode\r
+ push { r1 }\r
+ and r0, r0, #0x1f // Keep only the mode bits\r
+ mrs r1, spsr // Read the spsr\r
+ bic r1, r1, #0x1f // Clear all mode bits\r
+ orr r1, r1, r0\r
+ msr spsr_cxsf, r1 // write back spsr (may have caused a mode switch)\r
+ isb\r
+ pop { r1 }\r
+ bx lr // return (hopefully thumb-safe!)\r
+\r
+dead\r
+ B dead\r
+ \r
+ END\r
--- /dev/null
+//\r
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AutoGen.h>\r
+#include <AsmMacroIoLib.h>\r
+#include "SecInternal.h"\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_IMPORT(CEntryPoint)\r
+GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r
+GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)\r
+GCC_ASM_IMPORT(ArmDisableInterrupts)\r
+GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r
+GCC_ASM_IMPORT(ArmReadMpidr)\r
+GCC_ASM_IMPORT(ArmCallWFE)\r
+GCC_ASM_EXPORT(_ModuleEntryPoint)\r
+\r
+StartupAddr: .word ASM_PFX(CEntryPoint)\r
+\r
+ASM_PFX(_ModuleEntryPoint):\r
+ // First ensure all interrupts are disabled\r
+ bl ASM_PFX(ArmDisableInterrupts)\r
+\r
+ // Ensure that the MMU and caches are off\r
+ bl ASM_PFX(ArmDisableCachesAndMmu)\r
+\r
+ // By default, we are doing a cold boot\r
+ mov r10, #ARM_SEC_COLD_BOOT\r
+\r
+ // Jump to Platform Specific Boot Action function\r
+ blx ASM_PFX(ArmPlatformSecBootAction)\r
+\r
+_IdentifyCpu:\r
+ // Identify CPU ID\r
+ bl ASM_PFX(ArmReadMpidr)\r
+ // Get ID of this CPU in Multicore system\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
+ and r5, r0, r1\r
+ \r
+ // Is it the Primary Core ?\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
+ cmp r5, r3\r
+ // Only the primary core initialize the memory (SMC)\r
+ beq _InitMem\r
+ \r
+_WaitInitMem:\r
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
+ // Otherwise we have to wait the Primary Core to finish the initialization\r
+ cmp r10, #ARM_SEC_COLD_BOOT\r
+ bne _SetupSecondaryCoreStack\r
+\r
+ // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
+ bl ASM_PFX(ArmCallWFE)\r
+ // Now the Init Mem is initialized, we setup the secondary core stacks\r
+ b _SetupSecondaryCoreStack\r
+ \r
+_InitMem:\r
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
+ cmp r10, #ARM_SEC_COLD_BOOT\r
+ bne _SetupPrimaryCoreStack\r
+\r
+ // Initialize Init Boot Memory\r
+ bl ASM_PFX(ArmPlatformSecBootMemoryInit)\r
+ \r
+ // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r
+\r
+_SetupPrimaryCoreStack:\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
+ add r1, r1, r2\r
+\r
+ LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)\r
+\r
+ // The reserved space for global variable must be 8-bytes aligned for pushing\r
+ // 64-bit variable on the stack\r
+ SetPrimaryStack (r1, r2, r3)\r
+ b _PrepareArguments\r
+\r
+_SetupSecondaryCoreStack:\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
+ add r1, r1, r2\r
+\r
+ // Get the Core Position (ClusterId * 4) + CoreId\r
+ GetCorePositionFromMpId(r0, r5, r2)\r
+ // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
+ add r0, r0, #1\r
+\r
+ // StackOffset = CorePos * StackSize\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
+ mul r0, r0, r2\r
+ // SP = StackBase + StackOffset\r
+ add sp, r1, r0\r
+\r
+_PrepareArguments:\r
+ // Move sec startup address into a data register\r
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ ldr r3, StartupAddr\r
+ \r
+ // Jump to SEC C code\r
+ // r0 = mp_id\r
+ // r1 = Boot Mode\r
+ mov r0, r5\r
+ mov r1, r10\r
+ blx r3\r
+ \r
+_NeverReturn:\r
+ b _NeverReturn\r
--- /dev/null
+//\r
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AutoGen.h>\r
+#include <AsmMacroIoLib.h>\r
+#include "SecInternal.h"\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+ \r
+ IMPORT CEntryPoint\r
+ IMPORT ArmPlatformSecBootAction\r
+ IMPORT ArmPlatformSecBootMemoryInit\r
+ IMPORT ArmDisableInterrupts\r
+ IMPORT ArmDisableCachesAndMmu\r
+ IMPORT ArmReadMpidr\r
+ IMPORT ArmCallWFE\r
+ EXPORT _ModuleEntryPoint\r
+\r
+ PRESERVE8\r
+ AREA SecEntryPoint, CODE, READONLY\r
+ \r
+StartupAddr DCD CEntryPoint\r
+\r
+_ModuleEntryPoint FUNCTION\r
+ // First ensure all interrupts are disabled\r
+ blx ArmDisableInterrupts\r
+\r
+ // Ensure that the MMU and caches are off\r
+ blx ArmDisableCachesAndMmu\r
+\r
+ // By default, we are doing a cold boot\r
+ mov r10, #ARM_SEC_COLD_BOOT\r
+\r
+ // Jump to Platform Specific Boot Action function\r
+ blx ArmPlatformSecBootAction\r
+\r
+_IdentifyCpu \r
+ // Identify CPU ID\r
+ bl ArmReadMpidr\r
+ // Get ID of this CPU in Multicore system\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
+ and r5, r0, r1\r
+ \r
+ // Is it the Primary Core ?\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
+ cmp r5, r3\r
+ // Only the primary core initialize the memory (SMC)\r
+ beq _InitMem\r
+ \r
+_WaitInitMem\r
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
+ // Otherwise we have to wait the Primary Core to finish the initialization\r
+ cmp r10, #ARM_SEC_COLD_BOOT\r
+ bne _SetupSecondaryCoreStack\r
+\r
+ // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
+ bl ArmCallWFE\r
+ // Now the Init Mem is initialized, we setup the secondary core stacks\r
+ b _SetupSecondaryCoreStack\r
+ \r
+_InitMem\r
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
+ cmp r10, #ARM_SEC_COLD_BOOT\r
+ bne _SetupPrimaryCoreStack\r
+\r
+ // Initialize Init Boot Memory\r
+ bl ArmPlatformSecBootMemoryInit\r
+ \r
+ // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r
+\r
+_SetupPrimaryCoreStack\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
+ add r1, r1, r2\r
+\r
+ LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)\r
+\r
+ // The reserved space for global variable must be 8-bytes aligned for pushing\r
+ // 64-bit variable on the stack\r
+ SetPrimaryStack (r1, r2, r3)\r
+ b _PrepareArguments\r
+\r
+_SetupSecondaryCoreStack\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
+ add r1, r1, r2\r
+\r
+ // Get the Core Position (ClusterId * 4) + CoreId\r
+ GetCorePositionFromMpId(r0, r5, r2)\r
+ // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
+ add r0, r0, #1\r
+\r
+ // StackOffset = CorePos * StackSize\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
+ mul r0, r0, r2\r
+ // SP = StackBase + StackOffset\r
+ add sp, r1, r0\r
+\r
+_PrepareArguments\r
+ // Move sec startup address into a data register\r
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ ldr r3, StartupAddr\r
+ \r
+ // Jump to SEC C code\r
+ // r0 = mp_id\r
+ // r1 = Boot Mode\r
+ mov r0, r5\r
+ mov r1, r10\r
+ blx r3\r
+ ENDFUNC\r
+ \r
+_NeverReturn\r
+ b _NeverReturn\r
+ END\r
+++ /dev/null
-#========================================================================================\r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http:#opensource.org/licenses/bsd-license.php \r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#=======================================================================================\r
-\r
-#start of the code section\r
-.text \r
-.align 3\r
-\r
-GCC_ASM_EXPORT(return_from_exception)\r
-GCC_ASM_EXPORT(enter_monitor_mode)\r
-GCC_ASM_EXPORT(copy_cpsr_into_spsr)\r
-GCC_ASM_EXPORT(set_non_secure_mode)\r
-\r
-# r0: Monitor World EntryPoint\r
-# r1: MpId\r
-# r2: SecBootMode\r
-# r3: Secure Monitor mode stack\r
-ASM_PFX(enter_monitor_mode):\r
- cmp r3, #0 @ If a Secure Monitor stack base has not been defined then use the Secure stack\r
- moveq r3, sp\r
-\r
- mrs r4, cpsr @ Save current mode (SVC) in r4\r
- bic r5, r4, #0x1f @ Clear all mode bits\r
- orr r5, r5, #0x16 @ Set bits for Monitor mode\r
- msr cpsr_cxsf, r5 @ We are now in Monitor Mode\r
-\r
- mov sp, r3 @ Set the stack of the Monitor Mode\r
-\r
- mov lr, r0 @ Use the pass entrypoint as lr\r
- \r
- msr spsr_cxsf, r4 @ Use saved mode for the MOVS jump to the kernel\r
-\r
- mov r4, r0 @ Swap EntryPoint and MpId registers\r
- mov r0, r1\r
- mov r1, r2\r
- mov r2, r3\r
-\r
- bx r4\r
-\r
-# We cannot use the instruction 'movs pc, lr' because the caller can be written either in ARM or Thumb2 assembler.\r
-# When we will jump into this function, we will set the CPSR flag to ARM assembler. By copying directly 'lr' into\r
-# 'pc'; we will not change the CPSR flag and it will crash.\r
-# The way to fix this limitation is to do the movs into the ARM assmbler code and then do a 'bx'.\r
-ASM_PFX(return_from_exception):\r
- ldr lr, returned_exception\r
-\r
- #The following instruction breaks the code.\r
- #movs pc, lr\r
- mrs r2, cpsr\r
- bic r2, r2, #0x1f\r
- orr r2, r2, #0x13\r
- msr cpsr_c, r2\r
-\r
-returned_exception: @ We are now in non-secure state\r
- bx r0\r
-\r
-# Save the current Program Status Register (PSR) into the Saved PSR\r
-ASM_PFX(copy_cpsr_into_spsr):\r
- mrs r0, cpsr\r
- msr spsr_cxsf, r0\r
- bx lr\r
-\r
-# Set the Non Secure Mode\r
-ASM_PFX(set_non_secure_mode):\r
- push { r1 }\r
- and r0, r0, #0x1f @ Keep only the mode bits\r
- mrs r1, spsr @ Read the spsr\r
- bic r1, r1, #0x1f @ Clear all mode bits\r
- orr r1, r1, r0\r
- msr spsr_cxsf, r1 @ write back spsr (may have caused a mode switch)\r
- isb\r
- pop { r1 }\r
- bx lr @ return (hopefully thumb-safe!)\r
-\r
-dead:\r
- b dead\r
- \r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-// \r
-// This program and the accompanying materials \r
-// are licensed and made available under the terms and conditions of the BSD License \r
-// which accompanies this distribution. The full text of the license may be found at \r
-// http://opensource.org/licenses/bsd-license.php \r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-//\r
-//\r
-\r
- EXPORT return_from_exception\r
- EXPORT enter_monitor_mode\r
- EXPORT copy_cpsr_into_spsr\r
- EXPORT set_non_secure_mode\r
- \r
- AREA Helper, CODE, READONLY\r
-\r
-// r0: Monitor World EntryPoint\r
-// r1: MpId\r
-// r2: SecBootMode\r
-// r3: Secure Monitor mode stack\r
-enter_monitor_mode FUNCTION\r
- cmp r3, #0 // If a Secure Monitor stack base has not been defined then use the Secure stack\r
- moveq r3, sp\r
-\r
- mrs r4, cpsr // Save current mode (SVC) in r4\r
- bic r5, r4, #0x1f // Clear all mode bits\r
- orr r5, r5, #0x16 // Set bits for Monitor mode\r
- msr cpsr_cxsf, r5 // We are now in Monitor Mode\r
-\r
- mov sp, r3 // Set the stack of the Monitor Mode\r
-\r
- mov lr, r0 // Use the pass entrypoint as lr\r
- \r
- msr spsr_cxsf, r4 // Use saved mode for the MOVS jump to the kernel\r
-\r
- mov r4, r0 // Swap EntryPoint and MpId registers\r
- mov r0, r1\r
- mov r1, r2\r
- mov r2, r3\r
-\r
- bx r4\r
- ENDFUNC\r
-\r
-// We cannot use the instruction 'movs pc, lr' because the caller can be written either in ARM or Thumb2 assembler.\r
-// When we will jump into this function, we will set the CPSR flag to ARM assembler. By copying directly 'lr' into\r
-// 'pc'; we will not change the CPSR flag and it will crash.\r
-// The way to fix this limitation is to do the movs into the ARM assmbler code and then do a 'bx'.\r
-return_from_exception\r
- adr lr, returned_exception\r
- movs pc, lr\r
-returned_exception // We are now in non-secure state\r
- bx r0\r
-\r
-// Save the current Program Status Register (PSR) into the Saved PSR\r
-copy_cpsr_into_spsr\r
- mrs r0, cpsr\r
- msr spsr_cxsf, r0\r
- bx lr\r
-\r
-// Set the Non Secure Mode\r
-set_non_secure_mode\r
- push { r1 }\r
- and r0, r0, #0x1f // Keep only the mode bits\r
- mrs r1, spsr // Read the spsr\r
- bic r1, r1, #0x1f // Clear all mode bits\r
- orr r1, r1, r0\r
- msr spsr_cxsf, r1 // write back spsr (may have caused a mode switch)\r
- isb\r
- pop { r1 }\r
- bx lr // return (hopefully thumb-safe!)\r
-\r
-dead\r
- B dead\r
- \r
- END\r
MODULE_TYPE = SEC\r
VERSION_STRING = 1.0\r
\r
-[Sources.ARM]\r
- Helper.asm | RVCT\r
- Helper.S | GCC\r
+[Sources]\r
Sec.c\r
- SecEntryPoint.S | GCC\r
- SecEntryPoint.asm | RVCT\r
+\r
+[Sources.ARM]\r
+ Arm/Helper.asm | RVCT\r
+ Arm/Helper.S | GCC\r
+ Arm/SecEntryPoint.S | GCC\r
+ Arm/SecEntryPoint.asm | RVCT\r
\r
[Packages]\r
MdePkg/MdePkg.dec\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-// \r
-// This program and the accompanying materials \r
-// are licensed and made available under the terms and conditions of the BSD License \r
-// which accompanies this distribution. The full text of the license may be found at \r
-// http://opensource.org/licenses/bsd-license.php \r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-//\r
-//\r
-\r
-#include <AutoGen.h>\r
-#include <AsmMacroIoLib.h>\r
-#include "SecInternal.h"\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_IMPORT(CEntryPoint)\r
-GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r
-GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)\r
-GCC_ASM_IMPORT(ArmDisableInterrupts)\r
-GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r
-GCC_ASM_IMPORT(ArmReadMpidr)\r
-GCC_ASM_IMPORT(ArmCallWFE)\r
-GCC_ASM_EXPORT(_ModuleEntryPoint)\r
-\r
-StartupAddr: .word ASM_PFX(CEntryPoint)\r
-\r
-ASM_PFX(_ModuleEntryPoint):\r
- // First ensure all interrupts are disabled\r
- bl ASM_PFX(ArmDisableInterrupts)\r
-\r
- // Ensure that the MMU and caches are off\r
- bl ASM_PFX(ArmDisableCachesAndMmu)\r
-\r
- // By default, we are doing a cold boot\r
- mov r10, #ARM_SEC_COLD_BOOT\r
-\r
- // Jump to Platform Specific Boot Action function\r
- blx ASM_PFX(ArmPlatformSecBootAction)\r
-\r
-_IdentifyCpu:\r
- // Identify CPU ID\r
- bl ASM_PFX(ArmReadMpidr)\r
- // Get ID of this CPU in Multicore system\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
- and r5, r0, r1\r
- \r
- // Is it the Primary Core ?\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
- cmp r5, r3\r
- // Only the primary core initialize the memory (SMC)\r
- beq _InitMem\r
- \r
-_WaitInitMem:\r
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
- // Otherwise we have to wait the Primary Core to finish the initialization\r
- cmp r10, #ARM_SEC_COLD_BOOT\r
- bne _SetupSecondaryCoreStack\r
-\r
- // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
- bl ASM_PFX(ArmCallWFE)\r
- // Now the Init Mem is initialized, we setup the secondary core stacks\r
- b _SetupSecondaryCoreStack\r
- \r
-_InitMem:\r
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
- cmp r10, #ARM_SEC_COLD_BOOT\r
- bne _SetupPrimaryCoreStack\r
-\r
- // Initialize Init Boot Memory\r
- bl ASM_PFX(ArmPlatformSecBootMemoryInit)\r
- \r
- // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r
-\r
-_SetupPrimaryCoreStack:\r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
- add r1, r1, r2\r
-\r
- LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)\r
-\r
- // The reserved space for global variable must be 8-bytes aligned for pushing\r
- // 64-bit variable on the stack\r
- SetPrimaryStack (r1, r2, r3)\r
- b _PrepareArguments\r
-\r
-_SetupSecondaryCoreStack:\r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
- add r1, r1, r2\r
-\r
- // Get the Core Position (ClusterId * 4) + CoreId\r
- GetCorePositionFromMpId(r0, r5, r2)\r
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
- add r0, r0, #1\r
-\r
- // StackOffset = CorePos * StackSize\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
- mul r0, r0, r2\r
- // SP = StackBase + StackOffset\r
- add sp, r1, r0\r
-\r
-_PrepareArguments:\r
- // Move sec startup address into a data register\r
- // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
- ldr r3, StartupAddr\r
- \r
- // Jump to SEC C code\r
- // r0 = mp_id\r
- // r1 = Boot Mode\r
- mov r0, r5\r
- mov r1, r10\r
- blx r3\r
- \r
-_NeverReturn:\r
- b _NeverReturn\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-// \r
-// This program and the accompanying materials \r
-// are licensed and made available under the terms and conditions of the BSD License \r
-// which accompanies this distribution. The full text of the license may be found at \r
-// http://opensource.org/licenses/bsd-license.php \r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-//\r
-//\r
-\r
-#include <AutoGen.h>\r
-#include <AsmMacroIoLib.h>\r
-#include "SecInternal.h"\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
- \r
- IMPORT CEntryPoint\r
- IMPORT ArmPlatformSecBootAction\r
- IMPORT ArmPlatformSecBootMemoryInit\r
- IMPORT ArmDisableInterrupts\r
- IMPORT ArmDisableCachesAndMmu\r
- IMPORT ArmReadMpidr\r
- IMPORT ArmCallWFE\r
- EXPORT _ModuleEntryPoint\r
-\r
- PRESERVE8\r
- AREA SecEntryPoint, CODE, READONLY\r
- \r
-StartupAddr DCD CEntryPoint\r
-\r
-_ModuleEntryPoint FUNCTION\r
- // First ensure all interrupts are disabled\r
- blx ArmDisableInterrupts\r
-\r
- // Ensure that the MMU and caches are off\r
- blx ArmDisableCachesAndMmu\r
-\r
- // By default, we are doing a cold boot\r
- mov r10, #ARM_SEC_COLD_BOOT\r
-\r
- // Jump to Platform Specific Boot Action function\r
- blx ArmPlatformSecBootAction\r
-\r
-_IdentifyCpu \r
- // Identify CPU ID\r
- bl ArmReadMpidr\r
- // Get ID of this CPU in Multicore system\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
- and r5, r0, r1\r
- \r
- // Is it the Primary Core ?\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
- cmp r5, r3\r
- // Only the primary core initialize the memory (SMC)\r
- beq _InitMem\r
- \r
-_WaitInitMem\r
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
- // Otherwise we have to wait the Primary Core to finish the initialization\r
- cmp r10, #ARM_SEC_COLD_BOOT\r
- bne _SetupSecondaryCoreStack\r
-\r
- // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
- bl ArmCallWFE\r
- // Now the Init Mem is initialized, we setup the secondary core stacks\r
- b _SetupSecondaryCoreStack\r
- \r
-_InitMem\r
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
- cmp r10, #ARM_SEC_COLD_BOOT\r
- bne _SetupPrimaryCoreStack\r
-\r
- // Initialize Init Boot Memory\r
- bl ArmPlatformSecBootMemoryInit\r
- \r
- // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r
-\r
-_SetupPrimaryCoreStack\r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
- add r1, r1, r2\r
-\r
- LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)\r
-\r
- // The reserved space for global variable must be 8-bytes aligned for pushing\r
- // 64-bit variable on the stack\r
- SetPrimaryStack (r1, r2, r3)\r
- b _PrepareArguments\r
-\r
-_SetupSecondaryCoreStack\r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
- add r1, r1, r2\r
-\r
- // Get the Core Position (ClusterId * 4) + CoreId\r
- GetCorePositionFromMpId(r0, r5, r2)\r
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
- add r0, r0, #1\r
-\r
- // StackOffset = CorePos * StackSize\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
- mul r0, r0, r2\r
- // SP = StackBase + StackOffset\r
- add sp, r1, r0\r
-\r
-_PrepareArguments\r
- // Move sec startup address into a data register\r
- // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
- ldr r3, StartupAddr\r
- \r
- // Jump to SEC C code\r
- // r0 = mp_id\r
- // r1 = Boot Mode\r
- mov r0, r5\r
- mov r1, r10\r
- blx r3\r
- ENDFUNC\r
- \r
-_NeverReturn\r
- b _NeverReturn\r
- END\r
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