EFI_STATUS Status;\r
UINT8 *DataPtr;\r
UINT8 *DataPhy;\r
- VOID *DataMap;\r
UINT8 PktId;\r
\r
Uhc = UHC_FROM_USB2_HC_PROTO (This);\r
IntTds = NULL;\r
DataPtr = NULL;\r
DataPhy = NULL;\r
- DataMap = NULL;\r
\r
IsSlowDevice = (BOOLEAN) ((EFI_USB_SPEED_LOW == DeviceSpeed) ? TRUE : FALSE);\r
\r
return EFI_DEVICE_ERROR;\r
}\r
\r
+ if ((EndPointAddress & 0x80) == 0) {\r
+ PktId = OUTPUT_PACKET_ID;\r
+ } else {\r
+ PktId = INPUT_PACKET_ID;\r
+ }\r
+\r
//\r
// Allocate and map source data buffer for bus master access.\r
//\r
- DataPtr = UsbHcAllocateMem (Uhc->MemPool, DataLength);\r
+ DataPtr = UsbHcAllocateMem (Uhc->MemPool, DataLength);\r
\r
if (DataPtr == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- OldTpl = gBS->RaiseTPL (UHCI_TPL);\r
-\r
- //\r
- // Map the user data then create a queue head and\r
- // list of TD for it.\r
- //\r
- Status = UhciMapUserData (\r
- Uhc,\r
- EfiUsbDataIn,\r
- DataPtr,\r
- &DataLength,\r
- &PktId,\r
- &DataPhy,\r
- &DataMap\r
- );\r
+ DataPhy = (UINT8 *)UsbHcGetPciAddressForHostMem (Uhc->MemPool, DataPtr, DataLength);\r
\r
- if (EFI_ERROR (Status)) {\r
- goto FREE_DATA;\r
- }\r
+ OldTpl = gBS->RaiseTPL (UHCI_TPL);\r
\r
Qh = UhciCreateQh (Uhc, PollingInterval);\r
\r
if (Qh == NULL) {\r
Status = EFI_OUT_OF_RESOURCES;\r
- goto UNMAP_DATA;\r
+ goto FREE_DATA;\r
}\r
\r
IntTds = UhciCreateBulkOrIntTds (\r
EndPointAddress,\r
DataLength,\r
PollingInterval,\r
- DataMap,\r
DataPtr,\r
CallBackFunction,\r
Context,\r
DESTORY_QH:\r
UsbHcFreeMem (Uhc->MemPool, Qh, sizeof (UHCI_QH_SW));\r
\r
-UNMAP_DATA:\r
- Uhc->PciIo->Unmap (Uhc->PciIo, DataMap);\r
-\r
FREE_DATA:\r
- gBS->FreePool (DataPtr);\r
+ UsbHcFreeMem (Uhc->MemPool, DataPtr, DataLength);\r
Uhc->PciIo->Flush (Uhc->PciIo);\r
\r
gBS->RestoreTPL (OldTpl);\r
\r
The UHCI register operation routines.\r
\r
-Copyright (c) 2007 - 2008, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
IN UHCI_TD_SW *Td\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN Len;\r
EFI_PHYSICAL_ADDRESS PhyAddr;\r
- VOID* Map;\r
\r
- Len = sizeof (UHCI_TD_HW);\r
- Status = Uhc->PciIo->Map (\r
- Uhc->PciIo,\r
- EfiPciIoOperationBusMasterRead,\r
- Td,\r
- &Len,\r
- &PhyAddr,\r
- &Map\r
- );\r
+ PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Td, sizeof (UHCI_TD_HW));\r
\r
- ASSERT (!EFI_ERROR (Status) && (Qh != NULL) && (Td != NULL));\r
+ ASSERT ((Qh != NULL) && (Td != NULL));\r
\r
Qh->QhHw.VerticalLink = QH_VLINK (PhyAddr, FALSE);\r
Qh->TDs = (VOID *) Td;\r
IN UHCI_TD_SW *ThisTd\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN Len;\r
EFI_PHYSICAL_ADDRESS PhyAddr;\r
- VOID* Map;\r
\r
- Len = sizeof (UHCI_TD_HW);\r
- Status = Uhc->PciIo->Map (\r
- Uhc->PciIo,\r
- EfiPciIoOperationBusMasterRead,\r
- ThisTd,\r
- &Len,\r
- &PhyAddr,\r
- &Map\r
- );\r
+ PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, ThisTd, sizeof (UHCI_TD_HW));\r
\r
- ASSERT (!EFI_ERROR (Status) && (PrevTd != NULL) && (ThisTd != NULL));\r
+ ASSERT ((PrevTd != NULL) && (ThisTd != NULL));\r
\r
PrevTd->TdHw.NextLink = TD_LINK (PhyAddr, TRUE, FALSE);\r
PrevTd->NextTd = (VOID *) ThisTd;\r
return NULL;\r
}\r
\r
+ Td->TdHw.NextLink = TD_LINK (NULL, FALSE, TRUE);\r
Td->NextTd = NULL;\r
Td->Data = NULL;\r
Td->DataLen = 0;\r
Td->TdHw.ShortPacket = FALSE;\r
Td->TdHw.IsIsoch = FALSE;\r
Td->TdHw.IntOnCpl = FALSE;\r
- Td->TdHw.ErrorCount = 0X03;\r
+ Td->TdHw.ErrorCount = 0x03;\r
Td->TdHw.Status = USBTD_ACTIVE;\r
Td->TdHw.LowSpeed = IsLow ? 1 : 0;\r
Td->TdHw.DataToggle = Toggle & 0x01;\r
\r
The EHCI register operation routines.\r
\r
-Copyright (c) 2007 - 2009, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
UINTN Pages;\r
UINTN Bytes;\r
UINTN Index;\r
- UINTN Len;\r
EFI_PHYSICAL_ADDRESS PhyAddr;\r
\r
//\r
goto ON_ERROR;\r
}\r
\r
- Uhc->FrameBase = (UINT32 *) (UINTN) Buffer; // Cpu memory address\r
- Uhc->FrameBasePciMemAddr = (UINT32 *) (UINTN) MappedAddr; // Pci memory address\r
+ Uhc->FrameBase = (UINT32 *) (UINTN) Buffer;\r
Uhc->FrameMapping = Mapping;\r
\r
+ //\r
+ // Tell the Host Controller where the Frame List lies,\r
+ // by set the Frame List Base Address Register.\r
+ //\r
+ UhciSetFrameListBaseAddr (Uhc->PciIo, (VOID *) MappedAddr);\r
+\r
//\r
// Allocate the QH used by sync interrupt/control/bulk transfer.\r
// FS ctrl/bulk queue head is set to loopback so additional BW\r
// Each frame entry is linked to this sequence of QH. These QH\r
// will remain on the schedul, never got removed\r
//\r
- Len = sizeof (UHCI_QH_HW);\r
- Status = Uhc->PciIo->Map (\r
- Uhc->PciIo,\r
- EfiPciIoOperationBusMasterRead,\r
- Uhc->CtrlQh,\r
- &Len,\r
- &PhyAddr,\r
- &Mapping\r
- );\r
- ASSERT (!EFI_ERROR (Status));\r
-\r
+ PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Uhc->CtrlQh, sizeof (UHCI_QH_HW));\r
Uhc->SyncIntQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);\r
Uhc->SyncIntQh->NextQh = Uhc->CtrlQh;\r
\r
- Status = Uhc->PciIo->Map (\r
- Uhc->PciIo,\r
- EfiPciIoOperationBusMasterRead,\r
- Uhc->BulkQh,\r
- &Len,\r
- &PhyAddr,\r
- &Mapping\r
- );\r
- ASSERT (!EFI_ERROR (Status));\r
-\r
+ PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Uhc->BulkQh, sizeof (UHCI_QH_HW));\r
Uhc->CtrlQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);\r
Uhc->CtrlQh->NextQh = Uhc->BulkQh;\r
\r
\r
Uhc->BulkQh->NextQh = NULL;\r
\r
- Len = sizeof (UHCI_QH_HW);\r
- Status = Uhc->PciIo->Map (\r
- Uhc->PciIo,\r
- EfiPciIoOperationBusMasterRead,\r
- Uhc->SyncIntQh,\r
- &Len,\r
- &PhyAddr,\r
- &Mapping\r
- );\r
- ASSERT (!EFI_ERROR (Status));\r
+ Uhc->FrameBaseHostAddr = AllocateZeroPool (4096);\r
+ if (Uhc->FrameBaseHostAddr == NULL) {\r
+ Status = EFI_OUT_OF_RESOURCES;\r
+ goto ON_ERROR;\r
+ }\r
\r
+ PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Uhc->SyncIntQh, sizeof (UHCI_QH_HW));\r
for (Index = 0; Index < UHCI_FRAME_NUM; Index++) {\r
- Uhc->FrameBase[Index] = QH_HLINK (Uhc->SyncIntQh, FALSE);\r
- Uhc->FrameBasePciMemAddr[Index] = QH_HLINK (PhyAddr, FALSE);\r
+ Uhc->FrameBase[Index] = QH_HLINK (PhyAddr, FALSE);\r
+ Uhc->FrameBaseHostAddr[Index] = (UINT32)(UINTN)Uhc->SyncIntQh;\r
}\r
\r
- //\r
- // Tell the Host Controller where the Frame List lies,\r
- // by set the Frame List Base Address Register.\r
- //\r
- UhciSetFrameListBaseAddr (Uhc->PciIo, (VOID *) (Uhc->FrameBasePciMemAddr));\r
return EFI_SUCCESS;\r
\r
ON_ERROR:\r
(VOID *) Uhc->FrameBase\r
);\r
\r
+ if (Uhc->FrameBaseHostAddr != NULL) {\r
+ FreePool (Uhc->FrameBaseHostAddr);\r
+ }\r
+\r
if (Uhc->SyncIntQh != NULL) {\r
UsbHcFreeMem (Uhc->MemPool, Uhc->SyncIntQh, sizeof (UHCI_QH_SW));\r
}\r
}\r
\r
Uhc->FrameBase = NULL;\r
- Uhc->FrameBasePciMemAddr = NULL;\r
+ Uhc->FrameBaseHostAddr = NULL;\r
Uhc->SyncIntQh = NULL;\r
Uhc->CtrlQh = NULL;\r
Uhc->BulkQh = NULL;\r
UINTN Index;\r
UHCI_QH_SW *Prev;\r
UHCI_QH_SW *Next;\r
- UINTN Len;\r
EFI_PHYSICAL_ADDRESS PhyAddr;\r
EFI_PHYSICAL_ADDRESS QhPciAddr;\r
- VOID* Map;\r
- EFI_STATUS Status;\r
\r
ASSERT ((Uhc->FrameBase != NULL) && (Qh != NULL));\r
\r
- Len = sizeof (UHCI_QH_HW);\r
- Status = Uhc->PciIo->Map (\r
- Uhc->PciIo,\r
- EfiPciIoOperationBusMasterRead,\r
- Qh,\r
- &Len,\r
- &QhPciAddr,\r
- &Map\r
- );\r
- ASSERT (!EFI_ERROR (Status));\r
+ QhPciAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Qh, sizeof (UHCI_QH_HW));\r
\r
for (Index = 0; Index < UHCI_FRAME_NUM; Index += Qh->Interval) {\r
//\r
// heads on the frame list\r
//\r
ASSERT (!LINK_TERMINATED (Uhc->FrameBase[Index]));\r
- Next = UHCI_ADDR (Uhc->FrameBase[Index]);\r
+ Next = (UHCI_QH_SW*)(UINTN)Uhc->FrameBaseHostAddr[Index];\r
Prev = NULL;\r
\r
//\r
//\r
if (Qh->NextQh == NULL) {\r
Qh->NextQh = Next;\r
-\r
- Len = sizeof (UHCI_QH_HW);\r
- Status = Uhc->PciIo->Map (\r
- Uhc->PciIo,\r
- EfiPciIoOperationBusMasterRead,\r
- Next,\r
- &Len,\r
- &PhyAddr,\r
- &Map\r
- );\r
- ASSERT (!EFI_ERROR (Status));\r
-\r
+ PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Next, sizeof (UHCI_QH_HW));\r
Qh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);\r
}\r
\r
if (Prev == NULL) {\r
- Uhc->FrameBase[Index] = QH_HLINK (Qh, FALSE);\r
- Uhc->FrameBasePciMemAddr[Index] = QH_HLINK (QhPciAddr, FALSE);\r
+ Uhc->FrameBase[Index] = QH_HLINK (QhPciAddr, FALSE);\r
+ Uhc->FrameBaseHostAddr[Index] = (UINT32)(UINTN)Qh;\r
} else {\r
Prev->NextQh = Qh;\r
Prev->QhHw.HorizonLink = QH_HLINK (QhPciAddr, FALSE);\r
// queue heads on the frame list\r
//\r
ASSERT (!LINK_TERMINATED (Uhc->FrameBase[Index]));\r
- This = UHCI_ADDR (Uhc->FrameBase[Index]);\r
+ This = (UHCI_QH_SW*)(UINTN)Uhc->FrameBaseHostAddr[Index];\r
Prev = NULL;\r
\r
//\r
//\r
// Qh is the first entry in the frame\r
//\r
- Uhc->FrameBase[Index] = (UINT32)(UINTN)Qh->NextQh;\r
- Uhc->FrameBasePciMemAddr[Index] = Qh->QhHw.HorizonLink;\r
+ Uhc->FrameBase[Index] = Qh->QhHw.HorizonLink;\r
+ Uhc->FrameBaseHostAddr[Index] = (UINT32)(UINTN)Qh->NextQh;\r
} else {\r
Prev->NextQh = Qh->NextQh;\r
Prev->QhHw.HorizonLink = Qh->QhHw.HorizonLink;\r
@param EndPoint EndPoint Address.\r
@param DataLen Data length.\r
@param Interval Polling Interval when inserted to frame list.\r
- @param Mapping Mapping value.\r
@param Data Data buffer, unmapped.\r
@param Callback Callback after interrupt transfeer.\r
@param Context Callback Context passed as function parameter.\r
IN UINT8 EndPoint,\r
IN UINTN DataLen,\r
IN UINTN Interval,\r
- IN VOID *Mapping,\r
IN UINT8 *Data,\r
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
IN VOID *Context,\r
AsyncReq->EndPoint = EndPoint;\r
AsyncReq->DataLen = DataLen;\r
AsyncReq->Interval = UhciConvertPollRate(Interval);\r
- AsyncReq->Mapping = Mapping;\r
AsyncReq->Data = Data;\r
AsyncReq->Callback = Callback;\r
AsyncReq->Context = Context;\r
UhciDestoryTds (Uhc, AsyncReq->FirstTd);\r
UsbHcFreeMem (Uhc->MemPool, AsyncReq->QhSw, sizeof (UHCI_QH_SW));\r
\r
- if (AsyncReq->Mapping != NULL) {\r
- Uhc->PciIo->Unmap (Uhc->PciIo, AsyncReq->Mapping);\r
- }\r
-\r
if (AsyncReq->Data != NULL) {\r
UsbHcFreeMem (Uhc->MemPool, AsyncReq->Data, AsyncReq->DataLen);\r
}\r
\r
The routine procedure for uhci memory allocate/free.\r
\r
-Copyright (c) 2007, Intel Corporation\r
+Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
return Block->Buf + (StartByte * 8 + StartBit) * USBHC_MEM_UNIT;\r
}\r
\r
+/**\r
+ Calculate the corresponding pci bus address according to the Mem parameter.\r
+\r
+ @param Pool The memory pool of the host controller.\r
+ @param Mem The pointer to host memory.\r
+ @param Size The size of the memory region.\r
+\r
+ @return the pci memory address\r
+**/\r
+EFI_PHYSICAL_ADDRESS\r
+UsbHcGetPciAddressForHostMem (\r
+ IN USBHC_MEM_POOL *Pool,\r
+ IN VOID *Mem,\r
+ IN UINTN Size\r
+ )\r
+{\r
+ USBHC_MEM_BLOCK *Head;\r
+ USBHC_MEM_BLOCK *Block;\r
+ UINTN AllocSize;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ UINTN Offset;\r
+\r
+ Head = Pool->Head;\r
+ AllocSize = USBHC_MEM_ROUND (Size);\r
+\r
+ if (Mem == NULL) {\r
+ return 0;\r
+ }\r
+\r
+ for (Block = Head; Block != NULL; Block = Block->Next) {\r
+ //\r
+ // scan the memory block list for the memory block that\r
+ // completely contains the allocated memory.\r
+ //\r
+ if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {\r
+ break;\r
+ }\r
+ }\r
+\r
+ ASSERT ((Block != NULL));\r
+ //\r
+ // calculate the pci memory address for host memory address.\r
+ //\r
+ Offset = (UINT8 *)Mem - Block->BufHost;\r
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->Buf + Offset);\r
+ return PhyAddr;\r
+}\r
\r
/**\r
Insert the memory block to the pool's list of the blocks.\r
projects / mirror_edk2.git / commitdiff