ArmVirtualizationPkg/PciHostBridgeDxe: set Root Bridge apertures from PCDs

Our PciHostBridgeDxe module creates one root bridge on the one and only
host bridge. The resource apertures of the root bridge (bus range, IO
space, MMIO space) are configured with the "mResAperture" array, which at
the moment carries static values inherited from PcAtChipsetPkg.

Set the array as first thing from the PCDs that we parsed from the device
tree.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16897 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.c b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.c
index 2f6ef68f1dcc742752ab6d89adea9f095d69c8fd..ced7528a2ea49fa932fc68438b4ab500f895f8d3 100644 (file)
--- a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.c
+++ b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.c
@@ -52,9 +52,7 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = {
   }\r
 };\r
 \r
-PCI_ROOT_BRIDGE_RESOURCE_APERTURE  mResAperture[1][1] = {\r
-  {{0, 0xff, 0x80000000, 0xffffffff, 0, 0xffff}}\r
-};\r
+STATIC PCI_ROOT_BRIDGE_RESOURCE_APERTURE  mResAperture[1][1];\r
 \r
 EFI_HANDLE mDriverImageHandle;\r
 \r
@@ -106,6 +104,18 @@ InitializePciHostBridge (
  \r
   mDriverImageHandle = ImageHandle;\r
   \r
+  mResAperture[0][0].BusBase  = PcdGet32 (PcdPciBusMin);\r
+  mResAperture[0][0].BusLimit = PcdGet32 (PcdPciBusMax);\r
+\r
+  mResAperture[0][0].MemBase  = PcdGet32 (PcdPciMmio32Base);\r
+  mResAperture[0][0].MemLimit = (UINT64)PcdGet32 (PcdPciMmio32Base) +\r
+                                PcdGet32 (PcdPciMmio32Size) - 1;\r
+\r
+  mResAperture[0][0].IoBase        = PcdGet64 (PcdPciIoBase);\r
+  mResAperture[0][0].IoLimit       = PcdGet64 (PcdPciIoBase) +\r
+                                     PcdGet64 (PcdPciIoSize) - 1;\r
+  mResAperture[0][0].IoTranslation = PcdGet64 (PcdPciIoTranslation);\r
+\r
   //\r
   // Create Host Bridge Device Handle\r
   //\r

diff --git a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.h b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.h
index b69b832c9c3bdf49d88ccbd051a92fc664a23d5e..6e9bd84c478127a84470f1667619cbd655c258b3 100644 (file)
--- a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.h
+++ b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridge.h
@@ -36,6 +36,7 @@
 #include <Library/DevicePathLib.h>\r
 #include <Library/IoLib.h>\r
 #include <Library/PciLib.h>\r
+#include <Library/PcdLib.h>\r
 \r
 //\r
 // Hard code the host bridge number in the platform.\r
@@ -403,6 +404,7 @@ typedef struct {
   \r
   UINT64          IoBase; \r
   UINT64          IoLimit;     \r
+  UINT64          IoTranslation;\r
 } PCI_ROOT_BRIDGE_RESOURCE_APERTURE;\r
 \r
 typedef enum {\r

diff --git a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf
index 4d5bb9ca14e702e61be5a27545bebbeb25bb7d76..be3200dedb32075262a7c4609cfdde4c34145f8d 100644 (file)
--- a/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf
+++ b/ArmPlatformPkg/ArmVirtualizationPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf
@@ -23,6 +23,7 @@
 \r
 [Packages]\r
   MdePkg/MdePkg.dec\r
+  ArmPlatformPkg/ArmPlatformPkg.dec\r
 \r
 [LibraryClasses]\r
   UefiDriverEntryPoint\r
@@ -36,6 +37,7 @@
   DevicePathLib\r
   IoLib\r
   PciLib\r
+  PcdLib\r
 \r
 [Sources]\r
   PciHostBridge.c\r
@@ -48,5 +50,14 @@
   gEfiMetronomeArchProtocolGuid                         ## CONSUMES\r
   gEfiDevicePathProtocolGuid                            ## PRODUCES\r
 \r
+[Pcd]\r
+  gArmPlatformTokenSpaceGuid.PcdPciBusMin\r
+  gArmPlatformTokenSpaceGuid.PcdPciBusMax\r
+  gArmPlatformTokenSpaceGuid.PcdPciIoBase\r
+  gArmPlatformTokenSpaceGuid.PcdPciIoSize\r
+  gArmPlatformTokenSpaceGuid.PcdPciIoTranslation\r
+  gArmPlatformTokenSpaceGuid.PcdPciMmio32Base\r
+  gArmPlatformTokenSpaceGuid.PcdPciMmio32Size\r
+\r
 [depex]\r
   gEfiMetronomeArchProtocolGuid\r