Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);\r
AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);\r
@endcode\r
+ @note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
**/\r
#define MSR_CORE_P5_MC_ADDR 0x00000000\r
\r
Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);\r
AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);\r
@endcode\r
+ @note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
**/\r
#define MSR_CORE_P5_MC_TYPE 0x00000001\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);\r
AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);\r
@endcode\r
+ @note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
**/\r
#define MSR_CORE_EBL_CR_POWERON 0x0000002A\r
\r
Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);\r
AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);\r
@endcode\r
+ @note MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.\r
+ MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.\r
+ MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.\r
+ MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r
+ MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.\r
+ MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.\r
+ MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.\r
+ MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.\r
@{\r
**/\r
#define MSR_CORE_LASTBRANCH_0 0x00000040\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);\r
@endcode\r
+ @note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
**/\r
#define MSR_CORE_FSB_FREQ 0x000000CD\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);\r
AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);\r
@endcode\r
+ @note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
**/\r
#define MSR_CORE_BBL_CR_CTL3 0x0000011E\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);\r
AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);\r
@endcode\r
+ @note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
**/\r
#define MSR_CORE_THERM2_CTL 0x0000019D\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);\r
AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);\r
@endcode\r
+ @note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
#define MSR_CORE_IA32_MISC_ENABLE 0x000001A0\r
\r
Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);\r
AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);\r
@endcode\r
+ @note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
#define MSR_CORE_LASTBRANCH_TOS 0x000001C9\r
\r
\r
Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);\r
@endcode\r
+ @note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
#define MSR_CORE_LER_FROM_LIP 0x000001DD\r
\r
\r
Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);\r
@endcode\r
+ @note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
#define MSR_CORE_LER_TO_LIP 0x000001DE\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6);\r
AsmWriteMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6, Msr.Uint64);\r
@endcode\r
+ @note MSR_CORE_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM.\r
**/\r
#define MSR_CORE_ROB_CR_BKUPTMPDR6 0x000001E0\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);\r
AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);\r
@endcode\r
+ @note MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.\r
+ MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.\r
+ MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.\r
+ MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.\r
+ MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.\r
+ MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.\r
+ MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.\r
+ MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.\r
@{\r
**/\r
#define MSR_CORE_MTRRPHYSBASE0 0x00000200\r
Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);\r
AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);\r
@endcode\r
+ @note MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.\r
+ MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.\r
+ MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.\r
+ MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.\r
+ MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.\r
+ MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.\r
+ MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.\r
+ MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.\r
@{\r
**/\r
#define MSR_CORE_MTRRPHYSMASK0 0x00000201\r
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000);\r
AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr);\r
@endcode\r
+ @note MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.\r
**/\r
#define MSR_CORE_MTRRFIX64K_00000 0x00000250\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000);\r
AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr);\r
@endcode\r
+ @note MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.\r
**/\r
#define MSR_CORE_MTRRFIX16K_80000 0x00000258\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000);\r
AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr);\r
@endcode\r
+ @note MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.\r
**/\r
#define MSR_CORE_MTRRFIX16K_A0000 0x00000259\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000);\r
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr);\r
@endcode\r
+ @note MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.\r
**/\r
#define MSR_CORE_MTRRFIX4K_C0000 0x00000268\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000);\r
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr);\r
@endcode\r
+ @note MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.\r
**/\r
#define MSR_CORE_MTRRFIX4K_C8000 0x00000269\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000);\r
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr);\r
@endcode\r
+ @note MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.\r
**/\r
#define MSR_CORE_MTRRFIX4K_D0000 0x0000026A\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000);\r
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr);\r
@endcode\r
+ @note MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.\r
**/\r
#define MSR_CORE_MTRRFIX4K_D8000 0x0000026B\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000);\r
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr);\r
@endcode\r
+ @note MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.\r
**/\r
#define MSR_CORE_MTRRFIX4K_E0000 0x0000026C\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000);\r
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr);\r
@endcode\r
+ @note MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.\r
**/\r
#define MSR_CORE_MTRRFIX4K_E8000 0x0000026D\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000);\r
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr);\r
@endcode\r
+ @note MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.\r
**/\r
#define MSR_CORE_MTRRFIX4K_F0000 0x0000026E\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000);\r
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr);\r
@endcode\r
+ @note MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.\r
**/\r
#define MSR_CORE_MTRRFIX4K_F8000 0x0000026F\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL);\r
AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr);\r
@endcode\r
+ @note MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
**/\r
#define MSR_CORE_MC4_CTL 0x0000040C\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS);\r
AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr);\r
@endcode\r
+ @note MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
**/\r
#define MSR_CORE_MC4_STATUS 0x0000040D\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR);\r
AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr);\r
@endcode\r
+ @note MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
**/\r
#define MSR_CORE_MC4_ADDR 0x0000040E\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MC3_CTL);\r
AsmWriteMsr64 (MSR_CORE_MC3_CTL, Msr);\r
@endcode\r
+ @note MSR_CORE_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
**/\r
#define MSR_CORE_MC3_CTL 0x00000410\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MC3_STATUS);\r
AsmWriteMsr64 (MSR_CORE_MC3_STATUS, Msr);\r
@endcode\r
+ @note MSR_CORE_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
**/\r
#define MSR_CORE_MC3_STATUS 0x00000411\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR);\r
AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr);\r
@endcode\r
+ @note MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
**/\r
#define MSR_CORE_MC3_ADDR 0x00000412\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC);\r
AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr);\r
@endcode\r
+ @note MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM.\r
**/\r
#define MSR_CORE_MC3_MISC 0x00000413\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL);\r
AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr);\r
@endcode\r
+ @note MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
**/\r
#define MSR_CORE_MC5_CTL 0x00000414\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS);\r
AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr);\r
@endcode\r
+ @note MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
**/\r
#define MSR_CORE_MC5_STATUS 0x00000415\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR);\r
AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr);\r
@endcode\r
+ @note MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
**/\r
#define MSR_CORE_MC5_ADDR 0x00000416\r
\r
Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC);\r
AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr);\r
@endcode\r
+ @note MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
**/\r
#define MSR_CORE_MC5_MISC 0x00000417\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);\r
AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64);\r
@endcode\r
+ @note MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM.\r
**/\r
#define MSR_CORE_IA32_EFER 0xC0000080\r
\r