@param PciIo PCI IO protocol instance.\r
@param PciDeviceInfo PCI device information.\r
@param Width Signifies the width of the memory operations.\r
- @param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Offset The offset within the PCI configuration space for the PCI controller.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL\r
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
IN UINT64 Width,\r
- IN UINT64 Address,\r
+ IN UINT64 Offset,\r
IN OUT VOID *Buffer\r
)\r
{\r
//\r
// Check access compatibility at first time\r
//\r
- Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, Address & 0xff, Width, &PciRegisterAccessData);\r
+ Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, Offset & 0xff, Width, &PciRegisterAccessData);\r
\r
if (Status == EFI_SUCCESS) {\r
//\r
AccessWidth = PciRegisterAccessData->Width;\r
}\r
\r
- AccessAddress = Address & ~((1 << AccessWidth) - 1);\r
+ AccessAddress = Offset & ~((1 << AccessWidth) - 1);\r
\r
TempBuffer = 0;\r
Stride = 0;\r
\r
if (PciRootBridgeIo != NULL) {\r
Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth,\r
- AccessAddress,\r
- 1,\r
- Pointer\r
- );\r
+ PciRootBridgeIo,\r
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth,\r
+ AccessAddress,\r
+ 1,\r
+ Pointer\r
+ );\r
} else if (PciIo != NULL) {\r
Status = PciIo->Pci.Read (\r
- PciIo,\r
- (EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth,\r
- (UINT32) AccessAddress,\r
- 1,\r
- Pointer\r
- );\r
+ PciIo,\r
+ (EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth,\r
+ (UINT32) AccessAddress,\r
+ 1,\r
+ Pointer\r
+ );\r
}\r
\r
if (Status != EFI_SUCCESS) {\r
\r
Stride = (UINTN)1 << AccessWidth;\r
AccessAddress += Stride;\r
- if (AccessAddress >= (Address + LShiftU64 (1ULL, (UINTN)Width))) {\r
+ if (AccessAddress >= (Offset + LShiftU64 (1ULL, (UINTN)Width))) {\r
//\r
// If all datas have been read, exit\r
//\r
//\r
if (PciRootBridgeIo != NULL) {\r
Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
- Address,\r
- 1,\r
- Buffer\r
- );\r
+ PciRootBridgeIo,\r
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
+ Offset,\r
+ 1,\r
+ Buffer\r
+ );\r
\r
} else {\r
Status = PciIo->Pci.Read (\r
- PciIo,\r
- (EFI_PCI_IO_PROTOCOL_WIDTH) Width,\r
- (UINT32) Address,\r
- 1,\r
- Buffer\r
- );\r
+ PciIo,\r
+ (EFI_PCI_IO_PROTOCOL_WIDTH) Width,\r
+ (UINT32) Offset,\r
+ 1,\r
+ Buffer\r
+ );\r
}\r
\r
return Status;\r
@param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
@param AccessType Access type, READ or WRITE.\r
@param Width Signifies the width of the memory operations.\r
- @param Address The address within the PCI configuration space.\r
+ @param Offset The offset within the PCI configuration space.\r
@param Buffer Store the register data.\r
\r
@retval EFI_SUCCESS The data has been updated.\r
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
IN UINT64 AccessType,\r
IN UINT64 Width,\r
- IN UINT64 Address,\r
+ IN UINT64 Offset,\r
IN OUT VOID *Buffer\r
)\r
{\r
//\r
// Check register value incompatibility\r
//\r
- Status = PciRegisterUpdateCheck (PciDeviceInfo, AccessType, Address & 0xff, &PciRegisterData);\r
+ Status = PciRegisterUpdateCheck (PciDeviceInfo, AccessType, Offset & 0xff, &PciRegisterData);\r
if (Status == EFI_SUCCESS) {\r
\r
- AndValue = ((UINT32) PciRegisterData->AndValue) >> (((UINT8) Address & 0x3) * 8);\r
- OrValue = ((UINT32) PciRegisterData->OrValue) >> (((UINT8) Address & 0x3) * 8);\r
+ AndValue = ((UINT32) PciRegisterData->AndValue) >> (((UINT8) Offset & 0x3) * 8);\r
+ OrValue = ((UINT32) PciRegisterData->OrValue) >> (((UINT8) Offset & 0x3) * 8);\r
\r
TempValue = * (UINT32 *) Buffer;\r
if (PciRegisterData->AndValue != VALUE_NOCARE) {\r
@param PciIo PCI IO protocol instance.\r
@param PciDeviceInfo PCI device information.\r
@param Width Signifies the width of the memory operations.\r
- @param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Offset The offset within the PCI configuration space for the PCI controller.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL\r
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
IN UINT64 Width,\r
- IN UINT64 Address,\r
+ IN UINT64 Offset,\r
IN VOID *Buffer\r
)\r
{\r
//\r
// Check access compatibility at first time\r
//\r
- Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, Address & 0xff, Width, &PciRegisterAccessData);\r
+ Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, Offset & 0xff, Width, &PciRegisterAccessData);\r
\r
if (Status == EFI_SUCCESS) {\r
//\r
AccessWidth = PciRegisterAccessData->Width;\r
}\r
\r
- AccessAddress = Address & ~((1 << AccessWidth) - 1);\r
+ AccessAddress = Offset & ~((1 << AccessWidth) - 1);\r
\r
Stride = 0;\r
Pointer = (UINT8 *) &Buffer;\r
//\r
UpdateConfigData (PciDeviceInfo, PCI_REGISTER_READ, AccessWidth, AccessAddress & 0xff, &Data);\r
\r
- Shift = (UINTN)(Address - AccessAddress) * 8;\r
+ Shift = (UINTN)(Offset - AccessAddress) * 8;\r
switch (Width) {\r
case EfiPciWidthUint8:\r
Data = (* (UINT8 *) Buffer) << Shift | (Data & ~(0xff << Shift));\r
\r
if (PciRootBridgeIo != NULL) {\r
Status = PciRootBridgeIo->Pci.Write (\r
- PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth,\r
- AccessAddress,\r
- 1,\r
- &Data\r
- );\r
+ PciRootBridgeIo,\r
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth,\r
+ AccessAddress,\r
+ 1,\r
+ &Data\r
+ );\r
} else {\r
Status = PciIo->Pci.Write (\r
- PciIo,\r
- (EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth,\r
- (UINT32) AccessAddress,\r
- 1,\r
- &Data\r
- );\r
+ PciIo,\r
+ (EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth,\r
+ (UINT32) AccessAddress,\r
+ 1,\r
+ &Data\r
+ );\r
}\r
\r
if (Status != EFI_SUCCESS) {\r
\r
Stride = (UINTN)1 << AccessWidth;\r
AccessAddress += Stride;\r
- if (AccessAddress >= (Address + LShiftU64 (1ULL, (UINTN)Width))) {\r
+ if (AccessAddress >= (Offset + LShiftU64 (1ULL, (UINTN)Width))) {\r
//\r
// If all datas have been written, exit\r
//\r
//\r
if (PciRootBridgeIo != NULL) {\r
Status = PciRootBridgeIo->Pci.Write (\r
- PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
- Address,\r
- 1,\r
- Buffer\r
- );\r
+ PciRootBridgeIo,\r
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
+ Offset,\r
+ 1,\r
+ Buffer\r
+ );\r
} else {\r
Status = PciIo->Pci.Write (\r
- PciIo,\r
- (EFI_PCI_IO_PROTOCOL_WIDTH) Width,\r
- (UINT32) Address,\r
- 1,\r
- Buffer\r
- );\r
+ PciIo,\r
+ (EFI_PCI_IO_PROTOCOL_WIDTH) Width,\r
+ (UINT32) Offset,\r
+ 1,\r
+ Buffer\r
+ );\r
}\r
\r
return Status;\r
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
@param PciIo A pointer to EFI_PCI_PROTOCOL.\r
@param Pci PCI device configuration space.\r
- @param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Offset The offset within the PCI configuration space for the PCI controller.\r
@param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
\r
@retval EFI_SUCCESS Pci device device information has been abstracted.\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL\r
IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL\r
IN PCI_TYPE00 *Pci, OPTIONAL\r
- IN UINT64 Address, OPTIONAL\r
+ IN UINT64 Offset, OPTIONAL\r
OUT EFI_PCI_DEVICE_INFO *PciDeviceInfo\r
)\r
{\r
//\r
// While PCI_TYPE00 hasn't been gotten, read PCI device device information directly\r
//\r
- PciAddress = Address & 0xffffffffffffff00ULL;\r
+ PciAddress = Offset & 0xffffffffffffff00ULL;\r
Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- EfiPciWidthUint32,\r
- PciAddress,\r
- 1,\r
- &PciConfigData\r
- );\r
+ PciRootBridgeIo,\r
+ EfiPciWidthUint32,\r
+ PciAddress,\r
+ 1,\r
+ &PciConfigData\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
PciDeviceInfo->DeviceID = PciConfigData >> 16;\r
\r
Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- EfiPciWidthUint32,\r
- PciAddress + 8,\r
- 1,\r
- &PciConfigData\r
- );\r
+ PciRootBridgeIo,\r
+ EfiPciWidthUint32,\r
+ PciAddress + 8,\r
+ 1,\r
+ &PciConfigData\r
+ );\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
PciDeviceInfo->RevisionID = PciConfigData & 0xf;\r
\r
Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- EfiPciWidthUint32,\r
- PciAddress + 0x2c,\r
- 1,\r
- &PciConfigData\r
- );\r
+ PciRootBridgeIo,\r
+ EfiPciWidthUint32,\r
+ PciAddress + 0x2c,\r
+ 1,\r
+ &PciConfigData\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
@param PciIo A pointer to the EFI_PCI_IO_PROTOCOL.\r
@param Pci A pointer to PCI_TYPE00.\r
@param Width Signifies the width of the memory operations.\r
- @param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Offset The offset within the PCI configuration space for the PCI controller.\r
@param Count The number of unit to be read.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL\r
IN PCI_TYPE00 *Pci, OPTIONAL\r
IN UINTN Width,\r
- IN UINT64 Address,\r
+ IN UINT64 Offset,\r
IN UINTN Count,\r
IN OUT VOID *Buffer\r
)\r
//\r
// get PCI device device information\r
//\r
- Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Address, &PciDeviceInfo);\r
+ Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Offset, &PciDeviceInfo);\r
if (Status != EFI_SUCCESS) {\r
return Status;\r
}\r
\r
Stride = 1 << Width;\r
\r
- for (; Count > 0; Count--, Address += Stride, Buffer = (UINT8 *)Buffer + Stride) {\r
+ for (; Count > 0; Count--, Offset += Stride, Buffer = (UINT8 *)Buffer + Stride) {\r
\r
//\r
// read configuration register\r
//\r
- Status = ReadConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, (UINT64) Width, Address, Buffer);\r
+ Status = ReadConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, (UINT64) Width, Offset, Buffer);\r
\r
if (Status != EFI_SUCCESS) {\r
return Status;\r
// update the data read from configuration register\r
//\r
if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) {\r
- UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_READ, Width, Address & 0xff, Buffer);\r
+ UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_READ, Width, Offset & 0xff, Buffer);\r
}\r
}\r
\r
@param PciIo A pointer to the EFI_PCI_IO_PROTOCOL.\r
@param Pci A pointer to PCI_TYPE00.\r
@param Width Signifies the width of the memory operations.\r
- @param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Offset The offset within the PCI configuration space for the PCI controller.\r
@param Count The number of unit to be write.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL\r
IN PCI_TYPE00 *Pci, OPTIONAL\r
IN UINTN Width,\r
- IN UINT64 Address,\r
+ IN UINT64 Offset,\r
IN UINTN Count,\r
IN OUT VOID *Buffer\r
)\r
//\r
// Get PCI device device information\r
//\r
- Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Address, &PciDeviceInfo);\r
+ Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Offset, &PciDeviceInfo);\r
if (Status != EFI_SUCCESS) {\r
return Status;\r
}\r
\r
Stride = 1 << Width;\r
\r
- for (; Count > 0; Count--, Address += Stride, Buffer = (UINT8 *) Buffer + Stride) {\r
+ for (; Count > 0; Count--, Offset += Stride, Buffer = (UINT8 *) Buffer + Stride) {\r
\r
Data = 0;\r
\r
// Update the data writen into configuration register\r
//\r
if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) {\r
- UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_WRITE, Width, Address & 0xff, &Data);\r
+ UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_WRITE, Width, Offset & 0xff, &Data);\r
}\r
\r
//\r
// Write configuration register\r
//\r
- Status = WriteConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, Width, Address, &Data);\r
+ Status = WriteConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, Width, Offset, &Data);\r
\r
if (Status != EFI_SUCCESS) {\r
return Status;\r
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
@param Pci A pointer to PCI_TYPE00.\r
@param Width Signifies the width of the memory operations.\r
- @param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Offset The offset within the PCI configuration space for the PCI controller.\r
@param Count The number of unit to be read.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
IN PCI_TYPE00 *Pci, OPTIONAL\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
+ IN UINT64 Offset,\r
IN UINTN Count,\r
IN OUT VOID *Buffer\r
)\r
NULL,\r
Pci,\r
(UINTN) Width,\r
- Address,\r
+ Offset,\r
Count,\r
Buffer\r
);\r
return PciRootBridgeIo->Pci.Read (\r
PciRootBridgeIo,\r
Width,\r
- Address,\r
+ Offset,\r
Count,\r
Buffer\r
);\r
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
@param Pci A pointer to PCI_TYPE00.\r
@param Width Signifies the width of the memory operations.\r
- @param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Offset The offset within the PCI configuration space for the PCI controller.\r
@param Count The number of unit to be read.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
IN PCI_TYPE00 *Pci,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
+ IN UINT64 Offset,\r
IN UINTN Count,\r
IN OUT VOID *Buffer\r
)\r
NULL,\r
Pci,\r
Width,\r
- Address,\r
+ Offset,\r
Count,\r
Buffer\r
);\r
return PciRootBridgeIo->Pci.Write (\r
PciRootBridgeIo,\r
Width,\r
- Address,\r
+ Offset,\r
Count,\r
Buffer\r
);\r
\r
@param PciIo A pointer to the EFI_PCI_O_PROTOCOL.\r
@param Width Signifies the width of the memory operations.\r
- @param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Offset The offset within the PCI configuration space for the PCI controller.\r
@param Count The number of unit to be read.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
PciIoRead (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
- IN UINT32 Address,\r
+ IN UINT32 Offset,\r
IN UINTN Count,\r
IN OUT VOID *Buffer\r
)\r
PciIo,\r
NULL,\r
(UINTN) Width,\r
- Address,\r
+ Offset,\r
Count,\r
Buffer\r
);\r
return PciIo->Pci.Read (\r
PciIo,\r
Width,\r
- Address,\r
+ Offset,\r
Count,\r
Buffer\r
);\r
PciIoWrite (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
- IN UINT32 Address,\r
+ IN UINT32 Offset,\r
IN UINTN Count,\r
IN OUT VOID *Buffer\r
)\r
PciIo,\r
NULL,\r
Width,\r
- Address,\r
+ Offset,\r
Count,\r
Buffer\r
);\r
return PciIo->Pci.Write (\r
PciIo,\r
Width,\r
- Address,\r
+ Offset,\r
Count,\r
Buffer\r
);\r
\r
**/\r
\r
-#ifndef _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H\r
-#define _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H\r
+#ifndef _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H_\r
+#define _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H_\r
\r
#include <Library/PciIncompatibleDeviceSupportLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
EFI_PCI_REGISTER_VALUE_DATA PciRegisterValueData;\r
} EFI_PCI_REGISTER_VALUE_DESCRIPTOR;\r
\r
-//\r
-// the incompatible PCI devices list for ACPI resource\r
-//\r
-GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gIncompatiblePciDeviceListForResource[] = {\r
- //\r
- // DEVICE_INF_TAG,\r
- // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
- // DEVICE_RES_TAG,\r
- // ResType, GFlag , SFlag, Granularity, RangeMin,\r
- // RangeMax, Offset, AddrLen\r
- //\r
-\r
- //\r
- // Sample Device 1\r
- //\r
- //DEVICE_INF_TAG,\r
- //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- //DEVICE_RES_TAG,\r
- //PCI_BAR_TYPE_IO,\r
- //PCI_ACPI_UNUSED,\r
- //PCI_ACPI_UNUSED,\r
- //PCI_ACPI_UNUSED,\r
- //PCI_ACPI_UNUSED,\r
- //PCI_BAR_EVEN_ALIGN,\r
- //PCI_BAR_ALL,\r
- //PCI_BAR_NOCHANGE,\r
-\r
- //\r
- // Sample Device 2\r
- //\r
- //DEVICE_INF_TAG,\r
- //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- //DEVICE_RES_TAG,\r
- //PCI_BAR_TYPE_IO,\r
- //PCI_ACPI_UNUSED,\r
- //PCI_ACPI_UNUSED,\r
- //PCI_ACPI_UNUSED,\r
- //PCI_ACPI_UNUSED,\r
- //PCI_BAR_EVEN_ALIGN,\r
- //PCI_BAR_ALL,\r
- //PCI_BAR_NOCHANGE,\r
-\r
- //\r
- // The end of the list\r
- //\r
- LIST_END_TAG\r
-};\r
-\r
-//\r
-// the incompatible PCI devices list for the values of configuration registers\r
-//\r
-GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gIncompatiblePciDeviceListForRegister[] = {\r
- //\r
- // DEVICE_INF_TAG,\r
- // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
- // PCI_RES_TAG,\r
- // PCI_ACCESS_TYPE, PCI_CONFIG_ADDRESS,\r
- // AND_VALUE, OR_VALUE\r
-\r
- //\r
- // Sample Device 1\r
- //\r
- //DEVICE_INF_TAG,\r
- //PCI_DEVICE_ID(0xXXXX, 0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- //DEVICE_RES_TAG,\r
- //PCI_REGISTER_READ,\r
- //PCI_CAPBILITY_POINTER_OFFSET,\r
- //0xffffff00,\r
- //VALUE_NOCARE,\r
-\r
- //\r
- // Sample Device 2\r
- //\r
- //DEVICE_INF_TAG,\r
- //PCI_DEVICE_ID(0xXXXX, 0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- //DEVICE_RES_TAG,\r
- //PCI_REGISTER_READ,\r
- //PCI_CAPBILITY_POINTER_OFFSET,\r
- //0xffffff00,\r
- //VALUE_NOCARE,\r
-\r
- //\r
- // The end of the list\r
- //\r
- LIST_END_TAG\r
-};\r
-\r
-//\r
-// the incompatible PCI devices list for the access width of configuration registers\r
-//\r
-GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gDeviceListForAccessWidth[] = {\r
- //\r
- // DEVICE_INF_TAG,\r
- // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
- // DEVICE_RES_TAG,\r
- // PCI_ACCESS_TYPE, PCI_ACCESS_WIDTH,\r
- // START_ADDRESS, END_ADDRESS,\r
- // ACTUAL_PCI_ACCESS_WIDTH,\r
- //\r
-\r
- //\r
- // Sample Device\r
- //\r
- //DEVICE_INF_TAG,\r
- //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- //DEVICE_RES_TAG,\r
- //PCI_REGISTER_READ,\r
- //EfiPciWidthUint8,\r
- //0,\r
- //0xFF,\r
- //EfiPciWidthUint32,\r
- //\r
-\r
- //\r
- // The end of the list\r
- //\r
- LIST_END_TAG\r
-};\r
-\r
#endif\r
\r
#include "IncompatiblePciDeviceList.h"\r
\r
-EFI_PCI_REGISTER_ACCESS_DATA mPciRegisterAccessData = {0, 0, 0}; \r
-EFI_PCI_REGISTER_VALUE_DATA mPciRegisterValueData = {0, 0};\r
+//\r
+// the incompatible PCI devices list template for ACPI resource\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gIncompatiblePciDeviceListForResource[] = {\r
+ //\r
+ // DEVICE_INF_TAG,\r
+ // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
+ // DEVICE_RES_TAG,\r
+ // ResType, GFlag , SFlag, Granularity, RangeMin,\r
+ // RangeMax, Offset, AddrLen\r
+ //\r
+\r
+ //\r
+ // Sample Device 1\r
+ //\r
+ //DEVICE_INF_TAG,\r
+ //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ //DEVICE_RES_TAG,\r
+ //PCI_BAR_TYPE_IO,\r
+ //PCI_ACPI_UNUSED,\r
+ //PCI_ACPI_UNUSED,\r
+ //PCI_ACPI_UNUSED,\r
+ //PCI_ACPI_UNUSED,\r
+ //PCI_BAR_EVEN_ALIGN,\r
+ //PCI_BAR_ALL,\r
+ //PCI_BAR_NOCHANGE,\r
+\r
+ //\r
+ // Sample Device 2\r
+ //\r
+ //DEVICE_INF_TAG,\r
+ //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ //DEVICE_RES_TAG,\r
+ //PCI_BAR_TYPE_IO,\r
+ //PCI_ACPI_UNUSED,\r
+ //PCI_ACPI_UNUSED,\r
+ //PCI_ACPI_UNUSED,\r
+ //PCI_ACPI_UNUSED,\r
+ //PCI_BAR_EVEN_ALIGN,\r
+ //PCI_BAR_ALL,\r
+ //PCI_BAR_NOCHANGE,\r
+\r
+ //\r
+ // The end of the list\r
+ //\r
+ LIST_END_TAG\r
+};\r
+\r
+//\r
+// the incompatible PCI devices list template for the values of configuration registers\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gIncompatiblePciDeviceListForRegister[] = {\r
+ //\r
+ // DEVICE_INF_TAG,\r
+ // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
+ // PCI_RES_TAG,\r
+ // PCI_ACCESS_TYPE, PCI_CONFIG_ADDRESS,\r
+ // AND_VALUE, OR_VALUE\r
+\r
+ //\r
+ // Sample Device 1\r
+ //\r
+ //DEVICE_INF_TAG,\r
+ //PCI_DEVICE_ID(0xXXXX, 0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ //DEVICE_RES_TAG,\r
+ //PCI_REGISTER_READ,\r
+ //PCI_CAPBILITY_POINTER_OFFSET,\r
+ //0xffffff00,\r
+ //VALUE_NOCARE,\r
+\r
+ //\r
+ // Sample Device 2\r
+ //\r
+ //DEVICE_INF_TAG,\r
+ //PCI_DEVICE_ID(0xXXXX, 0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ //DEVICE_RES_TAG,\r
+ //PCI_REGISTER_READ,\r
+ //PCI_CAPBILITY_POINTER_OFFSET,\r
+ //0xffffff00,\r
+ //VALUE_NOCARE,\r
+\r
+ //\r
+ // The end of the list\r
+ //\r
+ LIST_END_TAG\r
+};\r
+\r
+//\r
+// the incompatible PCI devices list template for the access width of configuration registers\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gDeviceListForAccessWidth[] = {\r
+ //\r
+ // DEVICE_INF_TAG,\r
+ // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
+ // DEVICE_RES_TAG,\r
+ // PCI_ACCESS_TYPE, PCI_ACCESS_WIDTH,\r
+ // START_ADDRESS, END_ADDRESS,\r
+ // ACTUAL_PCI_ACCESS_WIDTH,\r
+ //\r
+\r
+ //\r
+ // Sample Device\r
+ //\r
+ //DEVICE_INF_TAG,\r
+ //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ //DEVICE_RES_TAG,\r
+ //PCI_REGISTER_READ,\r
+ //EfiPciWidthUint8,\r
+ //0,\r
+ //0xFF,\r
+ //EfiPciWidthUint32,\r
+ //\r
+\r
+ //\r
+ // The end of the list\r
+ //\r
+ LIST_END_TAG\r
+};\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_REGISTER_ACCESS_DATA mPciRegisterAccessData = {0, 0, 0}; \r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_REGISTER_VALUE_DATA mPciRegisterValueData = {0, 0};\r
\r
\r
/**\r
\r
/**\r
Check the incompatible device list for access width incompatibility and\r
- return the configuration\r
+ return the configuration.\r
\r
This function searches the incompatible device list for access width\r
incompatibility according to request information. If the PCI device\r
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