Clean up ECC.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8665 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.c
index cb5d82f2e3891715fb56d469a3561a1dd1fd993d..20c2c2fcfe71c924b2b0f1c6166f5d7b4d49a58f 100644 (file)
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.c
@@ -169,7 +169,7 @@ IsRootPciHotPlugBus (
 /**\r
   Test whether device path is for root pci hot plug controller.\r
 \r
 /**\r
   Test whether device path is for root pci hot plug controller.\r
 \r

-  @param HpbDevicePath  A pointer to device path data structure to be tested.\r
+  @param HpcDevicePath  A pointer to device path data structure to be tested.\r

   @param HpIndex        If HpIndex is not NULL, return the index of root hot\r
                         plug in global array when TRUE is retuned.\r
 \r
   @param HpIndex        If HpIndex is not NULL, return the index of root hot\r
                         plug in global array when TRUE is retuned.\r
 \r

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.h b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.h
index ee6df6595aaf4bce6050545e1f446137ce8c3775..a84e256b90fc476fa141a86e9a02b8bf4743177f 100644 (file)
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.h
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.h
@@ -118,7 +118,7 @@ IsRootPciHotPlugBus (
 /**\r
   Test whether device path is for root pci hot plug controller.\r
 \r
 /**\r
   Test whether device path is for root pci hot plug controller.\r
 \r

-  @param HpbDevicePath  A pointer to device path data structure to be tested.\r
+  @param HpcDevicePath  A pointer to device path data structure to be tested.\r

   @param HpIndex        If HpIndex is not NULL, return the index of root hot\r
                         plug in global array when TRUE is retuned.\r
 \r
   @param HpIndex        If HpIndex is not NULL, return the index of root hot\r
                         plug in global array when TRUE is retuned.\r
 \r

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c
index 87425a078bb521076a5d0b4f1d6ade07f5474e95..a27f5606b6d7a44808c863954cb0035d777181ab 100644 (file)
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c
@@ -1341,7 +1341,7 @@ PciHostBridgeEnumerator (
   @param  PciIo               PCI IO protocol instance.\r
   @param  PciDeviceInfo       PCI device information.\r
   @param  Width               Signifies the width of the memory operations.\r
   @param  PciIo               PCI IO protocol instance.\r
   @param  PciDeviceInfo       PCI device information.\r
   @param  Width               Signifies the width of the memory operations.\r

-  @param  Address             The address within the PCI configuration space for the PCI controller.\r
+  @param  Offset              The offset within the PCI configuration space for the PCI controller.\r

   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r
 \r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r
 \r


@@ -1357,7 +1357,7 @@ ReadConfigData (
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,            OPTIONAL\r
   IN       EFI_PCI_DEVICE_INFO                    *PciDeviceInfo,\r
   IN       UINT64                                 Width,\r
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,            OPTIONAL\r
   IN       EFI_PCI_DEVICE_INFO                    *PciDeviceInfo,\r
   IN       UINT64                                 Width,\r

-  IN       UINT64                                 Address,\r
+  IN       UINT64                                 Offset,\r

   IN OUT   VOID                                   *Buffer\r
   )\r
 {\r
   IN OUT   VOID                                   *Buffer\r
   )\r
 {\r


@@ -1376,7 +1376,7 @@ ReadConfigData (
     //\r
     // Check access compatibility at first time\r
     //\r
     //\r
     // Check access compatibility at first time\r
     //\r

-    Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, Address & 0xff, Width, &PciRegisterAccessData);\r
+    Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, Offset & 0xff, Width, &PciRegisterAccessData);\r

 \r
     if (Status == EFI_SUCCESS) {\r
       //\r
 \r
     if (Status == EFI_SUCCESS) {\r
       //\r


@@ -1388,7 +1388,7 @@ ReadConfigData (
         AccessWidth = PciRegisterAccessData->Width;\r
       }\r
 \r
         AccessWidth = PciRegisterAccessData->Width;\r
       }\r
 \r

-      AccessAddress = Address & ~((1 << AccessWidth) - 1);\r
+      AccessAddress = Offset & ~((1 << AccessWidth) - 1);\r

 \r
       TempBuffer    = 0;\r
       Stride        = 0;\r
 \r
       TempBuffer    = 0;\r
       Stride        = 0;\r


@@ -1398,20 +1398,20 @@ ReadConfigData (
 \r
         if (PciRootBridgeIo != NULL) {\r
           Status = PciRootBridgeIo->Pci.Read (\r
 \r
         if (PciRootBridgeIo != NULL) {\r
           Status = PciRootBridgeIo->Pci.Read (\r

-                         PciRootBridgeIo,\r
-                         (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth,\r
-                         AccessAddress,\r
-                         1,\r
-                         Pointer\r
-                         );\r
+                                      PciRootBridgeIo,\r
+                                      (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth,\r
+                                      AccessAddress,\r
+                                      1,\r
+                                      Pointer\r
+                                      );\r

         } else if (PciIo != NULL) {\r
           Status = PciIo->Pci.Read (\r
         } else if (PciIo != NULL) {\r
           Status = PciIo->Pci.Read (\r

-                         PciIo,\r
-                         (EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth,\r
-                         (UINT32) AccessAddress,\r
-                         1,\r
-                         Pointer\r
-                         );\r
+                            PciIo,\r
+                            (EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth,\r
+                            (UINT32) AccessAddress,\r
+                            1,\r
+                            Pointer\r
+                            );\r

         }\r
 \r
         if (Status != EFI_SUCCESS) {\r
         }\r
 \r
         if (Status != EFI_SUCCESS) {\r


@@ -1420,7 +1420,7 @@ ReadConfigData (
 \r
        Stride = (UINTN)1 << AccessWidth;\r
         AccessAddress += Stride;\r
 \r
        Stride = (UINTN)1 << AccessWidth;\r
         AccessAddress += Stride;\r

-        if (AccessAddress >= (Address + LShiftU64 (1ULL, (UINTN)Width))) {\r
+        if (AccessAddress >= (Offset + LShiftU64 (1ULL, (UINTN)Width))) {\r

           //\r
           // If all datas have been read, exit\r
           //\r
           //\r
           // If all datas have been read, exit\r
           //\r


@@ -1470,21 +1470,21 @@ ReadConfigData (
   //\r
   if (PciRootBridgeIo != NULL) {\r
     Status = PciRootBridgeIo->Pci.Read (\r
   //\r
   if (PciRootBridgeIo != NULL) {\r
     Status = PciRootBridgeIo->Pci.Read (\r

-                     PciRootBridgeIo,\r
-                     (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
-                     Address,\r
-                     1,\r
-                     Buffer\r
-                     );\r
+                                PciRootBridgeIo,\r
+                                (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
+                                Offset,\r
+                                1,\r
+                                Buffer\r
+                                );\r

 \r
   } else {\r
     Status = PciIo->Pci.Read (\r
 \r
   } else {\r
     Status = PciIo->Pci.Read (\r

-                     PciIo,\r
-                     (EFI_PCI_IO_PROTOCOL_WIDTH) Width,\r
-                     (UINT32) Address,\r
-                     1,\r
-                     Buffer\r
-                     );\r
+                      PciIo,\r
+                      (EFI_PCI_IO_PROTOCOL_WIDTH) Width,\r
+                      (UINT32) Offset,\r
+                      1,\r
+                      Buffer\r
+                      );\r

   }\r
 \r
   return Status;\r
   }\r
 \r
   return Status;\r


@@ -1499,7 +1499,7 @@ ReadConfigData (
   @param  PciDeviceInfo       A pointer to EFI_PCI_DEVICE_INFO.\r
   @param  AccessType          Access type, READ or WRITE.\r
   @param  Width               Signifies the width of the memory operations.\r
   @param  PciDeviceInfo       A pointer to EFI_PCI_DEVICE_INFO.\r
   @param  AccessType          Access type, READ or WRITE.\r
   @param  Width               Signifies the width of the memory operations.\r

-  @param  Address             The address within the PCI configuration space.\r
+  @param  Offset              The offset within the PCI configuration space.\r

   @param  Buffer              Store the register data.\r
 \r
   @retval EFI_SUCCESS         The data has been updated.\r
   @param  Buffer              Store the register data.\r
 \r
   @retval EFI_SUCCESS         The data has been updated.\r


@@ -1512,7 +1512,7 @@ UpdateConfigData (
   IN       EFI_PCI_DEVICE_INFO                    *PciDeviceInfo,\r
   IN       UINT64                                 AccessType,\r
   IN       UINT64                                 Width,\r
   IN       EFI_PCI_DEVICE_INFO                    *PciDeviceInfo,\r
   IN       UINT64                                 AccessType,\r
   IN       UINT64                                 Width,\r

-  IN       UINT64                                 Address,\r
+  IN       UINT64                                 Offset,\r

   IN OUT   VOID                                   *Buffer\r
 )\r
 {\r
   IN OUT   VOID                                   *Buffer\r
 )\r
 {\r


@@ -1527,11 +1527,11 @@ UpdateConfigData (
   //\r
   // Check register value incompatibility\r
   //\r
   //\r
   // Check register value incompatibility\r
   //\r

-  Status = PciRegisterUpdateCheck (PciDeviceInfo, AccessType, Address & 0xff, &PciRegisterData);\r
+  Status = PciRegisterUpdateCheck (PciDeviceInfo, AccessType, Offset & 0xff, &PciRegisterData);\r

   if (Status == EFI_SUCCESS) {\r
 \r
   if (Status == EFI_SUCCESS) {\r
 \r

-    AndValue = ((UINT32) PciRegisterData->AndValue) >> (((UINT8) Address & 0x3) * 8);\r
-    OrValue  = ((UINT32) PciRegisterData->OrValue)  >> (((UINT8) Address & 0x3) * 8);\r
+    AndValue = ((UINT32) PciRegisterData->AndValue) >> (((UINT8) Offset & 0x3) * 8);\r
+    OrValue  = ((UINT32) PciRegisterData->OrValue)  >> (((UINT8) Offset & 0x3) * 8);\r

 \r
     TempValue = * (UINT32 *) Buffer;\r
     if (PciRegisterData->AndValue != VALUE_NOCARE) {\r
 \r
     TempValue = * (UINT32 *) Buffer;\r
     if (PciRegisterData->AndValue != VALUE_NOCARE) {\r


@@ -1571,7 +1571,7 @@ UpdateConfigData (
   @param  PciIo               PCI IO protocol instance.\r
   @param  PciDeviceInfo       PCI device information.\r
   @param  Width               Signifies the width of the memory operations.\r
   @param  PciIo               PCI IO protocol instance.\r
   @param  PciDeviceInfo       PCI device information.\r
   @param  Width               Signifies the width of the memory operations.\r

-  @param  Address             The address within the PCI configuration space for the PCI controller.\r
+  @param  Offset              The offset within the PCI configuration space for the PCI controller.\r

   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r
 \r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r
 \r


@@ -1586,7 +1586,7 @@ WriteConfigData (
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,            OPTIONAL\r
   IN       EFI_PCI_DEVICE_INFO                    *PciDeviceInfo,\r
   IN       UINT64                                 Width,\r
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,            OPTIONAL\r
   IN       EFI_PCI_DEVICE_INFO                    *PciDeviceInfo,\r
   IN       UINT64                                 Width,\r

-  IN       UINT64                                 Address,\r
+  IN       UINT64                                 Offset,\r

   IN       VOID                                   *Buffer\r
   )\r
 {\r
   IN       VOID                                   *Buffer\r
   )\r
 {\r


@@ -1606,7 +1606,7 @@ WriteConfigData (
     //\r
     // Check access compatibility at first time\r
     //\r
     //\r
     // Check access compatibility at first time\r
     //\r

-    Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, Address & 0xff, Width, &PciRegisterAccessData);\r
+    Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, Offset & 0xff, Width, &PciRegisterAccessData);\r

 \r
     if (Status == EFI_SUCCESS) {\r
       //\r
 \r
     if (Status == EFI_SUCCESS) {\r
       //\r


@@ -1618,7 +1618,7 @@ WriteConfigData (
         AccessWidth = PciRegisterAccessData->Width;\r
       }\r
 \r
         AccessWidth = PciRegisterAccessData->Width;\r
       }\r
 \r

-      AccessAddress = Address & ~((1 << AccessWidth) - 1);\r
+      AccessAddress = Offset & ~((1 << AccessWidth) - 1);\r

 \r
       Stride        = 0;\r
       Pointer       = (UINT8 *) &Buffer;\r
 \r
       Stride        = 0;\r
       Pointer       = (UINT8 *) &Buffer;\r


@@ -1640,7 +1640,7 @@ WriteConfigData (
           //\r
           UpdateConfigData (PciDeviceInfo, PCI_REGISTER_READ, AccessWidth, AccessAddress & 0xff, &Data);\r
 \r
           //\r
           UpdateConfigData (PciDeviceInfo, PCI_REGISTER_READ, AccessWidth, AccessAddress & 0xff, &Data);\r
 \r

-          Shift = (UINTN)(Address - AccessAddress) * 8;\r
+          Shift = (UINTN)(Offset - AccessAddress) * 8;\r

           switch (Width) {\r
           case EfiPciWidthUint8:\r
             Data = (* (UINT8 *) Buffer) << Shift | (Data & ~(0xff << Shift));\r
           switch (Width) {\r
           case EfiPciWidthUint8:\r
             Data = (* (UINT8 *) Buffer) << Shift | (Data & ~(0xff << Shift));\r


@@ -1659,20 +1659,20 @@ WriteConfigData (
 \r
         if (PciRootBridgeIo != NULL) {\r
           Status = PciRootBridgeIo->Pci.Write (\r
 \r
         if (PciRootBridgeIo != NULL) {\r
           Status = PciRootBridgeIo->Pci.Write (\r

-                         PciRootBridgeIo,\r
-                         (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth,\r
-                         AccessAddress,\r
-                         1,\r
-                         &Data\r
-                         );\r
+                                      PciRootBridgeIo,\r
+                                      (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth,\r
+                                      AccessAddress,\r
+                                      1,\r
+                                      &Data\r
+                                      );\r

         } else {\r
           Status = PciIo->Pci.Write (\r
         } else {\r
           Status = PciIo->Pci.Write (\r

-                         PciIo,\r
-                         (EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth,\r
-                         (UINT32) AccessAddress,\r
-                         1,\r
-                         &Data\r
-                         );\r
+                            PciIo,\r
+                            (EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth,\r
+                            (UINT32) AccessAddress,\r
+                            1,\r
+                            &Data\r
+                            );\r

         }\r
 \r
         if (Status != EFI_SUCCESS) {\r
         }\r
 \r
         if (Status != EFI_SUCCESS) {\r


@@ -1683,7 +1683,7 @@ WriteConfigData (
 \r
         Stride = (UINTN)1 << AccessWidth;\r
         AccessAddress += Stride;\r
 \r
         Stride = (UINTN)1 << AccessWidth;\r
         AccessAddress += Stride;\r

-        if (AccessAddress >= (Address + LShiftU64 (1ULL, (UINTN)Width))) {\r
+        if (AccessAddress >= (Offset + LShiftU64 (1ULL, (UINTN)Width))) {\r

           //\r
           // If all datas have been written, exit\r
           //\r
           //\r
           // If all datas have been written, exit\r
           //\r


@@ -1720,20 +1720,20 @@ WriteConfigData (
   //\r
   if (PciRootBridgeIo != NULL) {\r
     Status = PciRootBridgeIo->Pci.Write (\r
   //\r
   if (PciRootBridgeIo != NULL) {\r
     Status = PciRootBridgeIo->Pci.Write (\r

-                     PciRootBridgeIo,\r
-                     (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
-                     Address,\r
-                     1,\r
-                     Buffer\r
-                     );\r
+                                PciRootBridgeIo,\r
+                                (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
+                                Offset,\r
+                                1,\r
+                                Buffer\r
+                                );\r

   } else {\r
     Status = PciIo->Pci.Write (\r
   } else {\r
     Status = PciIo->Pci.Write (\r

-                   PciIo,\r
-                   (EFI_PCI_IO_PROTOCOL_WIDTH) Width,\r
-                   (UINT32) Address,\r
-                   1,\r
-                   Buffer\r
-                   );\r
+                      PciIo,\r
+                      (EFI_PCI_IO_PROTOCOL_WIDTH) Width,\r
+                      (UINT32) Offset,\r
+                      1,\r
+                      Buffer\r
+                      );\r

   }\r
 \r
   return Status;\r
   }\r
 \r
   return Status;\r


@@ -1745,7 +1745,7 @@ WriteConfigData (
   @param  PciRootBridgeIo     A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param  PciIo               A pointer to EFI_PCI_PROTOCOL.\r
   @param  Pci                 PCI device configuration space.\r
   @param  PciRootBridgeIo     A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param  PciIo               A pointer to EFI_PCI_PROTOCOL.\r
   @param  Pci                 PCI device configuration space.\r

-  @param  Address             The address within the PCI configuration space for the PCI controller.\r
+  @param  Offset              The offset within the PCI configuration space for the PCI controller.\r

   @param  PciDeviceInfo       A pointer to EFI_PCI_DEVICE_INFO.\r
 \r
   @retval EFI_SUCCESS         Pci device device information has been abstracted.\r
   @param  PciDeviceInfo       A pointer to EFI_PCI_DEVICE_INFO.\r
 \r
   @retval EFI_SUCCESS         Pci device device information has been abstracted.\r


@@ -1758,7 +1758,7 @@ GetPciDeviceDeviceInfo (
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *PciRootBridgeIo,  OPTIONAL\r
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,            OPTIONAL\r
   IN       PCI_TYPE00                             *Pci,              OPTIONAL\r
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *PciRootBridgeIo,  OPTIONAL\r
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,            OPTIONAL\r
   IN       PCI_TYPE00                             *Pci,              OPTIONAL\r

-  IN       UINT64                                 Address,           OPTIONAL\r
+  IN       UINT64                                 Offset,           OPTIONAL\r

   OUT      EFI_PCI_DEVICE_INFO                    *PciDeviceInfo\r
 )\r
 {\r
   OUT      EFI_PCI_DEVICE_INFO                    *PciDeviceInfo\r
 )\r
 {\r


@@ -1783,14 +1783,14 @@ GetPciDeviceDeviceInfo (
     //\r
     // While PCI_TYPE00 hasn't been gotten, read PCI device device information directly\r
     //\r
     //\r
     // While PCI_TYPE00 hasn't been gotten, read PCI device device information directly\r
     //\r

-    PciAddress = Address & 0xffffffffffffff00ULL;\r
+    PciAddress = Offset & 0xffffffffffffff00ULL;\r

     Status = PciRootBridgeIo->Pci.Read (\r
     Status = PciRootBridgeIo->Pci.Read (\r

-                                    PciRootBridgeIo,\r
-                                    EfiPciWidthUint32,\r
-                                    PciAddress,\r
-                                    1,\r
-                                    &PciConfigData\r
-                                    );\r
+                                PciRootBridgeIo,\r
+                                EfiPciWidthUint32,\r
+                                PciAddress,\r
+                                1,\r
+                                &PciConfigData\r
+                                );\r

 \r
     if (EFI_ERROR (Status)) {\r
       return Status;\r
 \r
     if (EFI_ERROR (Status)) {\r
       return Status;\r


@@ -1804,12 +1804,12 @@ GetPciDeviceDeviceInfo (
     PciDeviceInfo->DeviceID = PciConfigData >> 16;\r
 \r
     Status = PciRootBridgeIo->Pci.Read (\r
     PciDeviceInfo->DeviceID = PciConfigData >> 16;\r
 \r
     Status = PciRootBridgeIo->Pci.Read (\r

-                                    PciRootBridgeIo,\r
-                                    EfiPciWidthUint32,\r
-                                    PciAddress + 8,\r
-                                    1,\r
-                                    &PciConfigData\r
-                                    );\r
+                                PciRootBridgeIo,\r
+                                EfiPciWidthUint32,\r
+                                PciAddress + 8,\r
+                                1,\r
+                                &PciConfigData\r
+                                );\r

     if (EFI_ERROR (Status)) {\r
       return Status;\r
     }\r
     if (EFI_ERROR (Status)) {\r
       return Status;\r
     }\r


@@ -1817,12 +1817,12 @@ GetPciDeviceDeviceInfo (
     PciDeviceInfo->RevisionID = PciConfigData & 0xf;\r
 \r
     Status = PciRootBridgeIo->Pci.Read (\r
     PciDeviceInfo->RevisionID = PciConfigData & 0xf;\r
 \r
     Status = PciRootBridgeIo->Pci.Read (\r

-                                    PciRootBridgeIo,\r
-                                    EfiPciWidthUint32,\r
-                                    PciAddress + 0x2c,\r
-                                    1,\r
-                                    &PciConfigData\r
-                                    );\r
+                                PciRootBridgeIo,\r
+                                EfiPciWidthUint32,\r
+                                PciAddress + 0x2c,\r
+                                1,\r
+                                &PciConfigData\r
+                                );\r

 \r
     if (EFI_ERROR (Status)) {\r
       return Status;\r
 \r
     if (EFI_ERROR (Status)) {\r
       return Status;\r


@@ -1849,7 +1849,7 @@ GetPciDeviceDeviceInfo (
   @param  PciIo               A pointer to the EFI_PCI_IO_PROTOCOL.\r
   @param  Pci                 A pointer to PCI_TYPE00.\r
   @param  Width               Signifies the width of the memory operations.\r
   @param  PciIo               A pointer to the EFI_PCI_IO_PROTOCOL.\r
   @param  Pci                 A pointer to PCI_TYPE00.\r
   @param  Width               Signifies the width of the memory operations.\r

-  @param  Address             The address within the PCI configuration space for the PCI controller.\r
+  @param  Offset              The offset within the PCI configuration space for the PCI controller.\r

   @param  Count               The number of unit to be read.\r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r
   @param  Count               The number of unit to be read.\r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r


@@ -1865,7 +1865,7 @@ PciIncompatibilityCheckRead (
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,             OPTIONAL\r
   IN       PCI_TYPE00                             *Pci,               OPTIONAL\r
   IN       UINTN                                  Width,\r
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,             OPTIONAL\r
   IN       PCI_TYPE00                             *Pci,               OPTIONAL\r
   IN       UINTN                                  Width,\r

-  IN       UINT64                                 Address,\r
+  IN       UINT64                                 Offset,\r

   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   )\r
   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   )\r


@@ -1882,19 +1882,19 @@ PciIncompatibilityCheckRead (
   //\r
   // get PCI device device information\r
   //\r
   //\r
   // get PCI device device information\r
   //\r

-  Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Address, &PciDeviceInfo);\r
+  Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Offset, &PciDeviceInfo);\r

   if (Status != EFI_SUCCESS) {\r
     return Status;\r
   }\r
 \r
   Stride = 1 << Width;\r
 \r
   if (Status != EFI_SUCCESS) {\r
     return Status;\r
   }\r
 \r
   Stride = 1 << Width;\r
 \r

-  for (; Count > 0; Count--, Address += Stride, Buffer = (UINT8 *)Buffer + Stride) {\r
+  for (; Count > 0; Count--, Offset += Stride, Buffer = (UINT8 *)Buffer + Stride) {\r

 \r
     //\r
     // read configuration register\r
     //\r
 \r
     //\r
     // read configuration register\r
     //\r

-    Status = ReadConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, (UINT64) Width, Address, Buffer);\r
+    Status = ReadConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, (UINT64) Width, Offset, Buffer);\r

 \r
     if (Status != EFI_SUCCESS) {\r
       return Status;\r
 \r
     if (Status != EFI_SUCCESS) {\r
       return Status;\r


@@ -1904,7 +1904,7 @@ PciIncompatibilityCheckRead (
     // update the data read from configuration register\r
     //\r
     if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) {\r
     // update the data read from configuration register\r
     //\r
     if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) {\r

-      UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_READ, Width, Address & 0xff, Buffer);\r
+      UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_READ, Width, Offset & 0xff, Buffer);\r

     }\r
   }\r
 \r
     }\r
   }\r
 \r


@@ -1918,7 +1918,7 @@ PciIncompatibilityCheckRead (
   @param  PciIo               A pointer to the EFI_PCI_IO_PROTOCOL.\r
   @param  Pci                 A pointer to PCI_TYPE00.\r
   @param  Width               Signifies the width of the memory operations.\r
   @param  PciIo               A pointer to the EFI_PCI_IO_PROTOCOL.\r
   @param  Pci                 A pointer to PCI_TYPE00.\r
   @param  Width               Signifies the width of the memory operations.\r

-  @param  Address             The address within the PCI configuration space for the PCI controller.\r
+  @param  Offset              The offset within the PCI configuration space for the PCI controller.\r

   @param  Count               The number of unit to be write.\r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r
   @param  Count               The number of unit to be write.\r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r


@@ -1936,7 +1936,7 @@ PciIncompatibilityCheckWrite (
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,             OPTIONAL\r
   IN       PCI_TYPE00                             *Pci,               OPTIONAL\r
   IN       UINTN                                  Width,\r
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,             OPTIONAL\r
   IN       PCI_TYPE00                             *Pci,               OPTIONAL\r
   IN       UINTN                                  Width,\r

-  IN       UINT64                                 Address,\r
+  IN       UINT64                                 Offset,\r

   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   )\r
   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   )\r


@@ -1954,14 +1954,14 @@ PciIncompatibilityCheckWrite (
   //\r
   // Get PCI device device information\r
   //\r
   //\r
   // Get PCI device device information\r
   //\r

-  Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Address, &PciDeviceInfo);\r
+  Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Offset, &PciDeviceInfo);\r

   if (Status != EFI_SUCCESS) {\r
     return Status;\r
   }\r
 \r
   Stride = 1 << Width;\r
 \r
   if (Status != EFI_SUCCESS) {\r
     return Status;\r
   }\r
 \r
   Stride = 1 << Width;\r
 \r

-  for (; Count > 0; Count--, Address += Stride, Buffer = (UINT8 *) Buffer + Stride) {\r
+  for (; Count > 0; Count--, Offset += Stride, Buffer = (UINT8 *) Buffer + Stride) {\r

 \r
     Data = 0;\r
 \r
 \r
     Data = 0;\r
 \r


@@ -1985,13 +1985,13 @@ PciIncompatibilityCheckWrite (
     // Update the data writen into configuration register\r
     //\r
     if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) {\r
     // Update the data writen into configuration register\r
     //\r
     if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) {\r

-      UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_WRITE, Width, Address & 0xff, &Data);\r
+      UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_WRITE, Width, Offset & 0xff, &Data);\r

     }\r
 \r
     //\r
     // Write configuration register\r
     //\r
     }\r
 \r
     //\r
     // Write configuration register\r
     //\r

-    Status = WriteConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, Width, Address, &Data);\r
+    Status = WriteConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, Width, Offset, &Data);\r

 \r
     if (Status != EFI_SUCCESS) {\r
       return Status;\r
 \r
     if (Status != EFI_SUCCESS) {\r
       return Status;\r


@@ -2007,7 +2007,7 @@ PciIncompatibilityCheckWrite (
   @param  PciRootBridgeIo     A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param  Pci                 A pointer to PCI_TYPE00.\r
   @param  Width               Signifies the width of the memory operations.\r
   @param  PciRootBridgeIo     A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param  Pci                 A pointer to PCI_TYPE00.\r
   @param  Width               Signifies the width of the memory operations.\r

-  @param  Address             The address within the PCI configuration space for the PCI controller.\r
+  @param  Offset              The offset within the PCI configuration space for the PCI controller.\r

   @param  Count               The number of unit to be read.\r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r
   @param  Count               The number of unit to be read.\r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r


@@ -2022,7 +2022,7 @@ PciRootBridgeIoRead (
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *PciRootBridgeIo,\r
   IN       PCI_TYPE00                             *Pci,            OPTIONAL\r
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *PciRootBridgeIo,\r
   IN       PCI_TYPE00                             *Pci,            OPTIONAL\r
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r

-  IN       UINT64                                 Address,\r
+  IN       UINT64                                 Offset,\r

   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   )\r
   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   )\r


@@ -2038,7 +2038,7 @@ PciRootBridgeIoRead (
                NULL,\r
                Pci,\r
                (UINTN) Width,\r
                NULL,\r
                Pci,\r
                (UINTN) Width,\r

-               Address,\r
+               Offset,\r

                Count,\r
                Buffer\r
                );\r
                Count,\r
                Buffer\r
                );\r


@@ -2051,7 +2051,7 @@ PciRootBridgeIoRead (
     return PciRootBridgeIo->Pci.Read (\r
                               PciRootBridgeIo,\r
                               Width,\r
     return PciRootBridgeIo->Pci.Read (\r
                               PciRootBridgeIo,\r
                               Width,\r

-                              Address,\r
+                              Offset,\r

                               Count,\r
                               Buffer\r
                               );\r
                               Count,\r
                               Buffer\r
                               );\r


@@ -2064,7 +2064,7 @@ PciRootBridgeIoRead (
   @param  PciRootBridgeIo     A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param  Pci                 A pointer to PCI_TYPE00.\r
   @param  Width               Signifies the width of the memory operations.\r
   @param  PciRootBridgeIo     A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param  Pci                 A pointer to PCI_TYPE00.\r
   @param  Width               Signifies the width of the memory operations.\r

-  @param  Address             The address within the PCI configuration space for the PCI controller.\r
+  @param  Offset              The offset within the PCI configuration space for the PCI controller.\r

   @param  Count               The number of unit to be read.\r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r
   @param  Count               The number of unit to be read.\r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r


@@ -2079,7 +2079,7 @@ PciRootBridgeIoWrite (
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *PciRootBridgeIo,\r
   IN       PCI_TYPE00                             *Pci,\r
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *PciRootBridgeIo,\r
   IN       PCI_TYPE00                             *Pci,\r
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r

-  IN       UINT64                                 Address,\r
+  IN       UINT64                                 Offset,\r

   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   )\r
   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   )\r


@@ -2095,7 +2095,7 @@ PciRootBridgeIoWrite (
                NULL,\r
                Pci,\r
                Width,\r
                NULL,\r
                Pci,\r
                Width,\r

-               Address,\r
+               Offset,\r

                Count,\r
                Buffer\r
                );\r
                Count,\r
                Buffer\r
                );\r


@@ -2109,7 +2109,7 @@ PciRootBridgeIoWrite (
     return  PciRootBridgeIo->Pci.Write (\r
                                PciRootBridgeIo,\r
                                Width,\r
     return  PciRootBridgeIo->Pci.Write (\r
                                PciRootBridgeIo,\r
                                Width,\r

-                               Address,\r
+                               Offset,\r

                                Count,\r
                                Buffer\r
                                );\r
                                Count,\r
                                Buffer\r
                                );\r


@@ -2121,7 +2121,7 @@ PciRootBridgeIoWrite (
 \r
   @param  PciIo               A pointer to the EFI_PCI_O_PROTOCOL.\r
   @param  Width               Signifies the width of the memory operations.\r
 \r
   @param  PciIo               A pointer to the EFI_PCI_O_PROTOCOL.\r
   @param  Width               Signifies the width of the memory operations.\r

-  @param  Address             The address within the PCI configuration space for the PCI controller.\r
+  @param  Offset              The offset within the PCI configuration space for the PCI controller.\r

   @param  Count               The number of unit to be read.\r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r
   @param  Count               The number of unit to be read.\r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r


@@ -2137,7 +2137,7 @@ EFI_STATUS
 PciIoRead (\r
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,\r
   IN       EFI_PCI_IO_PROTOCOL_WIDTH              Width,\r
 PciIoRead (\r
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,\r
   IN       EFI_PCI_IO_PROTOCOL_WIDTH              Width,\r

-  IN       UINT32                                 Address,\r
+  IN       UINT32                                 Offset,\r

   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   )\r
   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   )\r


@@ -2151,7 +2151,7 @@ PciIoRead (
              PciIo,\r
              NULL,\r
              (UINTN) Width,\r
              PciIo,\r
              NULL,\r
              (UINTN) Width,\r

-             Address,\r
+             Offset,\r

              Count,\r
              Buffer\r
              );\r
              Count,\r
              Buffer\r
              );\r


@@ -2159,7 +2159,7 @@ PciIoRead (
     return PciIo->Pci.Read (\r
                     PciIo,\r
                     Width,\r
     return PciIo->Pci.Read (\r
                     PciIo,\r
                     Width,\r

-                    Address,\r
+                    Offset,\r

                     Count,\r
                     Buffer\r
                     );\r
                     Count,\r
                     Buffer\r
                     );\r


@@ -2189,7 +2189,7 @@ EFI_STATUS
 PciIoWrite (\r
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,\r
   IN       EFI_PCI_IO_PROTOCOL_WIDTH              Width,\r
 PciIoWrite (\r
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,\r
   IN       EFI_PCI_IO_PROTOCOL_WIDTH              Width,\r

-  IN       UINT32                                 Address,\r
+  IN       UINT32                                 Offset,\r

   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   )\r
   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   )\r


@@ -2203,7 +2203,7 @@ PciIoWrite (
               PciIo,\r
               NULL,\r
               Width,\r
               PciIo,\r
               NULL,\r
               Width,\r

-              Address,\r
+              Offset,\r

               Count,\r
               Buffer\r
               );\r
               Count,\r
               Buffer\r
               );\r


@@ -2212,7 +2212,7 @@ PciIoWrite (
     return PciIo->Pci.Write (\r
                     PciIo,\r
                     Width,\r
     return PciIo->Pci.Write (\r
                     PciIo,\r
                     Width,\r

-                    Address,\r
+                    Offset,\r

                     Count,\r
                     Buffer\r
                     );\r
                     Count,\r
                     Buffer\r
                     );\r

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.h b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.h
index c758315d1a9b4e6d5665d9e31df694aae371a2de..e5beaa671e91ca399c8383f2aebec04c716e1669 100644 (file)
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.h
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.h
@@ -154,7 +154,7 @@ PciHostBridgeEnumerator (
 \r
   @param  PciIo               A pointer to the EFI_PCI_O_PROTOCOL.\r
   @param  Width               Signifies the width of the memory operations.\r
 \r
   @param  PciIo               A pointer to the EFI_PCI_O_PROTOCOL.\r
   @param  Width               Signifies the width of the memory operations.\r

-  @param  Address             The address within the PCI configuration space for the PCI controller.\r
+  @param  Offset              The offset within the PCI configuration space for the PCI controller.\r

   @param  Count               The number of unit to be read.\r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r
   @param  Count               The number of unit to be read.\r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r


@@ -170,7 +170,7 @@ EFI_STATUS
 PciIoRead (\r
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,\r
   IN       EFI_PCI_IO_PROTOCOL_WIDTH              Width,\r
 PciIoRead (\r
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,\r
   IN       EFI_PCI_IO_PROTOCOL_WIDTH              Width,\r

-  IN       UINT32                                 Address,\r
+  IN       UINT32                                 Offset,\r

   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   );\r
   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   );\r


@@ -198,7 +198,7 @@ EFI_STATUS
 PciIoWrite (\r
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,\r
   IN       EFI_PCI_IO_PROTOCOL_WIDTH              Width,\r
 PciIoWrite (\r
   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,\r
   IN       EFI_PCI_IO_PROTOCOL_WIDTH              Width,\r

-  IN       UINT32                                 Address,\r
+  IN       UINT32                                 Offset,\r

   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   );\r
   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   );\r


@@ -209,7 +209,7 @@ PciIoWrite (
   @param  PciRootBridgeIo     A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param  Pci                 A pointer to PCI_TYPE00.\r
   @param  Width               Signifies the width of the memory operations.\r
   @param  PciRootBridgeIo     A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param  Pci                 A pointer to PCI_TYPE00.\r
   @param  Width               Signifies the width of the memory operations.\r

-  @param  Address             The address within the PCI configuration space for the PCI controller.\r
+  @param  Offset              The offset within the PCI configuration space for the PCI controller.\r

   @param  Count               The number of unit to be read.\r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r
   @param  Count               The number of unit to be read.\r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r


@@ -224,7 +224,7 @@ PciRootBridgeIoWrite (
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *PciRootBridgeIo,\r
   IN       PCI_TYPE00                             *Pci,\r
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *PciRootBridgeIo,\r
   IN       PCI_TYPE00                             *Pci,\r
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r

-  IN       UINT64                                 Address,\r
+  IN       UINT64                                 Offset,\r

   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   );\r
   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   );\r


@@ -235,7 +235,7 @@ PciRootBridgeIoWrite (
   @param  PciRootBridgeIo     A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param  Pci                 A pointer to PCI_TYPE00.\r
   @param  Width               Signifies the width of the memory operations.\r
   @param  PciRootBridgeIo     A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param  Pci                 A pointer to PCI_TYPE00.\r
   @param  Width               Signifies the width of the memory operations.\r

-  @param  Address             The address within the PCI configuration space for the PCI controller.\r
+  @param  Offset              The offset within the PCI configuration space for the PCI controller.\r

   @param  Count               The number of unit to be read.\r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r
   @param  Count               The number of unit to be read.\r
   @param  Buffer              For read operations, the destination buffer to store the results. For\r
                               write operations, the source buffer to write data from.\r


@@ -250,8 +250,9 @@ PciRootBridgeIoRead (
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *PciRootBridgeIo,\r
   IN       PCI_TYPE00                             *Pci,            OPTIONAL\r
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *PciRootBridgeIo,\r
   IN       PCI_TYPE00                             *Pci,            OPTIONAL\r
   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r

-  IN       UINT64                                 Address,\r
+  IN       UINT64                                 Offset,\r

   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   );\r
   IN       UINTN                                  Count,\r
   IN OUT   VOID                                   *Buffer\r
   );\r

+\r

 #endif\r
 #endif\r

diff --git a/IntelFrameworkModulePkg/Include/Library/PciIncompatibleDeviceSupportLib.h b/IntelFrameworkModulePkg/Include/Library/PciIncompatibleDeviceSupportLib.h
index f9efd074267143f64c1e7c7c0e2b9ea0876427b0..f490ae4106e5de59ee908e275ae6de676b841880 100644 (file)
--- a/IntelFrameworkModulePkg/Include/Library/PciIncompatibleDeviceSupportLib.h
+++ b/IntelFrameworkModulePkg/Include/Library/PciIncompatibleDeviceSupportLib.h
@@ -115,7 +115,7 @@ PciRegisterUpdateCheck (
 \r
 /**\r
   Check the incompatible device list for access width incompatibility and\r
 \r
 /**\r
   Check the incompatible device list for access width incompatibility and\r

-  return the configuration\r
+  return the configuration.\r

 \r
   This function searches the incompatible device list for access width\r
   incompatibility according to request information. If the PCI device\r
 \r
   This function searches the incompatible device list for access width\r
   incompatibility according to request information. If the PCI device\r

diff --git a/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/IncompatiblePciDeviceList.h b/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/IncompatiblePciDeviceList.h
index 53609c0bfcb27e5715ec50cd51a9da5a2c2c09ef..49ac0ad850a4286c5267dde52f65c6c5ac6af4ab 100644 (file)
--- a/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/IncompatiblePciDeviceList.h
+++ b/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/IncompatiblePciDeviceList.h
@@ -12,8 +12,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 **/\r
 \r
 \r
 **/\r
 \r

-#ifndef _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H\r
-#define _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H\r
+#ifndef _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H_\r
+#define _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H_\r

 \r
 #include <Library/PciIncompatibleDeviceSupportLib.h>\r
 #include <Library/MemoryAllocationLib.h>\r
 \r
 #include <Library/PciIncompatibleDeviceSupportLib.h>\r
 #include <Library/MemoryAllocationLib.h>\r


@@ -51,123 +51,4 @@ typedef struct {
   EFI_PCI_REGISTER_VALUE_DATA    PciRegisterValueData;\r
 } EFI_PCI_REGISTER_VALUE_DESCRIPTOR;\r
 \r
   EFI_PCI_REGISTER_VALUE_DATA    PciRegisterValueData;\r
 } EFI_PCI_REGISTER_VALUE_DESCRIPTOR;\r
 \r

-//\r
-// the incompatible PCI devices list for ACPI resource\r
-//\r
-GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gIncompatiblePciDeviceListForResource[] = {\r
-  //\r
-  // DEVICE_INF_TAG,\r
-  // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
-  // DEVICE_RES_TAG,\r
-  // ResType,  GFlag , SFlag,   Granularity,  RangeMin,\r
-  // RangeMax, Offset, AddrLen\r
-  //\r
-\r
-  //\r
-  // Sample Device 1\r
-  //\r
-  //DEVICE_INF_TAG,\r
-  //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
-  //DEVICE_RES_TAG,\r
-  //PCI_BAR_TYPE_IO,\r
-  //PCI_ACPI_UNUSED,\r
-  //PCI_ACPI_UNUSED,\r
-  //PCI_ACPI_UNUSED,\r
-  //PCI_ACPI_UNUSED,\r
-  //PCI_BAR_EVEN_ALIGN,\r
-  //PCI_BAR_ALL,\r
-  //PCI_BAR_NOCHANGE,\r
-\r
-  //\r
-  // Sample Device 2\r
-  //\r
-  //DEVICE_INF_TAG,\r
-  //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
-  //DEVICE_RES_TAG,\r
-  //PCI_BAR_TYPE_IO,\r
-  //PCI_ACPI_UNUSED,\r
-  //PCI_ACPI_UNUSED,\r
-  //PCI_ACPI_UNUSED,\r
-  //PCI_ACPI_UNUSED,\r
-  //PCI_BAR_EVEN_ALIGN,\r
-  //PCI_BAR_ALL,\r
-  //PCI_BAR_NOCHANGE,\r
-\r
-  //\r
-  // The end of the list\r
-  //\r
-  LIST_END_TAG\r
-};\r
-\r
-//\r
-// the incompatible PCI devices list for the values of configuration registers\r
-//\r
-GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gIncompatiblePciDeviceListForRegister[] = {\r
-  //\r
-  // DEVICE_INF_TAG,\r
-  // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
-  // PCI_RES_TAG,\r
-  // PCI_ACCESS_TYPE, PCI_CONFIG_ADDRESS,\r
-  // AND_VALUE, OR_VALUE\r
-\r
-  //\r
-  // Sample Device 1\r
-  //\r
-  //DEVICE_INF_TAG,\r
-  //PCI_DEVICE_ID(0xXXXX, 0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
-  //DEVICE_RES_TAG,\r
-  //PCI_REGISTER_READ,\r
-  //PCI_CAPBILITY_POINTER_OFFSET,\r
-  //0xffffff00,\r
-  //VALUE_NOCARE,\r
-\r
-  //\r
-  // Sample Device 2\r
-  //\r
-  //DEVICE_INF_TAG,\r
-  //PCI_DEVICE_ID(0xXXXX, 0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
-  //DEVICE_RES_TAG,\r
-  //PCI_REGISTER_READ,\r
-  //PCI_CAPBILITY_POINTER_OFFSET,\r
-  //0xffffff00,\r
-  //VALUE_NOCARE,\r
-\r
-  //\r
-  // The end of the list\r
-  //\r
-  LIST_END_TAG\r
-};\r
-\r
-//\r
-// the incompatible PCI devices list for the access width of configuration registers\r
-//\r
-GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gDeviceListForAccessWidth[] = {\r
-  //\r
-  // DEVICE_INF_TAG,\r
-  // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
-  // DEVICE_RES_TAG,\r
-  // PCI_ACCESS_TYPE, PCI_ACCESS_WIDTH,\r
-  // START_ADDRESS, END_ADDRESS,\r
-  // ACTUAL_PCI_ACCESS_WIDTH,\r
-  //\r
-\r
-  //\r
-  // Sample Device\r
-  //\r
-  //DEVICE_INF_TAG,\r
-  //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
-  //DEVICE_RES_TAG,\r
-  //PCI_REGISTER_READ,\r
-  //EfiPciWidthUint8,\r
-  //0,\r
-  //0xFF,\r
-  //EfiPciWidthUint32,\r
-  //\r
-\r
-  //\r
-  // The end of the list\r
-  //\r
-  LIST_END_TAG\r
-};\r
-\r

 #endif\r
 #endif\r

diff --git a/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.c b/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.c
index 4934d4e2c1d0ff7e42c6349616e9d923425c473c..21d527408bdca671b660c7052b9f51ca6d98c015 100644 (file)
--- a/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.c
+++ b/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.c
@@ -14,8 +14,127 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 #include "IncompatiblePciDeviceList.h"\r
 \r
 \r
 #include "IncompatiblePciDeviceList.h"\r
 \r

-EFI_PCI_REGISTER_ACCESS_DATA mPciRegisterAccessData = {0, 0, 0}; \r
-EFI_PCI_REGISTER_VALUE_DATA  mPciRegisterValueData  = {0, 0};\r
+//\r
+// the incompatible PCI devices list template for ACPI resource\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gIncompatiblePciDeviceListForResource[] = {\r
+  //\r
+  // DEVICE_INF_TAG,\r
+  // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
+  // DEVICE_RES_TAG,\r
+  // ResType,  GFlag , SFlag,   Granularity,  RangeMin,\r
+  // RangeMax, Offset, AddrLen\r
+  //\r
+\r
+  //\r
+  // Sample Device 1\r
+  //\r
+  //DEVICE_INF_TAG,\r
+  //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+  //DEVICE_RES_TAG,\r
+  //PCI_BAR_TYPE_IO,\r
+  //PCI_ACPI_UNUSED,\r
+  //PCI_ACPI_UNUSED,\r
+  //PCI_ACPI_UNUSED,\r
+  //PCI_ACPI_UNUSED,\r
+  //PCI_BAR_EVEN_ALIGN,\r
+  //PCI_BAR_ALL,\r
+  //PCI_BAR_NOCHANGE,\r
+\r
+  //\r
+  // Sample Device 2\r
+  //\r
+  //DEVICE_INF_TAG,\r
+  //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+  //DEVICE_RES_TAG,\r
+  //PCI_BAR_TYPE_IO,\r
+  //PCI_ACPI_UNUSED,\r
+  //PCI_ACPI_UNUSED,\r
+  //PCI_ACPI_UNUSED,\r
+  //PCI_ACPI_UNUSED,\r
+  //PCI_BAR_EVEN_ALIGN,\r
+  //PCI_BAR_ALL,\r
+  //PCI_BAR_NOCHANGE,\r
+\r
+  //\r
+  // The end of the list\r
+  //\r
+  LIST_END_TAG\r
+};\r
+\r
+//\r
+// the incompatible PCI devices list template for the values of configuration registers\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gIncompatiblePciDeviceListForRegister[] = {\r
+  //\r
+  // DEVICE_INF_TAG,\r
+  // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
+  // PCI_RES_TAG,\r
+  // PCI_ACCESS_TYPE, PCI_CONFIG_ADDRESS,\r
+  // AND_VALUE, OR_VALUE\r
+\r
+  //\r
+  // Sample Device 1\r
+  //\r
+  //DEVICE_INF_TAG,\r
+  //PCI_DEVICE_ID(0xXXXX, 0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+  //DEVICE_RES_TAG,\r
+  //PCI_REGISTER_READ,\r
+  //PCI_CAPBILITY_POINTER_OFFSET,\r
+  //0xffffff00,\r
+  //VALUE_NOCARE,\r
+\r
+  //\r
+  // Sample Device 2\r
+  //\r
+  //DEVICE_INF_TAG,\r
+  //PCI_DEVICE_ID(0xXXXX, 0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+  //DEVICE_RES_TAG,\r
+  //PCI_REGISTER_READ,\r
+  //PCI_CAPBILITY_POINTER_OFFSET,\r
+  //0xffffff00,\r
+  //VALUE_NOCARE,\r
+\r
+  //\r
+  // The end of the list\r
+  //\r
+  LIST_END_TAG\r
+};\r
+\r
+//\r
+// the incompatible PCI devices list template for the access width of configuration registers\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gDeviceListForAccessWidth[] = {\r
+  //\r
+  // DEVICE_INF_TAG,\r
+  // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
+  // DEVICE_RES_TAG,\r
+  // PCI_ACCESS_TYPE, PCI_ACCESS_WIDTH,\r
+  // START_ADDRESS, END_ADDRESS,\r
+  // ACTUAL_PCI_ACCESS_WIDTH,\r
+  //\r
+\r
+  //\r
+  // Sample Device\r
+  //\r
+  //DEVICE_INF_TAG,\r
+  //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+  //DEVICE_RES_TAG,\r
+  //PCI_REGISTER_READ,\r
+  //EfiPciWidthUint8,\r
+  //0,\r
+  //0xFF,\r
+  //EfiPciWidthUint32,\r
+  //\r
+\r
+  //\r
+  // The end of the list\r
+  //\r
+  LIST_END_TAG\r
+};\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_REGISTER_ACCESS_DATA mPciRegisterAccessData = {0, 0, 0}; \r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_REGISTER_VALUE_DATA  mPciRegisterValueData  = {0, 0};\r

  \r
 \r
 /**\r
  \r
 \r
 /**\r


@@ -299,7 +418,7 @@ PciRegisterUpdateCheck (
 \r
 /**\r
   Check the incompatible device list for access width incompatibility and\r
 \r
 /**\r
   Check the incompatible device list for access width incompatibility and\r

-  return the configuration\r
+  return the configuration.\r

 \r
   This function searches the incompatible device list for access width\r
   incompatibility according to request information. If the PCI device\r
 \r
   This function searches the incompatible device list for access width\r
   incompatibility according to request information. If the PCI device\r