Allocate Tile size based on Page.

We had better separate code from data in tile in page level,
so that other program may use page level protection on that.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18957 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 2489848c794f807d3a137271a0eeaf38d145ff89..670a5cf663f8c573a65aa061caaf7176743a9d7f 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -760,6 +760,9 @@ PiCpuSmmEntry (
   UINTN                      NumberOfEnabledProcessors;\r
   UINTN                      Index;\r
   VOID                       *Buffer;\r
+  UINTN                      BufferPages;\r
+  UINTN                      TileCodeSize;\r
+  UINTN                      TileDataSize;\r
   UINTN                      TileSize;\r
   VOID                       *GuidHob;\r
   EFI_SMRAM_DESCRIPTOR       *SmramDescriptor;\r
@@ -937,9 +940,13 @@ PiCpuSmmEntry (
   // specific context in a PROCESSOR_SMM_DESCRIPTOR, and the SMI entry point.  This size\r
   // is rounded up to nearest power of 2.\r
   //\r
-  TileSize = sizeof (SMRAM_SAVE_STATE_MAP) + sizeof (PROCESSOR_SMM_DESCRIPTOR) + GetSmiHandlerSize () - 1;\r
+  TileCodeSize = GetSmiHandlerSize ();\r
+  TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);\r
+  TileDataSize = sizeof (SMRAM_SAVE_STATE_MAP) + sizeof (PROCESSOR_SMM_DESCRIPTOR);\r
+  TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);\r
+  TileSize = TileDataSize + TileCodeSize - 1;\r
   TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);\r
-  DEBUG ((EFI_D_INFO, "SMRAM TileSize = %08x\n", TileSize));\r
+  DEBUG ((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));\r
 \r
   //\r
   // If the TileSize is larger than space available for the SMI Handler of CPU[i],\r
@@ -961,12 +968,14 @@ PiCpuSmmEntry (
   // Intel486 processors: FamilyId is 4\r
   // Pentium processors : FamilyId is 5\r
   //\r
+  BufferPages = EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1));\r
   if ((FamilyId == 4) || (FamilyId == 5)) {\r
-    Buffer = AllocateAlignedPages (EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1)), SIZE_32KB);\r
+    Buffer = AllocateAlignedCodePages (BufferPages, SIZE_32KB);\r
   } else {\r
-    Buffer = AllocatePages (EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1)));\r
+    Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB);\r
   }\r
   ASSERT (Buffer != NULL);\r
+  DEBUG ((EFI_D_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE(BufferPages)));\r
 \r
   //\r
   // Allocate buffer for pointers to array in  SMM_CPU_PRIVATE_DATA.\r