+/*++\r
+\r
+Copyright (c) 2009, Hewlett-Packard Company \r
+Portions copyright (c) 2010, Apple Inc. All rights reserved.\r
+\r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+\r
+--*/\r
+\r
+#include "CpuDxe.h"\r
+\r
+//\r
+// Translation/page table definitions\r
+//\r
+\r
+// First Level Descriptors\r
+typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;\r
+\r
+// memory space covered by a first level descriptor\r
+#define ARM_PAGE_DESC_ENTRY_MVA_SIZE 0x00100000 // 1MB\r
+\r
+// number of first level descriptors to cover entire 32-bit memory space\r
+#define FIRST_LEVEL_ENTRY_COUNT (0xFFFFFFFF / ARM_PAGE_DESC_ENTRY_MVA_SIZE + 1)\r
+\r
+\r
+// page table 1st level descriptor entries\r
+#define ARM_PAGE_DESC_BASE_MASK 0xFFFFFC00\r
+#define ARM_PAGE_DESC_BASE_SHFIT 10\r
+#define ARM_PAGE_DESC_DOMAIN_MASK 0x000001E0\r
+#define ARM_PAGE_DESC_DOMAIN_SHIFT 5\r
+#define ARM_PAGE_DESC_NS 0x00000008\r
+\r
+#define ARM_FIRST_LEVEL_DESC_ALIGN 0x00004000 // 16KB\r
+\r
+// section 1st level desriptor entries\r
+#define ARM_SECTION_BASE_MASK 0xFFF00000\r
+#define ARM_SECTION_BASE_SHIFT 20\r
+#define ARM_SECTION_NS 0x00080000\r
+#define ARM_SECTION_nG 0x00020000\r
+#define ARM_SECTION_S 0x00010000\r
+#define ARM_SECTION_AP2 0x00008000\r
+#define ARM_SECTION_TEX_MASK 0x00007000\r
+#define ARM_SECTION_TEX_SHIFT 12\r
+#define ARM_SECTION_AP10_MASK 0x00000C00\r
+#define ARM_SECTION_AP10_SHIFT 10\r
+#define ARM_SECTION_DOMAIN_MASK 0x000001E0\r
+#define ARM_SECTION_DOMAIN_SHIFT 5\r
+#define ARM_SECTION_XN 0x00000010\r
+#define ARM_SECTION_C 0x00000008\r
+#define ARM_SECTION_B 0x00000004\r
+\r
+// section level AP[2:0] definitions\r
+#define ARM_SECTION_AP_NO_ACCESS 0 // AP[2:0] = 0\r
+#define ARM_SECTION_AP_READ_WRITE ARM_SECTION_AP10_MASK // AP[2:0] = 011\r
+#define ARM_SECTION_AP_READ_ONLY (ARM_SECTION_AP2 | ARM_SECTION_AP10_MASK) // AP[2:0] = 111\r
+\r
+// common 1st level descriptor fields\r
+#define ARM_DESC_TYPE_MASK 0x00000003\r
+\r
+// descriptor type values\r
+#define ARM_DESC_TYPE_FAULT 0x0\r
+#define ARM_DESC_TYPE_PAGE_TABLE 0x1\r
+#define ARM_DESC_TYPE_SECTION 0x2\r
+\r
+\r
+// Second Level Descriptors\r
+typedef UINT32 ARM_PAGE_TABLE_ENTRY;\r
+\r
+// small page 2nd level descriptor entries\r
+#define ARM_SMALL_PAGE_BASE_MASK 0xFFFFF000\r
+#define ARM_SMALL_PAGE_INDEX_MASK 0x000FF000\r
+#define ARM_SMALL_PAGE_BASE_SHIFT 12\r
+#define ARM_SMALL_PAGE_TEX_MASK 0x000001C0\r
+#define ARM_SMALL_PAGE_TEX_SHIFT 6\r
+#define ARM_SMALL_PAGE_XN 0x00000001\r
+\r
+// large page 2nd level descriptor entries\r
+#define ARM_LARGE_PAGE_BASE_MASK 0xFFFF0000\r
+#define ARM_LARGE_PAGE_BASE_SHIFT 16\r
+#define ARM_LARGE_PAGE_TEX_MASK 0x00007000\r
+#define ARM_LARGE_PAGE_TEX_SHIFT 12\r
+#define ARM_LARGE_PAGE_XN 0x00008000\r
+\r
+// common 2nd level desriptor fields\r
+#define ARM_PAGE_nG 0x00000800\r
+#define ARM_PAGE_S 0x00000400\r
+#define ARM_PAGE_AP2 0x00000200\r
+#define ARM_PAGE_AP10_MASK 0x00000030\r
+#define ARM_PAGE_AP10_SHIFT 4\r
+#define ARM_PAGE_C 0x00000008\r
+#define ARM_PAGE_B 0x00000004\r
+#define ARM_PAGE_DESC_TYPE_MASK 0x00000003\r
+\r
+// descriptor type values\r
+#define ARM_PAGE_TYPE_FAULT 0x0\r
+#define ARM_PAGE_TYPE_LARGE 0x1\r
+#define ARM_PAGE_TYPE_SMALL 0x2\r
+#define ARM_PAGE_TYPE_SMALL_XN 0x3\r
+\r
+#define SMALL_PAGE_TABLE_ENTRY_COUNT (ARM_PAGE_DESC_ENTRY_MVA_SIZE / EFI_PAGE_SIZE)\r
+\r
+\r
+// Translation Table Base 0 fields\r
+#define ARM_TTBR0_BASE_MASK 0xFFFFC000\r
+#define ARM_TTBR0_BASE_SHIFT 14\r
+#define ARM_TTRB0_NOS 0x00000020\r
+\r
+// define the combination of interesting attributes: cacheability and access permissions\r
+#define ARM_SECTION_CACHEABILITY_MASK ( ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B )\r
+#define ARM_SECTION_RW_PERMISSIONS_MASK ( ARM_SECTION_AP2 | ARM_SECTION_AP10_MASK )\r
+#define ARM_DESCRIPTOR_ATTRIBUTES ( ARM_SECTION_CACHEABILITY_MASK | ARM_SECTION_RW_PERMISSIONS_MASK | ARM_SECTION_XN )\r
+\r
+// cacheability values for section entries\r
+#define ARM_SECTION_STRONGLY_ORDERED 0\r
+#define ARM_SECTION_SHAREABLE_DEVICE ARM_SECTION_B\r
+#define ARM_SECTION_WRITE_THROUGH ARM_SECTION_C\r
+#define ARM_SECTION_WRITE_BACK_NWA ( ARM_SECTION_C| ARM_SECTION_B )\r
+#define ARM_SECTION_NORMAL_UNCACHEABLE ( 0x1 << ARM_SECTION_TEX_SHIFT )\r
+#define ARM_SECTION_WRITE_BACK ( ( 0x1 << ARM_SECTION_TEX_SHIFT ) | ARM_SECTION_C | ARM_SECTION_B )\r
+#define ARM_SECTION_NONSHAREABLE_DEVICE ( 0x2 << ARM_SECTION_TEX_SHIFT )\r
+\r
+// permissions values for section entries\r
+#define ARM_SECTION_NO_ACCESS 0\r
+#define ARM_SECTION_PRIV_ACCESS_ONLY ( 0x1 << ARM_SECTION_AP10_SHIFT)\r
+#define ARM_SECTION_USER_READ_ONLY ( 0x2 << ARM_SECTION_AP10_SHIFT)\r
+#define ARM_SECTION_FULL_ACCESS ( 0x3 << ARM_SECTION_AP10_SHIFT)\r
+#define ARM_SECTION_PRIV_READ_ONLY ( ARM_SECTION_AP2 | (0x1 << ARM_SECTION_AP10_SHIFT) )\r
+#define ARM_SECTION_READ_ONLY_DEP ( ARM_SECTION_AP2 | (0x2 << ARM_SECTION_AP10_SHIFT) )\r
+#define ARM_SECTION_READ_ONLY ( ARM_SECTION_AP2 | (0x3 << ARM_SECTION_AP10_SHIFT) )\r
+\r
+\r
+\r
+EFI_STATUS \r
+SectionToGcdAttributes (\r
+ IN UINT32 SectionAttributes,\r
+ OUT UINT64 *GcdAttributes\r
+ )\r
+{\r
+ *GcdAttributes = 0;\r
+\r
+ // determine cacheability attributes\r
+ switch(SectionAttributes & ARM_SECTION_CACHEABILITY_MASK) {\r
+ case ARM_SECTION_STRONGLY_ORDERED:\r
+ *GcdAttributes |= EFI_MEMORY_UC;\r
+ break;\r
+ case ARM_SECTION_SHAREABLE_DEVICE:\r
+ *GcdAttributes |= EFI_MEMORY_UC;\r
+ break;\r
+ case ARM_SECTION_WRITE_THROUGH:\r
+ *GcdAttributes |= EFI_MEMORY_WT;\r
+ break;\r
+ case ARM_SECTION_WRITE_BACK_NWA:\r
+ *GcdAttributes |= EFI_MEMORY_WB;\r
+ break;\r
+ case ARM_SECTION_NORMAL_UNCACHEABLE:\r
+ *GcdAttributes |= EFI_MEMORY_WC;\r
+ break;\r
+ case ARM_SECTION_WRITE_BACK:\r
+ *GcdAttributes |= EFI_MEMORY_WB;\r
+ break;\r
+ case ARM_SECTION_NONSHAREABLE_DEVICE:\r
+ *GcdAttributes |= EFI_MEMORY_UC;\r
+ break;\r
+ default:\r
+ return EFI_UNSUPPORTED;\r
+ break;\r
+ }\r
+ \r
+ // determine protection attributes\r
+ switch(SectionAttributes & ARM_SECTION_RW_PERMISSIONS_MASK) {\r
+ case ARM_SECTION_NO_ACCESS: // no read, no write\r
+ *GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;\r
+ break;\r
+\r
+ case ARM_SECTION_PRIV_ACCESS_ONLY:\r
+ case ARM_SECTION_FULL_ACCESS:\r
+ // normal read/write access, do not add additional attributes\r
+ break;\r
+\r
+ // read only cases map to write-protect\r
+ case ARM_SECTION_PRIV_READ_ONLY:\r
+ case ARM_SECTION_READ_ONLY_DEP:\r
+ case ARM_SECTION_READ_ONLY:\r
+ *GcdAttributes |= EFI_MEMORY_WP;\r
+ break;\r
+\r
+ default:\r
+ return EFI_UNSUPPORTED;\r
+ break;\r
+ }\r
+\r
+ // now process eXectue Never attribute\r
+ if ((SectionAttributes & ARM_SECTION_XN) != 0 ) {\r
+ *GcdAttributes |= EFI_MEMORY_XP;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+\r
+EFI_STATUS\r
+SyncCacheConfig (\r
+ IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINT32 i;\r
+ UINT32 Descriptor;\r
+ UINT32 SectionAttributes;\r
+ EFI_PHYSICAL_ADDRESS NextRegionBase;\r
+ UINT64 NextRegionLength;\r
+ UINT64 GcdAttributes;\r
+ UINT32 NextRegionAttributes = 0;\r
+ volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
+\r
+\r
+ // This code assumes MMU is enabled and filed with section translations\r
+ ASSERT (ArmMmuEnabled ());\r
+\r
+\r
+ // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs\r
+ // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a\r
+ // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were\r
+ // a client) to update its copy of the attributes. This is bad architecture and should be replaced\r
+ // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.\r
+\r
+ // obtain page table base\r
+ FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTranslationTableBaseAddress ());\r
+\r
+\r
+ // iterate through each 1MB descriptor\r
+ NextRegionBase = NextRegionLength = 0;\r
+ for (i=0; i< FIRST_LEVEL_ENTRY_COUNT; i++) {\r
+\r
+ // obtain existing descriptor\r
+ Descriptor = FirstLevelTable[i];\r
+\r
+ // extract attributes (cacheability and permissions)\r
+ SectionAttributes = Descriptor & 0xDEC;\r
+\r
+ // do we already have an existing region (or are we about to finish)?\r
+ // Skip the first entry, and make sure we close on the last entry\r
+ if ( (NextRegionLength > 0) || (i == (FIRST_LEVEL_ENTRY_COUNT-1)) ) {\r
+ // attributes are changing, update attributes in GCD\r
+ if (SectionAttributes != NextRegionAttributes) {\r
+ \r
+ // convert section entry attributes to GCD bitmask\r
+ Status = SectionToGcdAttributes (NextRegionAttributes, &GcdAttributes);\r
+ ASSERT_EFI_ERROR(Status);\r
+\r
+ // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
+ Status = gDS->SetMemorySpaceAttributes (NextRegionBase, NextRegionLength, GcdAttributes);\r
+ ASSERT_EFI_ERROR(Status);\r
+\r
+ // start on a new region\r
+ NextRegionLength = 0;\r
+ NextRegionBase = Descriptor & ARM_SECTION_BASE_MASK;\r
+ }\r
+ }\r
+\r
+ // starting a new region?\r
+ if (NextRegionLength == 0) {\r
+ NextRegionAttributes = SectionAttributes;\r
+ }\r
+\r
+ NextRegionLength += ARM_PAGE_DESC_ENTRY_MVA_SIZE;\r
+\r
+ } // section entry loop\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+\r
+EFI_STATUS\r
+UpdatePageEntries (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes,\r
+ IN EFI_PHYSICAL_ADDRESS VirtualMask\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINT32 EntryValue;\r
+ UINT32 EntryMask;\r
+ UINT32 FirstLevelIdx;\r
+ UINT32 Offset;\r
+ UINT32 NumPageEntries;\r
+ UINT32 Descriptor;\r
+ UINT32 p;\r
+ UINT32 PageTableIndex;\r
+ UINT32 PageTableEntry;\r
+\r
+ volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
+ volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r
+\r
+ // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
+ // EntryValue: values at bit positions specified by EntryMask\r
+\r
+ // Although the PI spec is unclear on this the GCD guarantees that only\r
+ // one Attribute bit is set at a time, so we can safely use a switch statement\r
+ switch (Attributes) {\r
+ case EFI_MEMORY_UC:\r
+ // modify cacheability attributes\r
+ EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+ // map to strongly ordered\r
+ EntryValue = 0; // TEX[2:0] = 0, C=0, B=0\r
+ break;\r
+\r
+ case EFI_MEMORY_WC:\r
+ // modify cacheability attributes\r
+ EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+ // map to normal non-cachable\r
+ EntryValue = (0x1 << ARM_SMALL_PAGE_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
+ break;\r
+\r
+ case EFI_MEMORY_WT:\r
+ // modify cacheability attributes\r
+ EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+ // write through with no-allocate\r
+ EntryValue = ARM_PAGE_C; // TEX [2:0] = 0, C=1, B=0\r
+ break;\r
+\r
+ case EFI_MEMORY_WB:\r
+ // modify cacheability attributes\r
+ EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+ // write back (with allocate)\r
+ EntryValue = (0x1 << ARM_SMALL_PAGE_TEX_SHIFT) | ARM_PAGE_C | ARM_PAGE_B; // TEX [2:0] = 001, C=1, B=1\r
+ break;\r
+\r
+ case EFI_MEMORY_WP:\r
+ case EFI_MEMORY_XP:\r
+ case EFI_MEMORY_UCE:\r
+ // cannot be implemented UEFI definition unclear for ARM\r
+ // Cause a page fault if these ranges are accessed.\r
+ EntryMask = 0x3;\r
+ EntryValue = 0;\r
+ DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
+ break;\r
+\r
+ default:\r
+ return EFI_UNSUPPORTED;\r
+ break;\r
+ }\r
+\r
+ // obtain page table base\r
+ FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r
+\r
+ // calculate number of 4KB page table entries to change\r
+ NumPageEntries = Length/EFI_PAGE_SIZE;\r
+ \r
+ // iterate for the number of 4KB pages to change\r
+ Offset = 0;\r
+ for(p=0; p<NumPageEntries; p++) {\r
+ // calculate index into first level translation table for page table value\r
+ \r
+ FirstLevelIdx = ((BaseAddress + Offset) & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;\r
+ ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);\r
+\r
+ // read the descriptor from the first level page table\r
+ Descriptor = FirstLevelTable[FirstLevelIdx];\r
+\r
+ // does this descriptor need to be converted from section entry to 4K pages?\r
+ if ((Descriptor & ARM_DESC_TYPE_MASK) == ARM_DESC_TYPE_SECTION ) {\r
+ Status = ConvertSectionToPages (FirstLevelIdx << ARM_SECTION_BASE_SHIFT);\r
+ if (EFI_ERROR(Status)) {\r
+ // exit for loop\r
+ break; \r
+ } \r
+ \r
+ // re-read descriptor\r
+ Descriptor = FirstLevelTable[FirstLevelIdx];\r
+ }\r
+\r
+ // obtain page table base address\r
+ PageTable = (ARM_PAGE_TABLE_ENTRY *)(Descriptor & ARM_SMALL_PAGE_BASE_MASK);\r
+\r
+ // calculate index into the page table\r
+ PageTableIndex = ((BaseAddress + Offset) & ARM_SMALL_PAGE_INDEX_MASK) >> ARM_SMALL_PAGE_BASE_SHIFT;\r
+ ASSERT(PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);\r
+\r
+ // get the entry\r
+ PageTableEntry = PageTable[PageTableIndex];\r
+\r
+ // mask off appropriate fields\r
+ PageTableEntry &= ~EntryMask;\r
+\r
+ // mask in new attributes and/or permissions\r
+ PageTableEntry |= EntryValue;\r
+\r
+ if (VirtualMask != 0) {\r
+ // Make this virtual address point at a physical page\r
+ PageTableEntry &= ~VirtualMask;\r
+ }\r
+ \r
+ // update the entry\r
+ PageTable[PageTableIndex] = PageTableEntry; \r
+ \r
+\r
+ Status = EFI_SUCCESS;\r
+ Offset += EFI_PAGE_SIZE;\r
+ \r
+ } // end first level translation table loop\r
+\r
+ return Status;\r
+}\r
+\r
+\r
+\r
+EFI_STATUS\r
+UpdateSectionEntries (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes,\r
+ IN EFI_PHYSICAL_ADDRESS VirtualMask\r
+ )\r
+{\r
+ EFI_STATUS Status = EFI_SUCCESS;\r
+ UINT32 EntryMask;\r
+ UINT32 EntryValue;\r
+ UINT32 FirstLevelIdx;\r
+ UINT32 NumSections;\r
+ UINT32 i;\r
+ UINT32 Descriptor;\r
+\r
+ volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
+\r
+ // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
+ // EntryValue: values at bit positions specified by EntryMask\r
+\r
+ // Although the PI spec is unclear on this the GCD guarantees that only\r
+ // one Attribute bit is set at a time, so we can safely use a switch statement\r
+ switch(Attributes) {\r
+ case EFI_MEMORY_UC:\r
+ // modify cacheability attributes\r
+ EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+ // map to strongly ordered\r
+ EntryValue = 0; // TEX[2:0] = 0, C=0, B=0\r
+ break;\r
+\r
+ case EFI_MEMORY_WC:\r
+ // modify cacheability attributes\r
+ EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+ // map to normal non-cachable\r
+ EntryValue = (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
+ break;\r
+\r
+ case EFI_MEMORY_WT:\r
+ // modify cacheability attributes\r
+ EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+ // write through with no-allocate\r
+ EntryValue = ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0\r
+ break;\r
+\r
+ case EFI_MEMORY_WB:\r
+ // modify cacheability attributes\r
+ EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+ // write back (with allocate)\r
+ EntryValue = (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1\r
+ break;\r
+\r
+ case EFI_MEMORY_WP:\r
+ case EFI_MEMORY_XP:\r
+ case EFI_MEMORY_RP:\r
+ case EFI_MEMORY_UCE:\r
+ // cannot be implemented UEFI definition unclear for ARM\r
+ // Cause a page fault if these ranges are accessed.\r
+ EntryMask = 0x3;\r
+ EntryValue = 0;\r
+ DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
+ break;\r
+\r
+\r
+ default:\r
+ return EFI_UNSUPPORTED;\r
+ break;\r
+ }\r
+\r
+ // obtain page table base\r
+ FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r
+\r
+ // calculate index into first level translation table for start of modification\r
+ FirstLevelIdx = (BaseAddress & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;\r
+ ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);\r
+\r
+ // calculate number of 1MB first level entries this applies to\r
+ NumSections = Length / ARM_PAGE_DESC_ENTRY_MVA_SIZE;\r
+ \r
+ // iterate through each descriptor\r
+ for(i=0; i<NumSections; i++) {\r
+ Descriptor = FirstLevelTable[FirstLevelIdx + i];\r
+\r
+ // has this descriptor already been coverted to pages?\r
+ if ((Descriptor & ARM_DESC_TYPE_MASK) == ARM_DESC_TYPE_PAGE_TABLE ) {\r
+ // forward this 1MB range to page table function instead\r
+ Status = UpdatePageEntries ((FirstLevelIdx + i) << ARM_SECTION_BASE_SHIFT, ARM_PAGE_DESC_ENTRY_MVA_SIZE, Attributes, VirtualMask);\r
+ } else {\r
+ // still a section entry\r
+ \r
+ // mask off appropriate fields\r
+ Descriptor &= ~EntryMask;\r
+\r
+ // mask in new attributes and/or permissions\r
+ Descriptor |= EntryValue;\r
+ if (VirtualMask != 0) {\r
+ Descriptor &= ~VirtualMask;\r
+ }\r
+\r
+ FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r
+\r
+ Status = EFI_SUCCESS;\r
+ }\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS \r
+ConvertSectionToPages (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS PageTableAddr;\r
+ UINT32 FirstLevelIdx;\r
+ UINT32 SectionDescriptor;\r
+ UINT32 PageTableDescriptor;\r
+ UINT32 PageDescriptor;\r
+ UINT32 i;\r
+\r
+ volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
+ volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r
+\r
+ DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));\r
+\r
+ // obtain page table base\r
+ FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r
+\r
+ // calculate index into first level translation table for start of modification\r
+ FirstLevelIdx = (BaseAddress & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;\r
+ ASSERT(FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);\r
+\r
+ // get section attributes and convert to page attributes\r
+ SectionDescriptor = FirstLevelTable[FirstLevelIdx];\r
+ PageDescriptor = ARM_PAGE_TYPE_SMALL;\r
+ PageDescriptor |= ((SectionDescriptor & ARM_SECTION_TEX_MASK) >> ARM_SECTION_TEX_SHIFT) << ARM_SMALL_PAGE_TEX_SHIFT;\r
+ if ((SectionDescriptor & ARM_SECTION_B) != 0) {\r
+ PageDescriptor |= ARM_PAGE_B;\r
+ }\r
+ if ((SectionDescriptor & ARM_SECTION_C) != 0) {\r
+ PageDescriptor |= ARM_PAGE_C;\r
+ }\r
+ PageDescriptor |= ((SectionDescriptor & ARM_SECTION_AP10_MASK) >> ARM_SECTION_AP10_SHIFT) << ARM_PAGE_AP10_SHIFT;\r
+ if ((SectionDescriptor & ARM_SECTION_AP2) != 0) {\r
+ PageDescriptor |= ARM_PAGE_AP2;\r
+ }\r
+ if ((SectionDescriptor & ARM_SECTION_XN) != 0) {\r
+ PageDescriptor |= ARM_PAGE_TYPE_SMALL_XN;\r
+ }\r
+ if ((SectionDescriptor & ARM_SECTION_nG) != 0) {\r
+ PageDescriptor |= ARM_PAGE_nG;\r
+ }\r
+ if ((SectionDescriptor & ARM_SECTION_S) != 0) {\r
+ PageDescriptor |= ARM_PAGE_S;\r
+ }\r
+\r
+ // allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)\r
+ Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, 1, &PageTableAddr);\r
+ if (EFI_ERROR(Status)) {\r
+ return Status;\r
+ }\r
+\r
+ PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;\r
+\r
+ // write the page table entries out\r
+ for (i=0; i<(ARM_PAGE_DESC_ENTRY_MVA_SIZE/EFI_PAGE_SIZE); i++) {\r
+ PageTable[i] = ((BaseAddress + (i << 12)) & ARM_SMALL_PAGE_BASE_MASK) | PageDescriptor;\r
+ }\r
+\r
+ // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
+ // TODO: change to use only PageTable base and length\r
+ // ArmInvalidateDataCache ();\r
+ InvalidateDataCacheRange ((VOID *)&PageTableAddr, EFI_PAGE_SIZE);\r
+\r
+ // formulate page table entry, Domain=0, NS=0\r
+ PageTableDescriptor = (((UINTN)PageTableAddr) & ARM_PAGE_DESC_BASE_MASK) | ARM_DESC_TYPE_PAGE_TABLE;\r
+\r
+ // write the page table entry out, repalcing section entry\r
+ FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+\r
+EFI_STATUS\r
+SetMemoryAttributes (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes,\r
+ IN EFI_PHYSICAL_ADDRESS VirtualMask\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ \r
+ if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {\r
+ // is the base and length a multiple of 1 MB?\r
+ DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
+ Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);\r
+ } else {\r
+ // base and/or length is not a multiple of 1 MB\r
+ DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
+ Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);\r
+ }\r
+\r
+ // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
+ // flush and invalidate pages\r
+ ArmCleanInvalidateDataCache ();\r
+ \r
+ ArmInvalidateInstructionCache ();\r
+\r
+ // invalidate all TLB entries so changes are synced\r
+ ArmInvalidateTlb (); \r
+\r
+ return Status;\r
+}\r
+\r
+\r
+/**\r
+ This function modifies the attributes for the memory region specified by BaseAddress and\r
+ Length from their current attributes to the attributes specified by Attributes.\r
+\r
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.\r
+ @param BaseAddress The physical address that is the start address of a memory region.\r
+ @param Length The size in bytes of the memory region.\r
+ @param Attributes The bit mask of attributes to set for the memory region.\r
+\r
+ @retval EFI_SUCCESS The attributes were set for the memory region.\r
+ @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
+ BaseAddress and Length cannot be modified.\r
+ @retval EFI_INVALID_PARAMETER Length is zero.\r
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
+ the memory resource range.\r
+ @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
+ resource range specified by BaseAddress and Length.\r
+ The bit mask of attributes is not support for the memory resource\r
+ range specified by BaseAddress and Length.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+CpuSetMemoryAttributes (\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes\r
+ )\r
+{\r
+ if ( ((BaseAddress & (EFI_PAGE_SIZE-1)) != 0) || ((Length & (EFI_PAGE_SIZE-1)) != 0)){\r
+ // minimum granularity is EFI_PAGE_SIZE (4KB on ARM)\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ \r
+ return SetMemoryAttributes (BaseAddress, Length, Attributes, 0);\r
+}\r
+\r
+\r
+\r
+//\r
+// Add a new protocol to support \r
+//\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+CpuConvertPagesToUncachedVirtualAddress (\r
+ IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,\r
+ IN EFI_PHYSICAL_ADDRESS Address,\r
+ IN UINTN Length,\r
+ IN EFI_PHYSICAL_ADDRESS VirtualMask,\r
+ OUT UINT64 *Attributes OPTIONAL\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;\r
+ \r
+ \r
+ if (Attributes != NULL) {\r
+ Status = gDS->GetMemorySpaceDescriptor (Address, &GcdDescriptor);\r
+ if (!EFI_ERROR (Status)) {\r
+ *Attributes = GcdDescriptor.Attributes;\r
+ }\r
+ }\r
+ \r
+ //\r
+ // Make this address range page fault if accessed. If it is a DMA buffer than this would \r
+ // be the PCI address. Code should always use the CPU address, and we will or in VirtualMask\r
+ // to that address. \r
+ //\r
+ Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_XP, 0);\r
+ if (!EFI_ERROR (Status)) {\r
+ Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask);\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+CpuFreeConvertedPages (\r
+ IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,\r
+ IN EFI_PHYSICAL_ADDRESS Address,\r
+ IN UINTN Length,\r
+ IN EFI_PHYSICAL_ADDRESS VirtualMask,\r
+ IN UINT64 Attributes\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ \r
+ //\r
+ // Unmap the alaised Address\r
+ //\r
+ Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_XP, 0);\r
+ if (!EFI_ERROR (Status)) {\r
+ //\r
+ // Restore atttributes\r
+ //\r
+ Status = SetMemoryAttributes (Address, Length, Attributes, 0);\r
+ }\r
+ \r
+ return Status;\r
+}\r
+\r
+\r
+VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages = {\r
+ CpuConvertPagesToUncachedVirtualAddress,\r
+ CpuFreeConvertedPages\r
+};\r
+\r
+\r
+\r
+\r
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