IntelSiliconPkg/VtdPeiSample: Add premem support.

Before memory is ready, this sample produces one VTd engine.
After memory and silicon is initialized, this sample produces
both IGD VTd engine and all-rest VTd engine by reinstall the
FV_INFO_PPI.

This update is to demonstrate how to support pre-mem VTd usage.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>

diff --git a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
index 6267da72339802d73fa8600e7ac73c659c545356..852dc0e50096b26fa0dbcf8a6d6b1d1a27b8a1d9 100644 (file)
--- a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
+++ b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
@@ -20,6 +20,7 @@
 #include <Library/DebugLib.h>\r
 #include <Library/PciLib.h>\r
 #include <Library/IoLib.h>\r
 #include <Library/DebugLib.h>\r
 #include <Library/PciLib.h>\r
 #include <Library/IoLib.h>\r

+#include <Library/MemoryAllocationLib.h>\r

 \r
 #define R_SA_MCHBAR               (0x48)\r
 #define R_SA_GGC                  (0x50)\r
 \r
 #define R_SA_MCHBAR               (0x48)\r
 #define R_SA_GGC                  (0x50)\r


@@ -33,6 +34,8 @@
 #define R_SA_MCHBAR_VTD1_OFFSET  0x5400  ///< HW UNIT for IGD\r
 #define R_SA_MCHBAR_VTD2_OFFSET  0x5410  ///< HW UNIT for all other - PEG, USB, SATA etc\r
 \r
 #define R_SA_MCHBAR_VTD1_OFFSET  0x5400  ///< HW UNIT for IGD\r
 #define R_SA_MCHBAR_VTD2_OFFSET  0x5410  ///< HW UNIT for all other - PEG, USB, SATA etc\r
 \r

+EFI_GUID gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 0x5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}};\r
+\r

 typedef struct {\r
   EFI_ACPI_DMAR_HEADER                         DmarHeader;\r
   //\r
 typedef struct {\r
   EFI_ACPI_DMAR_HEADER                         DmarHeader;\r
   //\r


@@ -131,50 +134,188 @@ EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {
   &mPlatformVTdSample\r
 };\r
 \r
   &mPlatformVTdSample\r
 };\r
 \r

+typedef struct {\r
+  EFI_ACPI_DMAR_HEADER                         DmarHeader;\r
+  //\r
+  // VTd engine 2 - all rest\r
+  //\r
+  EFI_ACPI_DMAR_DRHD_HEADER                    Drhd2;\r
+} MY_VTD_INFO_NO_IGD_PPI;\r
+\r
+MY_VTD_INFO_NO_IGD_PPI  mPlatformVTdNoIgdSample = {\r
+  { // DmarHeader\r
+    { // Header\r
+      EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,\r
+      sizeof(MY_VTD_INFO_NO_IGD_PPI),\r
+      EFI_ACPI_DMAR_REVISION,\r
+    },\r
+    0x26, // HostAddressWidth\r
+  },\r
+\r
+  { // Drhd2\r
+    { // Header\r
+      EFI_ACPI_DMAR_TYPE_DRHD,\r
+      sizeof(EFI_ACPI_DMAR_DRHD_HEADER)\r
+    },\r
+    EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags\r
+    0, // Reserved\r
+    0, // SegmentNumber\r
+    0xFED91000 // RegisterBaseAddress -- TO BE PATCHED\r
+  },\r
+};\r
+\r
+EFI_PEI_PPI_DESCRIPTOR mPlatformVTdNoIgdInfoSampleDesc = {\r
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+  &gEdkiiVTdInfoPpiGuid,\r
+  &mPlatformVTdNoIgdSample\r
+};\r
+\r

 /**\r
 /**\r

-  Patch Graphic UMA address in RMRR and base address.\r
+  Initialize VTd register.\r

 **/\r
 VOID\r
 **/\r
 VOID\r

-PatchDmar (\r
+InitDmar (\r

   VOID\r
   )\r
 {\r
   UINT32              MchBar;\r
   VOID\r
   )\r
 {\r
   UINT32              MchBar;\r

-  UINT16              IgdMode;\r
-  UINT16              GttMode;\r
-  UINT32              IgdMemSize;\r
-  UINT32              GttMemSize;\r
-\r
-  ///\r
-  /// Calculate IGD memsize\r
-  ///\r
-  IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;\r
-  if (IgdMode < 0xF0) {\r
-    IgdMemSize = IgdMode * 32 * (1024) * (1024);\r
+\r
+  DEBUG ((DEBUG_INFO, "InitDmar\n"));\r
+\r
+  MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;\r
+  PciWrite32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR), 0xFED10000 | BIT0);\r
+  DEBUG ((DEBUG_INFO, "MchBar - %x\n", MchBar));\r
+\r
+  MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, (UINT32)mPlatformVTdSample.Drhd2.RegisterBaseAddress | 1);\r
+  DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET))));\r
+}\r
+\r
+/**\r
+  Patch Graphic UMA address in RMRR and base address.\r
+**/\r
+EFI_PEI_PPI_DESCRIPTOR *\r
+PatchDmar (\r
+  VOID\r
+  )\r
+{\r
+  UINT32                  MchBar;\r
+  UINT16                  IgdMode;\r
+  UINT16                  GttMode;\r
+  UINT32                  IgdMemSize;\r
+  UINT32                  GttMemSize;\r
+  MY_VTD_INFO_PPI         *PlatformVTdSample;\r
+  EFI_PEI_PPI_DESCRIPTOR  *PlatformVTdInfoSampleDesc;\r
+  MY_VTD_INFO_NO_IGD_PPI  *PlatformVTdNoIgdSample;\r
+  EFI_PEI_PPI_DESCRIPTOR  *PlatformVTdNoIgdInfoSampleDesc;\r
+\r
+  DEBUG ((DEBUG_INFO, "PatchDmar\n"));\r
+\r
+  if (PciRead16 (PCI_LIB_ADDRESS(0, 2, 0, 0)) != 0xFFFF) {\r
+    PlatformVTdSample = AllocateCopyPool (sizeof(MY_VTD_INFO_PPI), &mPlatformVTdSample);\r
+    ASSERT(PlatformVTdSample != NULL);\r
+    PlatformVTdInfoSampleDesc = AllocateCopyPool (sizeof(EFI_PEI_PPI_DESCRIPTOR), &mPlatformVTdInfoSampleDesc);\r
+    ASSERT(PlatformVTdInfoSampleDesc != NULL);\r
+    PlatformVTdInfoSampleDesc->Ppi = PlatformVTdSample;\r
+\r
+    ///\r
+    /// Calculate IGD memsize\r
+    ///\r
+    IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;\r
+    if (IgdMode < 0xF0) {\r
+      IgdMemSize = IgdMode * 32 * (1024) * (1024);\r
+    } else {\r
+      IgdMemSize = 4 * (IgdMode - 0xF0 + 1) * (1024) * (1024);\r
+    }\r
+\r
+    ///\r
+    /// Calculate GTT mem size\r
+    ///\r
+    GttMemSize = 0;\r
+    GttMode = (PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_SA_GGC_GGMS_MASK) >> N_SKL_SA_GGC_GGMS_OFFSET;\r
+    if (GttMode <= V_SKL_SA_GGC_GGMS_8MB) {\r
+      GttMemSize = (1 << GttMode) * (1024) * (1024);\r
+    }\r
+\r
+    PlatformVTdSample->Rmrr1.ReservedMemoryRegionBaseAddress  = (PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_TOLUD)) & ~(0x01)) - IgdMemSize - GttMemSize;\r
+    PlatformVTdSample->Rmrr1.ReservedMemoryRegionLimitAddress = PlatformVTdSample->Rmrr1.ReservedMemoryRegionBaseAddress + IgdMemSize + GttMemSize - 1;\r
+\r
+    ///\r
+    /// Update DRHD structures of DmarTable\r
+    ///\r
+    MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;\r
+\r
+    if ((MmioRead32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET) &~1) != 0) {\r
+      PlatformVTdSample->Drhd1.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET) &~1);\r
+    } else {\r
+      MmioWrite32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET, (UINT32)PlatformVTdSample->Drhd1.RegisterBaseAddress | 1);\r
+    }\r
+    DEBUG ((DEBUG_INFO, "VTd1 - %x\n", (MmioRead32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET))));\r
+\r
+    if ((MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1) != 0) {\r
+      PlatformVTdSample->Drhd2.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1);\r
+    } else {\r
+      MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, (UINT32)PlatformVTdSample->Drhd2.RegisterBaseAddress | 1);\r
+    }\r
+    DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET))));\r
+\r
+    return PlatformVTdInfoSampleDesc;\r

   } else {\r
   } else {\r

-    IgdMemSize = 4 * (IgdMode - 0xF0 + 1) * (1024) * (1024);\r
-  }\r
+    PlatformVTdNoIgdSample = AllocateCopyPool (sizeof(MY_VTD_INFO_NO_IGD_PPI), &mPlatformVTdNoIgdSample);\r
+    ASSERT(PlatformVTdNoIgdSample != NULL);\r
+    PlatformVTdNoIgdInfoSampleDesc = AllocateCopyPool (sizeof(EFI_PEI_PPI_DESCRIPTOR), &mPlatformVTdNoIgdInfoSampleDesc);\r
+    ASSERT(PlatformVTdNoIgdInfoSampleDesc != NULL);\r
+    PlatformVTdNoIgdInfoSampleDesc->Ppi = PlatformVTdNoIgdSample;\r
+\r
+    ///\r
+    /// Update DRHD structures of DmarTable\r
+    ///\r
+    MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;\r

 \r
 \r

-  ///\r
-  /// Calculate GTT mem size\r
-  ///\r
-  GttMemSize = 0;\r
-  GttMode = (PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_SA_GGC_GGMS_MASK) >> N_SKL_SA_GGC_GGMS_OFFSET;\r
-  if (GttMode <= V_SKL_SA_GGC_GGMS_8MB) {\r
-    GttMemSize = (1 << GttMode) * (1024) * (1024);\r
+    if ((MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1) != 0) {\r
+      PlatformVTdNoIgdSample->Drhd2.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1);\r
+    } else {\r
+      MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, (UINT32)PlatformVTdNoIgdSample->Drhd2.RegisterBaseAddress | 1);\r
+    }\r
+    DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET))));\r
+\r
+    return PlatformVTdNoIgdInfoSampleDesc;\r

   }\r
   }\r

+}\r

 \r
 \r

-  mPlatformVTdSample.Rmrr1.ReservedMemoryRegionBaseAddress  = (PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_TOLUD)) & ~(0x01)) - IgdMemSize - GttMemSize;\r
-  mPlatformVTdSample.Rmrr1.ReservedMemoryRegionLimitAddress = mPlatformVTdSample.Rmrr1.ReservedMemoryRegionBaseAddress + IgdMemSize + GttMemSize - 1;\r
+/**\r
+  The callback function for SiliconInitializedPpi.\r
+  It reinstalls VTD_INFO_PPI.\r

 \r
 \r

-  ///\r
-  /// Update DRHD structures of DmarTable\r
-  ///\r
-  MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;\r
-  mPlatformVTdSample.Drhd1.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET) &~1);\r
-  mPlatformVTdSample.Drhd2.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1);\r
+  @param[in]  PeiServices       General purpose services available to every PEIM.\r
+  @param[in]  NotifyDescriptor  Notify that this module published.\r
+  @param[in]  Ppi               PPI that was installed.\r
+\r
+  @retval     EFI_SUCCESS       The function completed successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SiliconInitializedPpiNotifyCallback (\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
+  IN VOID                       *Ppi\r
+  )\r
+{\r
+  EFI_STATUS               Status;\r
+  EFI_PEI_PPI_DESCRIPTOR   *PpiDesc;\r
+\r
+  PpiDesc = PatchDmar ();\r
+\r
+  Status = PeiServicesReInstallPpi (&mPlatformVTdNoIgdInfoSampleDesc, PpiDesc);\r
+  ASSERT_EFI_ERROR (Status);\r
+  return EFI_SUCCESS;\r

 }\r
 \r
 }\r
 \r

+EFI_PEI_NOTIFY_DESCRIPTOR mSiliconInitializedNotifyList = {\r
+  (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+  &gEdkiiSiliconInitializedPpiGuid,\r
+  (EFI_PEIM_NOTIFY_ENTRY_POINT) SiliconInitializedPpiNotifyCallback\r
+};\r
+\r

 /**\r
   Platform VTd Info sample driver.\r
 \r
 /**\r
   Platform VTd Info sample driver.\r
 \r


@@ -190,12 +331,37 @@ PlatformVTdInfoSampleInitialize (
   IN CONST EFI_PEI_SERVICES     **PeiServices\r
   )\r
 {\r
   IN CONST EFI_PEI_SERVICES     **PeiServices\r
   )\r
 {\r

-  EFI_STATUS  Status;\r
+  EFI_STATUS               Status;\r
+  BOOLEAN                  SiliconInitialized;\r
+  VOID                     *SiliconInitializedPpi;\r
+  EFI_PEI_PPI_DESCRIPTOR   *PpiDesc;\r
+\r
+  SiliconInitialized = FALSE;\r
+  //\r
+  // Check if silicon is initialized.\r
+  //\r
+  Status = PeiServicesLocatePpi (\r
+             &gEdkiiSiliconInitializedPpiGuid,\r
+             0,\r
+             NULL,\r
+             &SiliconInitializedPpi\r
+             );\r
+  if (!EFI_ERROR(Status)) {\r
+    SiliconInitialized = TRUE;\r
+  }\r
+  DEBUG ((DEBUG_INFO, "SiliconInitialized - %x\n", SiliconInitialized));\r
+  if (!SiliconInitialized) {\r
+    Status = PeiServicesNotifyPpi (&mSiliconInitializedNotifyList);\r
+    InitDmar ();\r

 \r
 \r

-  PatchDmar ();\r
+    Status = PeiServicesInstallPpi (&mPlatformVTdNoIgdInfoSampleDesc);\r
+    ASSERT_EFI_ERROR (Status);\r
+  } else {\r
+    PpiDesc = PatchDmar ();\r

 \r
 \r

-  Status = PeiServicesInstallPpi (&mPlatformVTdInfoSampleDesc);\r
-  ASSERT_EFI_ERROR (Status);\r
+    Status = PeiServicesInstallPpi (PpiDesc);\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r

 \r
   return Status;\r
 }\r
 \r
   return Status;\r
 }\r

diff --git a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
index 96adb70edca071828558825a40e8e1fe79e709ea..a4ffe51e2f3d23e770927321d962c2c842946b62 100644 (file)
--- a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
+++ b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
@@ -47,7 +47,7 @@
   gEdkiiVTdInfoPpiGuid         ## PRODUCES\r
 \r
 [Depex]\r
   gEdkiiVTdInfoPpiGuid         ## PRODUCES\r
 \r
 [Depex]\r

-  gEfiPeiMemoryDiscoveredPpiGuid\r
+  gEfiPeiMasterBootModePpiGuid\r

 \r
 [UserExtensions.TianoCore."ExtraFiles"]\r
   PlatformVTdInfoSamplePeiExtra.uni\r
 \r
 [UserExtensions.TianoCore."ExtraFiles"]\r
   PlatformVTdInfoSamplePeiExtra.uni\r