This change is purely cosmetic, to tidy some code before change.
Mods involve:
Re-order #includes
Reformat comments.
Use ns consistently (always "100ns" not sometimes "100 nS")
Split overlength code lines.
Make protocol functions STATIC.
Remove "Horor vacui" comments.
Rationalize GIC register address calculations
Replace explicit test and assert with ASSERT_EFI_ERROR.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
/*++\r
\r
-Copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>\r
+Copyright (c) 2013-2017, ARM Ltd. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
IN VOID *Context\r
);\r
\r
-//\r
// Making this global saves a few bytes in image size\r
-//\r
EFI_HANDLE gHardwareInterruptHandle = NULL;\r
\r
-//\r
// Notifications\r
-//\r
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;\r
\r
// Maximum Number of Interrupts\r
{\r
EFI_STATUS Status;\r
EFI_CPU_ARCH_PROTOCOL *Cpu;\r
+ CONST UINTN RihArraySize =\r
+ (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);\r
\r
// Initialize the array for the Interrupt Handlers\r
- gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);\r
+ gRegisteredInterruptHandlers = AllocateZeroPool (RihArraySize);\r
if (gRegisteredInterruptHandlers == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&gHardwareInterruptHandle,\r
- &gHardwareInterruptProtocolGuid, InterruptProtocol,\r
+ &gHardwareInterruptProtocolGuid,\r
+ InterruptProtocol,\r
NULL\r
);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
- //\r
// Get the CPU protocol that this driver requires.\r
- //\r
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
- //\r
// Unregister the default exception handler.\r
- //\r
Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
- //\r
// Register to receive interrupts\r
- //\r
- Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, InterruptHandler);\r
+ Status = Cpu->RegisterInterruptHandler (\r
+ Cpu,\r
+ ARM_ARCH_EXCEPTION_IRQ,\r
+ InterruptHandler\r
+ );\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
// Register for an ExitBootServicesEvent\r
- Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);\r
+ Status = gBS->CreateEvent (\r
+ EVT_SIGNAL_EXIT_BOOT_SERVICES,\r
+ TPL_NOTIFY,\r
+ ExitBootServicesEvent,\r
+ NULL,\r
+ &EfiExitBootServicesEvent\r
+ );\r
\r
return Status;\r
}\r
/*++\r
\r
-Copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>\r
+Copyright (c) 2013-2017, ARM Ltd. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
extern UINTN mGicNumInterrupts;\r
extern HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers;\r
\r
-//\r
// Common API\r
-//\r
EFI_STATUS\r
InstallAndRegisterInterruptService (\r
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol,\r
IN HARDWARE_INTERRUPT_HANDLER Handler\r
);\r
\r
-//\r
// GicV2 API\r
-//\r
EFI_STATUS\r
GicV2DxeInitialize (\r
IN EFI_HANDLE ImageHandle,\r
IN EFI_SYSTEM_TABLE *SystemTable\r
);\r
\r
-//\r
// GicV3 API\r
-//\r
EFI_STATUS\r
GicV3DxeInitialize (\r
IN EFI_HANDLE ImageHandle,\r
/** @file\r
*\r
-* Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
#include <Library/IoLib.h>\r
#include <Library/PcdLib.h>\r
\r
+\r
+#define ISENABLER_ADDRESS(base,offset) ((base) + \\r
+ ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * offset))\r
+\r
+#define ICENABLER_ADDRESS(base,offset) ((base) + \\r
+ ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + (4 * offset))\r
+\r
/**\r
*\r
* Return whether the Source interrupt index refers to a shared interrupt (SPI)\r
UINTN GicCpuRedistributorBase;\r
\r
MpId = ArmReadMpidr ();\r
- // Define CPU affinity as Affinity0[0:8], Affinity1[9:15], Affinity2[16:23], Affinity3[24:32]\r
+ // Define CPU affinity as:\r
+ // Affinity0[0:8], Affinity1[9:15], Affinity2[16:23], Affinity3[24:32]\r
// whereas Affinity3 is defined at [32:39] in MPIDR\r
- CpuAffinity = (MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2)) | ((MpId & ARM_CORE_AFF3) >> 8);\r
+ CpuAffinity = (MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2)) |\r
+ ((MpId & ARM_CORE_AFF3) >> 8);\r
\r
if (Revision == ARM_GIC_ARCH_REVISION_3) {\r
- // 2 x 64KB frame: Redistributor control frame + SGI Control & Generation frame\r
- GicRedistributorGranularity = ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_SGI_PPI_FRAME_SIZE;\r
+ // 2 x 64KB frame:\r
+ // Redistributor control frame + SGI Control & Generation frame\r
+ GicRedistributorGranularity = ARM_GICR_CTLR_FRAME_SIZE\r
+ + ARM_GICR_SGI_PPI_FRAME_SIZE;\r
} else {\r
ASSERT_EFI_ERROR (EFI_UNSUPPORTED);\r
return 0;\r
IN INTN SgiId\r
)\r
{\r
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);\r
+ MmioWrite32 (\r
+ GicDistributorBase + ARM_GIC_ICDSGIR,\r
+ ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId\r
+ );\r
}\r
\r
/*\r
* in the GICv3 the register value is only the InterruptId.\r
*\r
* @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface\r
- * @param InterruptId InterruptId read from the Interrupt Acknowledge Register\r
+ * @param InterruptId InterruptId read from the Interrupt\r
+ * Acknowledge Register\r
*\r
* @retval value returned by the Interrupt Acknowledge Register\r
*\r
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
SourceIsSpi (Source)) {\r
// Write set-enable register\r
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);\r
+ MmioWrite32 (\r
+ GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset),\r
+ 1 << RegShift\r
+ );\r
} else {\r
- GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);\r
+ GicCpuRedistributorBase = GicGetCpuRedistributorBase (\r
+ GicRedistributorBase,\r
+ Revision\r
+ );\r
if (GicCpuRedistributorBase == 0) {\r
ASSERT_EFI_ERROR (EFI_NOT_FOUND);\r
return;\r
}\r
\r
// Write set-enable register\r
- MmioWrite32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * RegOffset), 1 << RegShift);\r
+ MmioWrite32 (\r
+ ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),\r
+ 1 << RegShift\r
+ );\r
}\r
}\r
\r
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
SourceIsSpi (Source)) {\r
// Write clear-enable register\r
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);\r
+ MmioWrite32 (\r
+ GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset),\r
+ 1 << RegShift\r
+ );\r
} else {\r
- GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);\r
+ GicCpuRedistributorBase = GicGetCpuRedistributorBase (\r
+ GicRedistributorBase,\r
+ Revision\r
+ );\r
if (GicCpuRedistributorBase == 0) {\r
return;\r
}\r
\r
// Write clear-enable register\r
- MmioWrite32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + (4 * RegOffset), 1 << RegShift);\r
+ MmioWrite32 (\r
+ ICENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),\r
+ 1 << RegShift\r
+ );\r
}\r
}\r
\r
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||\r
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
SourceIsSpi (Source)) {\r
- Interrupts = ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);\r
+ Interrupts = ((MmioRead32 (\r
+ GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)\r
+ )\r
+ & (1 << RegShift)) != 0);\r
} else {\r
- GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);\r
+ GicCpuRedistributorBase = GicGetCpuRedistributorBase (\r
+ GicRedistributorBase,\r
+ Revision\r
+ );\r
if (GicCpuRedistributorBase == 0) {\r
return 0;\r
}\r
\r
// Read set-enable register\r
- Interrupts = MmioRead32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * RegOffset));\r
+ Interrupts = MmioRead32 (\r
+ ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset)\r
+ );\r
}\r
\r
return ((Interrupts & (1 << RegShift)) != 0);\r
\r
Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r
Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r
-Portions copyright (c) 2011-2016, ARM Ltd. All rights reserved.<BR>\r
+Portions copyright (c) 2011-2017, ARM Ltd. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
@retval EFI_UNSUPPORTED Source interrupt is not supported\r
\r
**/\r
+STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV2EnableInterruptSource (\r
@retval EFI_UNSUPPORTED Source interrupt is not supported\r
\r
**/\r
+STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV2DisableInterruptSource (\r
@retval EFI_UNSUPPORTED Source interrupt is not supported\r
\r
**/\r
+STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV2GetInterruptSourceState (\r
@retval EFI_UNSUPPORTED Source interrupt is not supported\r
\r
**/\r
+STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV2EndOfInterrupt (\r
EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r
\r
@param InterruptType Defines the type of interrupt or exception that\r
- occurred on the processor.This parameter is processor architecture specific.\r
+ occurred on the processor.This parameter is\r
+ processor architecture specific.\r
@param SystemContext A pointer to the processor context when\r
the interrupt occurred on the processor.\r
\r
@return None\r
\r
**/\r
+STATIC\r
VOID\r
EFIAPI\r
GicV2IrqInterruptHandler (\r
\r
GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);\r
\r
- // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).\r
+ // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the\r
+ // number of interrupt (ie: Spurious interrupt).\r
if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {\r
- // The special interrupt do not need to be acknowledge\r
+ // The special interrupts do not need to be acknowledged\r
return;\r
}\r
\r
// Call the registered interrupt handler.\r
InterruptHandler (GicInterrupt, SystemContext);\r
} else {\r
- DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));\r
+ DEBUG ((DEBUG_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));\r
GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);\r
}\r
}\r
\r
-//\r
// The protocol instance produced by this driver\r
-//\r
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {\r
RegisterInterruptSource,\r
GicV2EnableInterruptSource,\r
/**\r
Shutdown our hardware\r
\r
- DXE Core will disable interrupts and turn off the timer and disable interrupts\r
- after all the event handlers have run.\r
+ DXE Core will disable interrupts and turn off the timer and disable\r
+ interrupts after all the event handlers have run.\r
\r
@param[in] Event The Event that is being processed\r
@param[in] Context Event Context\r
**/\r
+STATIC\r
VOID\r
EFIAPI\r
GicV2ExitBootServicesEvent (\r
UINTN RegShift;\r
UINT32 CpuTarget;\r
\r
- // Make sure the Interrupt Controller Protocol is not already installed in the system.\r
+ // Make sure the Interrupt Controller Protocol is not already installed in\r
+ // the system.\r
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
\r
mGicInterruptInterfaceBase = PcdGet64 (PcdGicInterruptInterfaceBase);\r
);\r
}\r
\r
- //\r
// Targets the interrupts to the Primary Cpu\r
- //\r
-\r
- // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading\r
- // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each\r
- // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.\r
- // More Info in the GIC Specification about "Interrupt Processor Targets Registers"\r
- //\r
- // Read the first Interrupt Processor Targets Register (that corresponds to the 4\r
- // first SGIs)\r
+\r
+ // Only Primary CPU will run this code. We can identify our GIC CPU ID by\r
+ // reading the GIC Distributor Target register. The 8 first GICD_ITARGETSRn\r
+ // are banked to each connected CPU. These 8 registers hold the CPU targets\r
+ // fields for interrupts 0-31. More Info in the GIC Specification about\r
+ // "Interrupt Processor Targets Registers"\r
+\r
+ // Read the first Interrupt Processor Targets Register (that corresponds to\r
+ // the 4 first SGIs)\r
CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);\r
\r
- // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value\r
- // is 0 when we run on a uniprocessor platform.\r
+ // The CPU target is a bit field mapping each CPU to a GIC CPU Interface.\r
+ // This value is 0 when we run on a uniprocessor platform.\r
if (CpuTarget != 0) {\r
// The 8 first Interrupt Processor Targets Registers are read-only\r
for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {\r
- MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);\r
+ MmioWrite32 (\r
+ mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4),\r
+ CpuTarget\r
+ );\r
}\r
}\r
\r
ArmGicEnableDistributor (mGicDistributorBase);\r
\r
Status = InstallAndRegisterInterruptService (\r
- &gHardwareInterruptV2Protocol, GicV2IrqInterruptHandler, GicV2ExitBootServicesEvent);\r
+ &gHardwareInterruptV2Protocol,\r
+ GicV2IrqInterruptHandler,\r
+ GicV2ExitBootServicesEvent\r
+ );\r
\r
return Status;\r
}\r
/** @file\r
*\r
-* Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
@retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
\r
**/\r
+STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV3EnableInterruptSource (\r
@retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
\r
**/\r
+STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV3DisableInterruptSource (\r
@retval EFI_DEVICE_ERROR InterruptState is not valid\r
\r
**/\r
+STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV3GetInterruptSourceState (\r
return EFI_UNSUPPORTED;\r
}\r
\r
- *InterruptState = ArmGicIsInterruptEnabled (mGicDistributorBase, mGicRedistributorsBase, Source);\r
+ *InterruptState = ArmGicIsInterruptEnabled (\r
+ mGicDistributorBase,\r
+ mGicRedistributorsBase,\r
+ Source\r
+ );\r
\r
return EFI_SUCCESS;\r
}\r
@retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
\r
**/\r
+STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV3EndOfInterrupt (\r
EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r
\r
@param InterruptType Defines the type of interrupt or exception that\r
- occurred on the processor.This parameter is processor architecture specific.\r
+ occurred on the processor. This parameter is\r
+ processor architecture specific.\r
@param SystemContext A pointer to the processor context when\r
the interrupt occurred on the processor.\r
\r
@return None\r
\r
**/\r
+STATIC\r
VOID\r
EFIAPI\r
GicV3IrqInterruptHandler (\r
// Call the registered interrupt handler.\r
InterruptHandler (GicInterrupt, SystemContext);\r
} else {\r
- DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));\r
+ DEBUG ((DEBUG_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));\r
GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, GicInterrupt);\r
}\r
}\r
\r
-//\r
// The protocol instance produced by this driver\r
-//\r
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {\r
RegisterInterruptSource,\r
GicV3EnableInterruptSource,\r
UINT64 CpuTarget;\r
UINT64 MpId;\r
\r
- // Make sure the Interrupt Controller Protocol is not already installed in the system.\r
+ // Make sure the Interrupt Controller Protocol is not already installed in\r
+ // the system.\r
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
\r
mGicDistributorBase = PcdGet64 (PcdGicDistributorBase);\r
mGicRedistributorsBase = PcdGet64 (PcdGicRedistributorsBase);\r
mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);\r
\r
- //\r
// We will be driving this GIC in native v3 mode, i.e., with Affinity\r
// Routing enabled. So ensure that the ARE bit is set.\r
- //\r
if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r
MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE);\r
}\r
);\r
}\r
\r
- //\r
// Targets the interrupts to the Primary Cpu\r
- //\r
\r
if (FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r
- // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading\r
- // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each\r
- // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.\r
- // More Info in the GIC Specification about "Interrupt Processor Targets Registers"\r
- //\r
- // Read the first Interrupt Processor Targets Register (that corresponds to the 4\r
- // first SGIs)\r
+ // Only Primary CPU will run this code. We can identify our GIC CPU ID by\r
+ // reading the GIC Distributor Target register. The 8 first\r
+ // GICD_ITARGETSRn are banked to each connected CPU. These 8 registers\r
+ // hold the CPU targets fields for interrupts 0-31. More Info in the GIC\r
+ // Specification about "Interrupt Processor Targets Registers"\r
+\r
+ // Read the first Interrupt Processor Targets Register (that corresponds\r
+ // to the 4 first SGIs)\r
CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);\r
\r
- // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value\r
- // is 0 when we run on a uniprocessor platform.\r
+ // The CPU target is a bit field mapping each CPU to a GIC CPU Interface.\r
+ // This value is 0 when we run on a uniprocessor platform.\r
if (CpuTarget != 0) {\r
// The 8 first Interrupt Processor Targets Registers are read-only\r
for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {\r
- MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);\r
+ MmioWrite32 (\r
+ mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4),\r
+ CpuTarget\r
+ );\r
}\r
}\r
} else {\r
MpId = ArmReadMpidr ();\r
- CpuTarget = MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);\r
+ CpuTarget = MpId &\r
+ (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);\r
+\r
+ if ((MmioRead32 (\r
+ mGicDistributorBase + ARM_GIC_ICDDCR\r
+ ) & ARM_GIC_ICDDCR_DS) != 0) {\r
\r
- if ((MmioRead32 (mGicDistributorBase + ARM_GIC_ICDDCR) & ARM_GIC_ICDDCR_DS) != 0) {\r
- //\r
// If the Disable Security (DS) control bit is set, we are dealing with a\r
// GIC that has only one security state. In this case, let's assume we are\r
// executing in non-secure state (which is appropriate for DXE modules)\r
// and that no other firmware has performed any configuration on the GIC.\r
// This means we need to reconfigure all interrupts to non-secure Group 1\r
// first.\r
- //\r
- MmioWrite32 (mGicRedistributorsBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDISR, 0xffffffff);\r
+\r
+ MmioWrite32 (\r
+ mGicRedistributorsBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDISR,\r
+ 0xffffffff\r
+ );\r
\r
for (Index = 32; Index < mGicNumInterrupts; Index += 32) {\r
- MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDISR + Index / 8, 0xffffffff);\r
+ MmioWrite32 (\r
+ mGicDistributorBase + ARM_GIC_ICDISR + Index / 8,\r
+ 0xffffffff\r
+ );\r
}\r
}\r
\r
// Route the SPIs to the primary CPU. SPIs start at the INTID 32\r
for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {\r
- MmioWrite32 (mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), CpuTarget | ARM_GICD_IROUTER_IRM);\r
+ MmioWrite32 (\r
+ mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),\r
+ CpuTarget | ARM_GICD_IROUTER_IRM\r
+ );\r
}\r
}\r
\r
ArmGicEnableDistributor (mGicDistributorBase);\r
\r
Status = InstallAndRegisterInterruptService (\r
- &gHardwareInterruptV3Protocol, GicV3IrqInterruptHandler, GicV3ExitBootServicesEvent);\r
+ &gHardwareInterruptV3Protocol,\r
+ GicV3IrqInterruptHandler,\r
+ GicV3ExitBootServicesEvent\r
+ );\r
\r
return Status;\r
}\r
/** @file\r
*\r
-* Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+* Copyright (c) 2013-2017, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD\r
\r
#include "GenericWatchdog.h"\r
\r
-// The number of 100ns periods (the unit of time passed to these functions)\r
-// in a second\r
+/* The number of 100ns periods (the unit of time passed to these functions)\r
+ in a second */\r
#define TIME_UNITS_PER_SECOND 10000000\r
\r
-// Tick frequency of the generic timer that is the basis of the generic watchdog\r
+// Tick frequency of the generic timer basis of the generic watchdog.\r
UINTN mTimerFrequencyHz = 0;\r
\r
-// In cases where the compare register was set manually, information about\r
-// how long the watchdog was asked to wait cannot be retrieved from hardware.\r
-// It is therefore stored here. 0 means the timer is not running.\r
+/* In cases where the compare register was set manually, information about\r
+ how long the watchdog was asked to wait cannot be retrieved from hardware.\r
+ It is therefore stored here. 0 means the timer is not running. */\r
UINT64 mNumTimerTicks = 0;\r
\r
EFI_HARDWARE_INTERRUPT_PROTOCOL *mInterruptProtocol;\r
return MmioWrite32 (GENERIC_WDOG_CONTROL_STATUS_REG, GENERIC_WDOG_DISABLED);\r
}\r
\r
-/**\r
- On exiting boot services we must make sure the Watchdog Timer\r
+/** On exiting boot services we must make sure the Watchdog Timer\r
is stopped.\r
**/\r
VOID\r
mNumTimerTicks = 0;\r
}\r
\r
-/*\r
- This function is called when the watchdog's first signal (WS0) goes high.\r
- It uses the ResetSystem Runtime Service to reset the board.\r
+/* This function is called when the watchdog's first signal (WS0) goes high.\r
+ It uses the ResetSystem Runtime Service to reset the board.\r
*/\r
VOID\r
EFIAPI\r
IN EFI_SYSTEM_CONTEXT SystemContext\r
)\r
{\r
- STATIC CONST CHAR16 ResetString[] = L"The generic watchdog timer ran out.";\r
+ STATIC CONST CHAR16 ResetString[]= L"The generic watchdog timer ran out.";\r
\r
WatchdogDisable ();\r
\r
then the new handler is registered and EFI_SUCCESS is returned.\r
If NotifyFunction is NULL, and a handler is already registered,\r
then that handler is unregistered.\r
- If an attempt is made to register a handler when a handler is already registered,\r
- then EFI_ALREADY_STARTED is returned.\r
- If an attempt is made to unregister a handler when a handler is not registered,\r
- then EFI_INVALID_PARAMETER is returned.\r
+ If an attempt is made to register a handler when a handler is already\r
+ registered, then EFI_ALREADY_STARTED is returned.\r
+ If an attempt is made to unregister a handler when a handler is not\r
+ registered, then EFI_INVALID_PARAMETER is returned.\r
\r
@param This The EFI_TIMER_ARCH_PROTOCOL instance.\r
@param NotifyFunction The function to call when a timer interrupt fires.\r
information is used to signal timer based events.\r
NULL will unregister the handler.\r
\r
- @retval EFI_SUCCESS The watchdog timer handler was registered.\r
- @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already\r
- registered.\r
- @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not\r
- previously registered.\r
+ @retval EFI_UNSUPPORTED The code does not support NotifyFunction.\r
\r
**/\r
EFI_STATUS\r
\r
/**\r
This function sets the amount of time to wait before firing the watchdog\r
- timer to TimerPeriod 100 nS units. If TimerPeriod is 0, then the watchdog\r
+ timer to TimerPeriod 100ns units. If TimerPeriod is 0, then the watchdog\r
timer is disabled.\r
\r
@param This The EFI_WATCHDOG_TIMER_ARCH_PROTOCOL instance.\r
- @param TimerPeriod The amount of time in 100 nS units to wait before the watchdog\r
- timer is fired. If TimerPeriod is zero, then the watchdog\r
- timer is disabled.\r
+ @param TimerPeriod The amount of time in 100ns units to wait before\r
+ the watchdog timer is fired. If TimerPeriod is zero,\r
+ then the watchdog timer is disabled.\r
\r
- @retval EFI_SUCCESS The watchdog timer has been programmed to fire in Time\r
- 100 nS units.\r
- @retval EFI_DEVICE_ERROR A watchdog timer could not be programmed due to a device\r
- error.\r
+ @retval EFI_SUCCESS The watchdog timer has been programmed to fire\r
+ in Time 100ns units.\r
+ @retval EFI_DEVICE_ERROR A watchdog timer could not be programmed due\r
+ to a device error.\r
\r
**/\r
EFI_STATUS\r
UINTN SystemCount;\r
EFI_STATUS Status;\r
\r
- // if TimerPerdiod is 0, this is a request to stop the watchdog.\r
+ // if TimerPeriod is 0, this is a request to stop the watchdog.\r
if (TimerPeriod == 0) {\r
mNumTimerTicks = 0;\r
return WatchdogDisable ();\r
// Work out how many timer ticks will equate to TimerPeriod\r
mNumTimerTicks = (mTimerFrequencyHz * TimerPeriod) / TIME_UNITS_PER_SECOND;\r
\r
- //\r
- // If the number of required ticks is greater than the max number the\r
- // watchdog's offset register (WOR) can hold, we need to manually compute and\r
- // set the compare register (WCV)\r
- //\r
+ /* If the number of required ticks is greater than the max the watchdog's\r
+ offset register (WOR) can hold, we need to manually compute and set\r
+ the compare register (WCV) */\r
if (mNumTimerTicks > MAX_UINT32) {\r
- //\r
- // We need to enable the watchdog *before* writing to the compare register,\r
- // because enabling the watchdog causes an "explicit refresh", which\r
- // clobbers the compare register (WCV). In order to make sure this doesn't\r
- // trigger an interrupt, set the offset to max.\r
- //\r
+ /* We need to enable the watchdog *before* writing to the compare register,\r
+ because enabling the watchdog causes an "explicit refresh", which\r
+ clobbers the compare register (WCV). In order to make sure this doesn't\r
+ trigger an interrupt, set the offset to max. */\r
Status = WatchdogWriteOffsetRegister (MAX_UINT32);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
/**\r
- This function retrieves the period of timer interrupts in 100 ns units,\r
+ This function retrieves the period of timer interrupts in 100ns units,\r
returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod\r
is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is\r
returned, then the timer is currently disabled.\r
\r
@param This The EFI_TIMER_ARCH_PROTOCOL instance.\r
- @param TimerPeriod A pointer to the timer period to retrieve in 100\r
- ns units. If 0 is returned, then the timer is\r
+ @param TimerPeriod A pointer to the timer period to retrieve in\r
+ 100ns units. If 0 is returned, then the timer is\r
currently disabled.\r
\r
\r
this function will not have any chance of executing.\r
\r
@param SetTimerPeriod\r
- Sets the period of the timer interrupt in 100 nS units.\r
+ Sets the period of the timer interrupt in 100ns units.\r
This function is optional, and may return EFI_UNSUPPORTED.\r
If this function is supported, then the timer period will\r
be rounded up to the nearest supported timer period.\r
\r
@param GetTimerPeriod\r
- Retrieves the period of the timer interrupt in 100 nS units.\r
+ Retrieves the period of the timer interrupt in 100ns units.\r
\r
**/\r
EFI_WATCHDOG_TIMER_ARCH_PROTOCOL gWatchdogTimer = {\r
- (EFI_WATCHDOG_TIMER_REGISTER_HANDLER) WatchdogRegisterHandler,\r
- (EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD) WatchdogSetTimerPeriod,\r
- (EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD) WatchdogGetTimerPeriod\r
+ (EFI_WATCHDOG_TIMER_REGISTER_HANDLER)WatchdogRegisterHandler,\r
+ (EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD)WatchdogSetTimerPeriod,\r
+ (EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD)WatchdogGetTimerPeriod\r
};\r
\r
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;\r
EFI_STATUS Status;\r
EFI_HANDLE Handle;\r
\r
- //\r
- // Make sure the Watchdog Timer Architectural Protocol has not been installed\r
- // in the system yet.\r
- // This will avoid conflicts with the universal watchdog\r
- //\r
+ /* Make sure the Watchdog Timer Architectural Protocol has not been installed\r
+ in the system yet.\r
+ This will avoid conflicts with the universal watchdog */\r
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolGuid);\r
\r
mTimerFrequencyHz = ArmGenericTimerGetTimerFreq ();\r
\r
// Register for an ExitBootServicesEvent\r
Status = gBS->CreateEvent (\r
- EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY,\r
- WatchdogExitBootServicesEvent, NULL, &EfiExitBootServicesEvent\r
+ EVT_SIGNAL_EXIT_BOOT_SERVICES,\r
+ TPL_NOTIFY,\r
+ WatchdogExitBootServicesEvent,\r
+ NULL,\r
+ &EfiExitBootServicesEvent\r
);\r
if (!EFI_ERROR (Status)) {\r
// Install interrupt handler\r
);\r
if (!EFI_ERROR (Status)) {\r
Status = mInterruptProtocol->RegisterInterruptSource (\r
- mInterruptProtocol,\r
- FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),\r
- WatchdogInterruptHandler\r
- );\r
+ mInterruptProtocol,\r
+ FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),\r
+ WatchdogInterruptHandler\r
+ );\r
if (!EFI_ERROR (Status)) {\r
// Install the Timer Architectural Protocol onto a new handle\r
Handle = NULL;\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&Handle,\r
- &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer,\r
+ &gEfiWatchdogTimerArchProtocolGuid,\r
+ &gWatchdogTimer,\r
NULL\r
);\r
}\r
}\r
}\r
\r
- if (EFI_ERROR (Status)) {\r
- // The watchdog failed to initialize\r
- ASSERT (FALSE);\r
- }\r
+ ASSERT_EFI_ERROR (Status);\r
\r
mNumTimerTicks = 0;\r
WatchdogDisable ();\r
/** @file\r
*\r
-* Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
\r
#include <Library/ArmGicArchLib.h>\r
\r
-//\r
// GIC Distributor\r
-//\r
#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register\r
#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r
#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register\r
#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)\r
#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)\r
\r
-//\r
// GIC Redistributor\r
-//\r
\r
#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB\r
#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB\r
#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers\r
#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers\r
\r
-//\r
// GIC Cpu interface\r
-//\r
#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register\r
#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r
#define ARM_GIC_ICCBPR 0x08 // Binary Point Register\r
IN INTN GicInterruptInterfaceBase\r
);\r
\r
-//\r
// GIC Secure interfaces\r
-//\r
VOID\r
EFIAPI\r
ArmGicSetupNonSecure (\r
* in the GICv3 the register value is only the InterruptId.\r
*\r
* @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface\r
- * @param InterruptId InterruptId read from the Interrupt Acknowledge Register\r
+ * @param InterruptId InterruptId read from the Interrupt\r
+ * Acknowledge Register\r
*\r
* @retval value returned by the Interrupt Acknowledge Register\r
*\r
IN UINTN Source\r
);\r
\r
-//\r
// GIC revision 2 specific declarations\r
-//\r
\r
-// Interrupts from 1020 to 1023 are considered as special interrupts (eg: spurious interrupts)\r
-#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >= 1020) && ((Interrupt) <= 1023))\r
+// Interrupts from 1020 to 1023 are considered as special interrupts\r
+// (eg: spurious interrupts)\r
+#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \\r
+ (((Interrupt) >= 1020) && ((Interrupt) <= 1023))\r
\r
VOID\r
EFIAPI\r
IN UINTN Source\r
);\r
\r
-//\r
// GIC revision 3 specific declarations\r
-//\r
\r
#define ICC_SRE_EL2_SRE (1 << 0)\r
\r
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