--- /dev/null
+/** @file\r
+ CPUID leaf definitions.\r
+\r
+ Provides defines for CPUID leaf indexes. Data structures are provided for\r
+ registers returned by a CPUID leaf that contain one or more bit fields.\r
+ If a register returned is a single 32-bit value, then a data structure is\r
+ not provided for that register.\r
+\r
+ Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Specification Reference:\r
+ AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34\r
+\r
+**/\r
+\r
+#ifndef __AMD_CPUID_H__\r
+#define __AMD_CPUID_H__\r
+\r
+/**\r
+\r
+ Memory Encryption Information\r
+\r
+ @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)\r
+\r
+ @retval EAX Returns the memory encryption feature support status.\r
+ @retval EBX If memory encryption feature is present then return\r
+ the page table bit number used to enable memory encryption support\r
+ and reducing of physical address space in bits.\r
+ @retval ECX Returns number of encrypted guest supported simultaneosuly.\r
+ @retval EDX Returns minimum SEV enabled and SEV disbled ASID..\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ UINT32 Edx;\r
+\r
+ AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx);\r
+ @endcode\r
+**/\r
+\r
+#define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F\r
+\r
+/**\r
+ CPUID Memory Encryption support information EAX for CPUID leaf\r
+ #CPUID_MEMORY_ENCRYPTION_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Secure Memory Encryption (Sme) Support\r
+ ///\r
+ UINT32 SmeBit:1;\r
+\r
+ ///\r
+ /// [Bit 1] Secure Encrypted Virtualization (Sev) Support\r
+ ///\r
+ UINT32 SevBit:1;\r
+\r
+ ///\r
+ /// [Bit 2] Page flush MSR support\r
+ ///\r
+ UINT32 PageFlushMsrBit:1;\r
+\r
+ ///\r
+ /// [Bit 3] Encrypted state support\r
+ ///\r
+ UINT32 SevEsBit:1;\r
+\r
+ ///\r
+ /// [Bit 4:31] Reserved\r
+ ///\r
+ UINT32 ReservedBits:28;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_MEMORY_ENCRYPTION_INFO_EAX;\r
+\r
+/**\r
+ CPUID Memory Encryption support information EBX for CPUID leaf\r
+ #CPUID_MEMORY_ENCRYPTION_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0:5] Page table bit number used to enable memory encryption\r
+ ///\r
+ UINT32 PtePosBits:6;\r
+\r
+ ///\r
+ /// [Bit 6:11] Reduction of system physical address space bits when memory encryption is enabled\r
+ ///\r
+ UINT32 ReducedPhysBits:5;\r
+\r
+ ///\r
+ /// [Bit 12:31] Reserved\r
+ ///\r
+ UINT32 ReservedBits:21;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_MEMORY_ENCRYPTION_INFO_EBX;\r
+\r
+/**\r
+ CPUID Memory Encryption support information ECX for CPUID leaf\r
+ #CPUID_MEMORY_ENCRYPTION_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0:31] Number of encrypted guest supported simultaneously\r
+ ///\r
+ UINT32 NumGuests;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_MEMORY_ENCRYPTION_INFO_ECX;\r
+\r
+/**\r
+ CPUID Memory Encryption support information EDX for CPUID leaf\r
+ #CPUID_MEMORY_ENCRYPTION_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0:31] Minimum SEV enabled, SEV-ES disabled ASID\r
+ ///\r
+ UINT32 MinAsid;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_MEMORY_ENCRYPTION_INFO_EDX;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Specification Reference:\r
+ AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34\r
+\r
+**/\r
+\r
+#ifndef __FAM17_MSR_H\r
+#define __FAM17_MSR_H\r
+\r
+/**\r
+ Secure Encrypted Virtualization (SEV) status register\r
+\r
+**/\r
+#define MSR_SEV_STATUS 0xc0010131\r
+\r
+/**\r
+ MSR information returned for #MSR_SEV_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled\r
+ ///\r
+ UINT32 SevBit:1;\r
+\r
+ ///\r
+ /// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled\r
+ ///\r
+ UINT32 SevEsBit:1;\r
+\r
+ UINT32 Reserved:30;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SEV_STATUS_REGISTER;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Specification Reference:\r
+ AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34\r
+\r
+**/\r
+\r
+#ifndef __AMD_MSR_H__\r
+#define __AMD_MSR_H__\r
+\r
+#include <Register/ArchitecturalMsr.h>\r
+#include <Register/Amd/Fam17Msr.h>\r
+\r
+#endif\r