/** @file\r
\r
- Copyright (c) 2011, ARM Limited. All rights reserved.\r
+ Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
#include <Base.h>\r
#include <Library/ArmLib.h>\r
#include <Library/ArmCpuLib.h>\r
-#include <Library/ArmGicLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PcdLib.h>\r
\r
-VOID\r
-ArmCpuSynchronizeSignal (\r
- IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
- )\r
-{\r
- if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {\r
- // Do nothing, Cortex A9 secondary cores are waiting for the SCU to be\r
- // enabled (done by ArmCpuSetup()) as a way to know when the Init Boot\r
- // Mem as been initialized\r
- } else {\r
- // Send SGI to all Secondary core to wake them up from WFI state.\r
- ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
- }\r
-}\r
-\r
-VOID\r
-CArmCpuSynchronizeWait (\r
- IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
- )\r
-{\r
- // Waiting for the SGI from the primary core\r
- ArmCallWFI ();\r
-\r
- // Acknowledge the interrupt and send End of Interrupt signal.\r
- ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
-}\r
-\r
-#if 0\r
-VOID\r
-ArmEnableScu (\r
- VOID\r
- )\r
-{\r
- INTN ScuBase;\r
-\r
- ScuBase = ArmGetScuBaseAddress();\r
-\r
- // Invalidate all: write -1 to SCU Invalidate All register\r
- MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);\r
- // Enable SCU\r
- MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);\r
-}\r
-#endif\r
-\r
VOID\r
ArmCpuSetup (\r
IN UINTN MpId\r
)\r
{\r
- /*AMP mode and SMP mode\r
-\r
- By default, the processor is in AMP mode (bit 5 reset to 0). To prevent coherent data corruption the sequence to turn on MP11 CPUs in SMP mode is:\r
-\r
- 1.Write the SCU register to change CPU mode.\r
- 2.Disable interrupts.\r
- 3.Clean and invalidate all the D-cache.\r
- 4.Write SMP/nAMP bit as 1.\r
- 5.Enable interrupts.\r
-\r
- Source: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/BIHHFGEC.html\r
- */\r
-\r
- // If MPCore then Enable the SCU\r
- if (ArmIsMpCore()) {\r
- //ArmEnableScu ();\r
- }\r
+ ASSERT(0); //TODO: Implement me\r
}\r
\r
\r
IN UINTN MpId\r
)\r
{\r
-#if 0\r
- INTN ScuBase;\r
-\r
- ArmSetAuxCrBit (A9_FEATURE_SMP);\r
-\r
- // Make the SCU accessible in Non Secure world\r
- if (IS_PRIMARY_CORE(MpId)) {\r
- ScuBase = ArmGetScuBaseAddress();\r
-\r
- // Allow NS access to SCU register\r
- MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);\r
- // Allow NS access to Private Peripherals\r
- MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);\r
- }\r
-#endif\r
+ ASSERT(0); //TODO: Implement me\r
}\r
\r
#/* @file\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
# \r
# This program and the accompanying materials \r
# are licensed and made available under the terms and conditions of the BSD License \r
\r
[LibraryClasses]\r
ArmLib\r
- ArmGicSecLib\r
IoLib\r
PcdLib\r
\r
[Sources.common]\r
Arm11Lib.c\r
- Arm11Helper.asm | RVCT\r
- Arm11Helper.S | GCC\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
-\r
- gArmTokenSpaceGuid.PcdGicDistributorBase\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
/** @file\r
\r
- Copyright (c) 2011, ARM Limited. All rights reserved.\r
+ Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
#include <Base.h>\r
#include <Library/ArmLib.h>\r
#include <Library/ArmCpuLib.h>\r
-#include <Library/ArmGicLib.h>\r
#include <Library/ArmV7ArchTimerLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
\r
#include <Chipset/ArmV7.h>\r
\r
-VOID\r
-ArmCpuSynchronizeSignal (\r
- IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
- )\r
-{\r
- if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {\r
- // Do nothing, Cortex A15 secondary cores are waiting for the GIC Distributor\r
- // to be enabled (done by the Sec module itself) as a way to know when the Init Boot\r
- // Mem as been initialized\r
- } else {\r
- // Send SGI to all Secondary core to wake them up from WFI state.\r
- ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
- }\r
-}\r
-\r
-VOID\r
-CArmCpuSynchronizeWait (\r
- IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
- )\r
-{\r
- // Waiting for the SGI from the primary core\r
- ArmCallWFI ();\r
-\r
- // Acknowledge the interrupt and send End of Interrupt signal.\r
- ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
-}\r
-\r
VOID\r
ArmCpuSetup (\r
IN UINTN MpId\r
#/* @file\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
# \r
# This program and the accompanying materials \r
# are licensed and made available under the terms and conditions of the BSD License \r
\r
[LibraryClasses]\r
ArmLib\r
- ArmGicSecLib\r
IoLib\r
PcdLib\r
\r
[Sources.common]\r
ArmCortexA15Lib.c\r
- ArmCortexA15Helper.asm | RVCT\r
- ArmCortexA15Helper.S | GCC\r
\r
[FeaturePcd]\r
\r
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
gArmTokenSpaceGuid.PcdArmPrimaryCore\r
\r
- gArmTokenSpaceGuid.PcdGicDistributorBase\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
-\r
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz\r
\r
#include <Chipset/ArmV7.h>\r
\r
-VOID\r
-ArmCpuSynchronizeWait (\r
- IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
- )\r
-{\r
- // The CortexA8 is a Unicore CPU. We must not use Synchronization functions\r
- ASSERT(0);\r
-}\r
-\r
-VOID\r
-ArmCpuSynchronizeSignal (\r
- IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
- )\r
-{\r
- // The CortexA8 is a Unicore CPU. We must not use Synchronization functions\r
- ASSERT(0);\r
-}\r
-\r
VOID\r
ArmCpuSetup (\r
IN UINTN MpId\r
//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
.text\r
.align 3\r
\r
-GCC_ASM_EXPORT(ArmCpuSynchronizeWait)\r
GCC_ASM_EXPORT(ArmGetScuBaseAddress)\r
-GCC_ASM_IMPORT(CArmCpuSynchronizeWait)\r
-\r
-// VOID\r
-// ArmCpuSynchronizeWait (\r
-// IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
-// );\r
-ASM_PFX(ArmCpuSynchronizeWait):\r
- cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
- // The SCU enabled is the event to tell us the Init Boot Memory is initialized\r
- beq ASM_PFX(ArmWaitScuEnabled)\r
- // Case when the stack has been set up\r
- push {r1,lr}\r
- LoadConstantToReg (ASM_PFX(CArmCpuSynchronizeWait), r1)\r
- blx r1\r
- pop {r1,lr}\r
- bx lr\r
\r
// IN None\r
// OUT r0 = SCU Base Address\r
// offset 0x0000 from the Private Memory Region.\r
mrc p15, 4, r0, c15, c0, 0\r
bx lr\r
-\r
-ASM_PFX(ArmWaitScuEnabled):\r
- // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
- // offset 0x0000 from the Private Memory Region.\r
- mrc p15, 4, r0, c15, c0, 0\r
- add r0, r0, #A9_SCU_CONTROL_OFFSET\r
- ldr r0, [r0]\r
- cmp r0, #1\r
- bne ASM_PFX(ArmWaitScuEnabled)\r
- bx lr\r
//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
\r
INCLUDE AsmMacroIoLib.inc\r
\r
- EXPORT ArmCpuSynchronizeWait\r
EXPORT ArmGetScuBaseAddress\r
- IMPORT CArmCpuSynchronizeWait\r
\r
PRESERVE8\r
AREA ArmCortexA9Helper, CODE, READONLY\r
\r
-// VOID\r
-// ArmCpuSynchronizeWait (\r
-// IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
-// );\r
-ArmCpuSynchronizeWait\r
- cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
- // The SCU enabled is the event to tell us the Init Boot Memory is initialized\r
- beq ArmWaitScuEnabled\r
- // Case when the stack has been set up\r
- push {r1,lr}\r
- LoadConstantToReg (CArmCpuSynchronizeWait, r1)\r
- blx r1\r
- pop {r1,lr}\r
- bx lr\r
-\r
// IN None\r
// OUT r0 = SCU Base Address\r
ArmGetScuBaseAddress\r
mrc p15, 4, r0, c15, c0, 0\r
bx lr\r
\r
-ArmWaitScuEnabled\r
- // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
- // offset 0x0000 from the Private Memory Region.\r
- mrc p15, 4, r0, c15, c0, 0\r
- add r0, r0, #A9_SCU_CONTROL_OFFSET\r
- ldr r0, [r0]\r
- cmp r0, #1\r
- bne ArmWaitScuEnabled\r
- bx lr\r
-\r
END\r
/** @file\r
\r
- Copyright (c) 2011, ARM Limited. All rights reserved.\r
+ Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
#include <Base.h>\r
#include <Library/ArmLib.h>\r
#include <Library/ArmCpuLib.h>\r
-#include <Library/ArmGicLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PcdLib.h>\r
\r
#include <Chipset/ArmCortexA9.h>\r
\r
-VOID\r
-ArmCpuSynchronizeSignal (\r
- IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
- )\r
-{\r
- if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {\r
- // Do nothing, Cortex A9 secondary cores are waiting for the SCU to be\r
- // enabled (done by ArmCpuSetup()) as a way to know when the Init Boot\r
- // Mem as been initialized\r
- } else {\r
- // Send SGI to all Secondary core to wake them up from WFI state.\r
- ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
- }\r
-}\r
-\r
-VOID\r
-CArmCpuSynchronizeWait (\r
- IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
- )\r
-{\r
- // Waiting for the SGI from the primary core\r
- ArmCallWFI ();\r
-\r
- // Acknowledge the interrupt and send End of Interrupt signal.\r
- ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
-}\r
-\r
VOID\r
ArmEnableScu (\r
VOID\r
#/* @file\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
# \r
# This program and the accompanying materials \r
# are licensed and made available under the terms and conditions of the BSD License \r
\r
[LibraryClasses]\r
ArmLib\r
- ArmGicSecLib\r
IoLib\r
PcdLib\r
\r
[FixedPcd]\r
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
gArmTokenSpaceGuid.PcdArmPrimaryCore\r
-\r
- gArmTokenSpaceGuid.PcdGicDistributorBase\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
/** @file
- Copyright (c) 2011, ARM Limited. All rights reserved.
+ Copyright (c) 2011-2012, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
#ifndef __ARMCPU_LIB__
#define __ARMCPU_LIB__
-// These are #define and not enum to be used in assembly files
-#define ARM_CPU_EVENT_DEFAULT 0
-#define ARM_CPU_EVENT_BOOT_MEM_INIT 1
-#define ARM_CPU_EVENT_SECURE_INIT 2
-
-typedef UINTN ARM_CPU_SYNCHRONIZE_EVENT;
-
-
-VOID
-ArmCpuSynchronizeWait (
- IN ARM_CPU_SYNCHRONIZE_EVENT Event
- );
-
-VOID
-ArmCpuSynchronizeSignal (
- IN ARM_CPU_SYNCHRONIZE_EVENT Event
- );
-
VOID
ArmCpuSetup (
IN UINTN MpId
VOID
EFIAPI
+ArmCallSEV (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmCallWFE (
+ VOID
+ );
+
ArmCallWFI (
VOID
);
#------------------------------------------------------------------------------ \r
#\r
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
GCC_ASM_EXPORT(ArmWriteNsacr)\r
GCC_ASM_EXPORT(ArmWriteScr)\r
GCC_ASM_EXPORT(ArmWriteVMBar)\r
+GCC_ASM_EXPORT(ArmCallWFE)\r
+GCC_ASM_EXPORT(ArmCallSEV)\r
\r
#------------------------------------------------------------------------------\r
\r
mcr p15, 0, r0, c12, c0, 1\r
bx lr\r
\r
+ASM_PFX(ArmCallWFE):\r
+ wfe\r
+ bx lr\r
+\r
+ASM_PFX(ArmCallSEV):\r
+ sev\r
+ bx lr\r
+\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
EXPORT ArmWriteNsacr\r
EXPORT ArmWriteScr\r
EXPORT ArmWriteVMBar\r
+ EXPORT ArmCallWFE\r
+ EXPORT ArmCallSEV\r
\r
AREA ArmLibSupport, CODE, READONLY\r
\r
mcr p15, 0, r0, c12, c0, 1\r
bx lr\r
\r
+ArmCallWFE\r
+ wfe\r
+ blx lr\r
+\r
+ArmCallSEV\r
+ sev\r
+ blx lr\r
+\r
END\r
BaseLib\r
DebugLib\r
DebugAgentLib\r
- ArmCpuLib\r
ArmLib\r
ArmGicLib\r
IoLib\r
#/** @file\r
# \r
-# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r
+# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
+# \r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
BaseLib\r
DebugLib\r
DebugAgentLib\r
- ArmCpuLib\r
ArmLib\r
IoLib\r
TimerLib\r
\r
#include <PiPei.h>\r
\r
-#include <Library/ArmCpuLib.h>\r
#include <Library/DebugAgentLib.h>\r
#include <Library/PrePiLib.h>\r
#include <Library/PrintLib.h>\r
if (IS_PRIMARY_CORE(MpId)) {\r
mGlobalVariableBase = GlobalVariableBase;\r
if (ArmIsMpCore()) {\r
- ArmCpuSynchronizeSignal (ARM_CPU_EVENT_DEFAULT);\r
+ // Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)\r
+ ArmCallSEV ();\r
}\r
} else {\r
- // Wait the Primay core has defined the address of the Global Variable region\r
- ArmCpuSynchronizeWait (ARM_CPU_EVENT_DEFAULT);\r
+ // Wait the Primay core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)\r
+ ArmCallWFE ();\r
}\r
}\r
\r
// Primary CPU clears out the SCU tag RAMs, secondaries wait
if (IS_PRIMARY_CORE(MpId)) {
if (ArmIsMpCore()) {
- ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT);
+ // Signal for the initial memory is configured (event: BOOT_MEM_INIT)
+ ArmCallSEV ();
}
// SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
// Setup the Trustzone Chipsets
if (IS_PRIMARY_CORE(MpId)) {
if (ArmIsMpCore()) {
- // Waiting for the Primary Core to have finished to initialize the Secure World
- ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT);
+ // Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)
+ ArmCallSEV ();
}
} else {
// The secondary cores need to wait until the Trustzone chipsets configuration is done
// before switching to Non Secure World
- // Waiting for the Primary Core to have finished to initialize the Secure World
- ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT);
+ // Wait for the Primary Core to finish the initialization of the Secure World (event: EVENT_SECURE_INIT)
+ ArmCallWFE ();
}
- // Call the Platform specific fucntion to execute additional actions if required
+ // Call the Platform specific function to execute additional actions if required
JumpAddress = PcdGet32 (PcdFvBaseAddress);
ArmPlatformSecExtraAction (MpId, &JumpAddress);
GCC_ASM_IMPORT(ArmWriteVBar)\r
GCC_ASM_IMPORT(ArmReadMpidr)\r
GCC_ASM_IMPORT(SecVectorTable)\r
-GCC_ASM_IMPORT(ArmCpuSynchronizeWait)\r
+GCC_ASM_IMPORT(ArmCallWFE)\r
GCC_ASM_EXPORT(_ModuleEntryPoint)\r
\r
StartupAddr: .word ASM_PFX(CEntryPoint)\r
beq _InitMem\r
\r
_WaitInitMem:\r
- mov r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
- bl ASM_PFX(ArmCpuSynchronizeWait)\r
+ // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
+ bl ASM_PFX(ArmCallWFE)\r
// Now the Init Mem is initialized, we setup the secondary core stacks\r
b _SetupSecondaryCoreStack\r
\r
IMPORT ArmDisableCachesAndMmu\r
IMPORT ArmWriteVBar\r
IMPORT ArmReadMpidr\r
+ IMPORT ArmCallWFE\r
IMPORT SecVectorTable\r
- IMPORT ArmCpuSynchronizeWait\r
EXPORT _ModuleEntryPoint\r
\r
PRESERVE8\r
beq _InitMem\r
\r
_WaitInitMem\r
- mov r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
- bl ArmCpuSynchronizeWait\r
+ // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
+ bl ArmCallWFE\r
// Now the Init Mem is initialized, we setup the secondary core stacks\r
b _SetupSecondaryCoreStack\r
\r
projects / mirror_edk2.git / commitdiff