Ia32/EnablePaging64.asm | INTEL\r
Ia32/EnableCache.nasm| INTEL\r
Ia32/EnableCache.asm | INTEL\r
+ Ia32/DisableCache.nasm| INTEL\r
Ia32/DisableCache.asm | INTEL\r
Ia32/RdRand.nasm| INTEL\r
Ia32/RdRand.asm | INTEL\r
Ia32/LShiftU64.S | GCC \r
Ia32/EnableCache.nasm| GCC\r
Ia32/EnableCache.S | GCC\r
+ Ia32/DisableCache.nasm| GCC\r
Ia32/DisableCache.S | GCC\r
Ia32/RdRand.nasm| GCC\r
Ia32/RdRand.S | GCC\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; DisableCache.Asm\r
+;\r
+; Abstract:\r
+;\r
+; Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a\r
+; WBINVD instruction.\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ SECTION .text\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmDisableCache (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+global ASM_PFX(AsmDisableCache)\r
+ASM_PFX(AsmDisableCache):\r
+ mov eax, cr0\r
+ bts eax, 30\r
+ btr eax, 29\r
+ mov cr0, eax\r
+ wbinvd\r
+ ret\r
+\r