Add computing Unit Chipset Subclass Progress Code definitions from PI 1.2 specification.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9146 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdePkg/Include/Pi/PiStatusCode.h b/MdePkg/Include/Pi/PiStatusCode.h
index ed808daf098c89f042930d84f3899343b5039d17..23c6a3836a148a91ea66fec2f401f07c0e69c5b4 100644 (file)
--- a/MdePkg/Include/Pi/PiStatusCode.h
+++ b/MdePkg/Include/Pi/PiStatusCode.h
@@ -208,6 +208,61 @@ typedef struct {
 // Computing Unit Chipset Subclass Progress Code definitions.\r
 //\r
 \r
+///\r
+/// South Bridge initialization prior to memory detection\r
+///\r
+#define EFI_CHIPSET_PC_PEI_CAR_SB_INIT      (EFI_SUBCLASS_SPECIFIC|0x00000000)\r
+\r
+///\r
+/// North Bridge initialization prior to memory detection\r
+///\r
+#define EFI_CHIPSET_PC_PEI_CAR_NB_INIT      (EFI_SUBCLASS_SPECIFIC|0x00000001)\r
+\r
+///\r
+/// South Bridge initialization after memory detection\r
+///\r
+#define EFI_CHIPSET_PC_PEI_MEM_SB_INIT      (EFI_SUBCLASS_SPECIFIC|0x00000002)\r
+\r
+///\r
+/// North Bridge initialization after memory detection\r
+///\r
+#define EFI_CHIPSET_PC_PEI_MEM_NB_INIT      (EFI_SUBCLASS_SPECIFIC|0x00000003)\r
+\r
+///\r
+/// PCI Host Bridge DXE initialization\r
+///\r
+#define EFI_CHIPSET_PC_DXE_HB_INIT          (EFI_SUBCLASS_SPECIFIC|0x00000004)\r
+\r
+///\r
+/// North Bridge DXE initialization\r
+///\r
+#define EFI_CHIPSET_PC_DXE_NB_INIT          (EFI_SUBCLASS_SPECIFIC|0x00000005)\r
+\r
+///\r
+/// North Bridge specific SMM initialization in DXE\r
+///\r
+#define EFI_CHIPSET_PC_DXE_NB_SMM_INIT      (EFI_SUBCLASS_SPECIFIC|0x00000006)\r
+\r
+///\r
+/// Initialization of the South Bridge specific UEFI Runtime Services\r
+///\r
+#define EFI_CHIPSET_PC_DXE_SB_RT_INIT       (EFI_SUBCLASS_SPECIFIC|0x00000007)\r
+\r
+///\r
+/// South Bridge DXE initialization\r
+///\r
+#define EFI_CHIPSET_PC_DXE_SB_INIT          (EFI_SUBCLASS_SPECIFIC|0x00000008)\r
+\r
+///\r
+/// South Bridge specific SMM initialization in DXE\r
+///\r
+#define EFI_CHIPSET_PC_DXE_SB_SMM_INIT      (EFI_SUBCLASS_SPECIFIC|0x00000009)\r
+\r
+///\r
+/// Initialization of the South Bridge devices\r
+///\r
+#define EFI_CHIPSET_PC_DXE_SB_DEVICES_INIT  (EFI_SUBCLASS_SPECIFIC|0x0000000a)\r
+\r
 ///\r
 /// Computing Unit Class Error Code definitions.\r
 /// These are shared by all subclasses.\r