#pragma pack()\r
\r
//\r
-// Define for Desriptor\r
+// Define for Descriptor\r
//\r
#define ACPI_SMALL_ITEM_FLAG 0x00\r
#define ACPI_LARGE_ITEM_FLAG 0x01\r
#pragma pack(1)\r
\r
///\r
-/// The commond definition of QWORD, DWORD, and WORD\r
+/// The common definition of QWORD, DWORD, and WORD\r
/// Address Space Descriptors.\r
///\r
typedef PACKED struct {\r
#include <IndustryStandard/Acpi10.h>\r
\r
//\r
-// Define for Desriptor\r
+// Define for Descriptor\r
//\r
#define ACPI_LARGE_GENERIC_REGISTER_DESCRIPTOR_NAME 0x02\r
\r
#define EFI_ACPI_2_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')\r
\r
///\r
-/// "SPCR" Serial Port Concole Redirection Table\r
+/// "SPCR" Serial Port Console Redirection Table\r
///\r
#define EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\r
\r
#include <IndustryStandard/Acpi20.h>\r
\r
//\r
-// Define for Desriptor\r
+// Define for Descriptor\r
//\r
#define ACPI_LARGE_EXTENDED_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0B\r
\r
#define EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')\r
\r
///\r
-/// "SPCR" Serial Port Concole Redirection Table\r
+/// "SPCR" Serial Port Console Redirection Table\r
///\r
#define EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\r
\r
#define EFI_ACPI_4_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')\r
\r
///\r
-/// "SPCR" Serial Port Concole Redirection Table\r
+/// "SPCR" Serial Port Console Redirection Table\r
///\r
#define EFI_ACPI_4_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\r
\r
#include <IndustryStandard/Acpi40.h>\r
\r
//\r
-// Define for Desriptor\r
+// Define for Descriptor\r
//\r
#define ACPI_SMALL_FIXED_DMA_DESCRIPTOR_NAME 0x0A\r
#define ACPI_LARGE_GPIO_CONNECTION_DESCRIPTOR_NAME 0x0C\r
///\r
UINT64 ExitBootServicesEntry;\r
///\r
- /// Timer value logged at the point just prior towhen the OS loader gaining\r
+ /// Timer value logged at the point just prior to when the OS loader gaining\r
/// control back from calls the ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
#define EFI_ACPI_5_0_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')\r
\r
///\r
-/// "SPCR" Serial Port Concole Redirection Table\r
+/// "SPCR" Serial Port Console Redirection Table\r
///\r
#define EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\r
\r
///\r
UINT64 ExitBootServicesEntry;\r
///\r
- /// Timer value logged at the point just prior towhen the OS loader gaining\r
+ /// Timer value logged at the point just prior to when the OS loader gaining\r
/// control back from calls the ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
#define EFI_ACPI_5_1_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')\r
\r
///\r
-/// "SPCR" Serial Port Concole Redirection Table\r
+/// "SPCR" Serial Port Console Redirection Table\r
///\r
#define EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\r
\r
///\r
UINT64 ExitBootServicesEntry;\r
///\r
- /// Timer value logged at the point just prior towhen the OS loader gaining\r
+ /// Timer value logged at the point just prior to when the OS loader gaining\r
/// control back from calls the ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
#define EFI_ACPI_6_0_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')\r
\r
///\r
-/// "SPCR" Serial Port Concole Redirection Table\r
+/// "SPCR" Serial Port Console Redirection Table\r
///\r
#define EFI_ACPI_6_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\r
\r
///\r
UINT64 ExitBootServicesEntry;\r
///\r
- /// Timer value logged at the point just prior towhen the OS loader gaining\r
+ /// Timer value logged at the point just prior to when the OS loader gaining\r
/// control back from calls the ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
#define EFI_ACPI_6_1_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')\r
\r
///\r
-/// "SPCR" Serial Port Concole Redirection Table\r
+/// "SPCR" Serial Port Console Redirection Table\r
///\r
#define EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\r
\r
///\r
UINT64 ExitBootServicesEntry;\r
///\r
- /// Timer value logged at the point just prior towhen the OS loader gaining\r
+ /// Timer value logged at the point just prior to when the OS loader gaining\r
/// control back from calls the ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_REVISION 0x01\r
\r
///\r
-/// Secure Devcice types\r
+/// Secure Device types\r
///\r
#define EFI_ACPI_6_2_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01\r
#define EFI_ACPI_6_2_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00\r
\r
///\r
-/// Secure Devcice flags\r
+/// Secure Device flags\r
///\r
#define EFI_ACPI_6_2_SDEV_FLAG_ALLOW_HANDOFF BIT0\r
\r
#define EFI_ACPI_6_2_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')\r
\r
///\r
-/// "SPCR" Serial Port Concole Redirection Table\r
+/// "SPCR" Serial Port Console Redirection Table\r
///\r
#define EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\r
\r
//\r
// ATA Packet Command Code\r
//\r
-#define ATA_CMD_FORMAT_UNIT 0x04 ///< defined in ATAPI Removable Rewritable Media Devcies\r
+#define ATA_CMD_FORMAT_UNIT 0x04 ///< defined in ATAPI Removable Rewritable Media Devices\r
#define ATA_CMD_SOFT_RESET 0x08 ///< defined from ATA-3\r
#define ATA_CMD_PACKET 0xA0 ///< defined from ATA-3\r
#define ATA_CMD_IDENTIFY_DEVICE 0xA1 ///< defined from ATA-3\r
#define ATA_CMD_SERVICE 0xA2 ///< defined from ATA-3\r
#define ATA_CMD_TEST_UNIT_READY 0x00 ///< defined from ATA-1\r
#define ATA_CMD_REQUEST_SENSE 0x03 ///< defined from ATA-4\r
-#define ATA_CMD_INQUIRY 0x12 ///< defined in ATAPI Removable Rewritable Media Devcies\r
-#define ATA_CMD_READ_FORMAT_CAPACITY 0x23 ///< defined in ATAPI Removable Rewritable Media Devcies\r
-#define ATA_CMD_READ_CAPACITY 0x25 ///< defined in ATAPI Removable Rewritable Media Devcies\r
-#define ATA_CMD_READ_10 0x28 ///< defined in ATAPI Removable Rewritable Media Devcies\r
-#define ATA_CMD_WRITE_10 0x2A ///< defined in ATAPI Removable Rewritable Media Devcies\r
-#define ATA_CMD_ATAPI_SEEK 0x2B ///< defined in ATAPI Removable Rewritable Media Devcies\r
-#define ATA_CMD_WRITE_AND_VERIFY 0x2E ///< defined in ATAPI Removable Rewritable Media Devcies\r
-#define ATA_CMD_VERIFY 0x2F ///< defined in ATAPI Removable Rewritable Media Devcies\r
-#define ATA_CMD_READ_12 0xA8 ///< defined in ATAPI Removable Rewritable Media Devcies\r
-#define ATA_CMD_WRITE_12 0xAA ///< defined in ATAPI Removable Rewritable Media Devcies\r
-#define ATA_CMD_START_STOP_UNIT 0x1B ///< defined in ATAPI Removable Rewritable Media Devcies\r
-#define ATA_CMD_PREVENT_ALLOW_MEDIA_REMOVAL 0x1E ///< defined in ATAPI Removable Rewritable Media Devcies\r
-#define ATA_CMD_MODE_SELECT 0x55 ///< defined in ATAPI Removable Rewritable Media Devcies\r
-\r
-#define ATA_CMD_MODE_SENSE 0x5A ///< defined in ATAPI Removable Rewritable Media Devcies\r
- #define ATA_PAGE_CODE_READ_WRITE_ERROR 0x01 ///< defined in ATAPI Removable Rewritable Media Devcies\r
- #define ATA_PAGE_CODE_CACHING_PAGE 0x08 ///< defined in ATAPI Removable Rewritable Media Devcies\r
- #define ATA_PAGE_CODE_REMOVABLE_BLOCK_CAPABILITIES 0x1B ///< defined in ATAPI Removable Rewritable Media Devcies\r
- #define ATA_PAGE_CODE_TIMER_PROTECT_PAGE 0x1C ///< defined in ATAPI Removable Rewritable Media Devcies\r
- #define ATA_PAGE_CODE_RETURN_ALL_PAGES 0x3F ///< defined in ATAPI Removable Rewritable Media Devcies\r
+#define ATA_CMD_INQUIRY 0x12 ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_READ_FORMAT_CAPACITY 0x23 ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_READ_CAPACITY 0x25 ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_READ_10 0x28 ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_WRITE_10 0x2A ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_ATAPI_SEEK 0x2B ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_WRITE_AND_VERIFY 0x2E ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_VERIFY 0x2F ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_READ_12 0xA8 ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_WRITE_12 0xAA ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_START_STOP_UNIT 0x1B ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_PREVENT_ALLOW_MEDIA_REMOVAL 0x1E ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_MODE_SELECT 0x55 ///< defined in ATAPI Removable Rewritable Media Devices\r
+\r
+#define ATA_CMD_MODE_SENSE 0x5A ///< defined in ATAPI Removable Rewritable Media Devices\r
+ #define ATA_PAGE_CODE_READ_WRITE_ERROR 0x01 ///< defined in ATAPI Removable Rewritable Media Devices\r
+ #define ATA_PAGE_CODE_CACHING_PAGE 0x08 ///< defined in ATAPI Removable Rewritable Media Devices\r
+ #define ATA_PAGE_CODE_REMOVABLE_BLOCK_CAPABILITIES 0x1B ///< defined in ATAPI Removable Rewritable Media Devices\r
+ #define ATA_PAGE_CODE_TIMER_PROTECT_PAGE 0x1C ///< defined in ATAPI Removable Rewritable Media Devices\r
+ #define ATA_PAGE_CODE_RETURN_ALL_PAGES 0x3F ///< defined in ATAPI Removable Rewritable Media Devices\r
\r
#define ATA_CMD_GET_CONFIGURATION 0x46 ///< defined in ATAPI Multimedia Devices\r
#define ATA_GCCD_RT_FIELD_VALUE_ALL 0x00 ///< defined in ATAPI Multimedia Devices\r
/** @file\r
ElTorito Partitions Format Definition.\r
- This file includes some defintions from\r
+ This file includes some definitions from\r
1. "El Torito" Bootable CD-ROM Format Specification, Version 1.0.\r
2. Volume and File Structure of CDROM for Information Interchange,\r
Standard ECMA-119. (IS0 9660)\r
} BootRecordVolume;\r
\r
///\r
- /// Primary Volumn Descriptor, defined in ISO 9660.\r
+ /// Primary Volume Descriptor, defined in ISO 9660.\r
///\r
struct {\r
UINT8 Type;\r
UINT8 MinPerfW8B52M; // Minimum Write Performance for 8bit at 52MHz [210]\r
UINT8 Reserved17; // Reserved [211]\r
UINT8 SecCount[4]; // Sector Count [215:212]\r
- UINT8 SleepNotificationTime; // Sleep Notification Timout [216]\r
+ UINT8 SleepNotificationTime; // Sleep Notification Timeout [216]\r
UINT8 SATimeout; // Sleep/awake timeout [217]\r
UINT8 ProductionStateAwarenessTimeout; // Production state awareness timeout [218]\r
UINT8 SCVccq; // Sleep current (VCCQ) [219]\r
//\r
\r
//\r
-// Definitions for Prepare for Discoveery command\r
+// Definitions for Prepare for Discovery command\r
//\r
#define IPMI_BRIDGE_PREPARE_FOR_DISCOVERY 0x10\r
\r
//\r
-// Constants and Structure definitions for "Prepare for Discoveery" command to follow here\r
+// Constants and Structure definitions for "Prepare for Discovery" command to follow here\r
//\r
\r
//\r
UINT32 Exlat; /* Exit Latency */\r
UINT8 Rrt:5; /* Relative Read Throughput */\r
UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */\r
- UINT8 Rrl:5; /* Relative Read Leatency */\r
+ UINT8 Rrl:5; /* Relative Read Latency */\r
UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */\r
UINT8 Rwt:5; /* Relative Write Throughput */\r
UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */\r
- UINT8 Rwl:5; /* Relative Write Leatency */\r
+ UINT8 Rwl:5; /* Relative Write Latency */\r
UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */\r
UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */\r
} NVME_PSDESCRIPTOR;\r
UINT16 Ssvid; /* PCI sub-system vendor ID */\r
UINT8 Sn[20]; /* Product serial number */\r
\r
- UINT8 Mn[40]; /* Proeduct model number */\r
+ UINT8 Mn[40]; /* Product model number */\r
UINT8 Fr[8]; /* Firmware Revision */\r
UINT8 Rab; /* Recommended Arbitration Burst */\r
UINT8 Ieee_oui[3]; /* Organization Unique Identifier */\r
//\r
typedef struct {\r
//\r
- // CDW 0, Common to all comnmands\r
+ // CDW 0, Common to all commands\r
//\r
UINT8 Opc; // Opcode\r
UINT8 Fuse:2; // Fused Operation\r
//\r
UINT8 AvailableSpareThreshold;\r
//\r
- // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer?s prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).\r
+ // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer's prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).\r
//\r
UINT8 PercentageUsed;\r
UINT8 Reserved1[26];\r
PCI Local Bus Specification, 2.2\r
PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
PC Card Standard, 8.0\r
- PCI Power Management Interface Specifiction, Revision 1.2\r
+ PCI Power Management Interface Specification, Revision 1.2\r
\r
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>\r
} PCI_TYPE_GENERIC;\r
\r
///\r
-/// CardBus Conroller Configuration Space,\r
+/// CardBus Controller Configuration Space,\r
/// Section 4.5.1, PC Card Standard. 8.0\r
///\r
typedef struct {\r
- UINT32 CardBusSocketReg; ///< Cardus Socket/ExCA Base\r
+ UINT32 CardBusSocketReg; ///< Cardbus Socket/ExCA Base\r
UINT8 Cap_Ptr;\r
UINT8 Reserved;\r
UINT16 SecondaryStatus; ///< Secondary Status\r
#define PCI_IF_8259_PIC 0x00\r
#define PCI_IF_ISA_PIC 0x01\r
#define PCI_IF_EISA_PIC 0x02\r
-#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.\r
+#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory.\r
#define PCI_IF_APIC_CONTROLLER2 0x20\r
#define PCI_SUBCLASS_DMA 0x01\r
#define PCI_IF_8237_DMA 0x00\r
#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r
\r
///\r
-/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,\r
+/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecture Specification,\r
///\r
#define PCI_BRIDGE_ROMBAR 0x38\r
\r
\r
///\r
/// PMC - Power Management Capabilities\r
-/// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2\r
+/// Section 3.2.3, PCI Power Management Interface Specification, Revision 1.2\r
///\r
typedef union {\r
struct {\r
\r
///\r
/// PMCSR - Power Management Control/Status\r
-/// Section 3.2.4, PCI Power Management Interface Specifiction, Revision 1.2\r
+/// Section 3.2.4, PCI Power Management Interface Specification, Revision 1.2\r
///\r
typedef union {\r
struct {\r
\r
///\r
/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions\r
-/// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2\r
+/// Section 3.2.5, PCI Power Management Interface Specification, Revision 1.2\r
///\r
typedef union {\r
struct {\r
\r
///\r
/// Power Management Register Block Definition\r
-/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2\r
+/// Section 3.2, PCI Power Management Interface Specification, Revision 1.2\r
///\r
typedef struct {\r
EFI_PCI_CAPABILITY_HDR Hdr;\r
\r
///\r
/// Slot Numbering Capabilities Register\r
-/// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2\r
+/// Section 3.2.6, PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
///\r
typedef struct {\r
EFI_PCI_CAPABILITY_HDR Hdr;\r
//\r
#define EFI_IMAGE_FILE_RELOCS_STRIPPED BIT0 ///< 0x0001 Relocation info stripped from file.\r
#define EFI_IMAGE_FILE_EXECUTABLE_IMAGE BIT1 ///< 0x0002 File is executable (i.e. no unresolved externel references).\r
-#define EFI_IMAGE_FILE_LINE_NUMS_STRIPPED BIT2 ///< 0x0004 Line nunbers stripped from file.\r
+#define EFI_IMAGE_FILE_LINE_NUMS_STRIPPED BIT2 ///< 0x0004 Line numbers stripped from file.\r
#define EFI_IMAGE_FILE_LOCAL_SYMS_STRIPPED BIT3 ///< 0x0008 Local symbols stripped from file.\r
#define EFI_IMAGE_FILE_BYTES_REVERSED_LO BIT7 ///< 0x0080 Bytes of machine word are reversed.\r
#define EFI_IMAGE_FILE_32BIT_MACHINE BIT8 ///< 0x0100 32 bit word machine.\r
#define EFI_SCSI_OP_SEND_VOL_TAG 0xb6\r
\r
//\r
-// Additional commands for Communition Devices\r
+// Additional commands for Communication Devices\r
//\r
#define EFI_SCSI_OP_GET_MESSAGE6 0x08\r
#define EFI_SCSI_OP_GET_MESSAGE10 0x28\r
/** @file\r
- This file declares the SMBus definitions defined in SmBus Specifciation V2.0\r
+ This file declares the SMBus definitions defined in SmBus Specification V2.0\r
and defined in PI1.0 specification volume 5.\r
\r
Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
\r
///\r
/// Part 2, section 5.12: TPM_MIGRATIONKEYAUTH\r
-/// decalared after section 10 to catch declaration of TPM_PUBKEY\r
+/// declared after section 10 to catch declaration of TPM_PUBKEY\r
///\r
/// Part 2 section 10.1: TPM_KEY_PARMS\r
/// [size_is(parmSize)] BYTE* parms;\r
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