+/** @file\r
+ SSDT for RhProxy Driver.\r
+\r
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+DefinitionBlock ("RHPX.aml", "SSDT", 1, "MSFT", "RHPROXY", 1)\r
+{\r
+ Scope (\_SB)\r
+ {\r
+ //\r
+ // Test peripheral device node for MinnowBoardMax\r
+ //\r
+ Device(RHPX)\r
+ {\r
+ Name(_HID, "MSFT8000")\r
+ Name(_CID, "MSFT8000")\r
+ Name(_UID, 1)\r
+\r
+ Name(_CRS, ResourceTemplate() \r
+ { \r
+ // Index 0 \r
+ SPISerialBus( // Pin 5, 7, 9 , 11 of JP1 for SIO_SPI\r
+ 1, // Device selection\r
+ PolarityLow, // Device selection polarity\r
+ FourWireMode, // wiremode\r
+ 8, // databit len\r
+ ControllerInitiated, // slave mode\r
+ 8000000, // Connection speed\r
+ ClockPolarityLow, // Clock polarity\r
+ ClockPhaseSecond, // clock phase\r
+ "\\_SB.SPI1", // ResourceSource: SPI bus controller name\r
+ 0, // ResourceSourceIndex\r
+ ResourceConsumer, // Resource usage\r
+ JSPI, // DescriptorName: creates name for offset of resource descriptor\r
+ ) // Vendor Data \r
+ \r
+ // Index 1 \r
+ I2CSerialBus( // Pin 13, 15 of JP1, for SIO_I2C5 (signal)\r
+ 0xFF, // SlaveAddress: bus address (TBD)\r
+ , // SlaveMode: default to ControllerInitiated\r
+ 400000, // ConnectionSpeed: in Hz\r
+ , // Addressing Mode: default to 7 bit\r
+ "\\_SB.I2C6", // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I2C5(0-based) is reported as ACPI I2C6(1-based))\r
+ ,\r
+ ,\r
+ JI2C, // Descriptor Name: creates name for offset of resource descriptor\r
+ ) // VendorData\r
+ \r
+ // Index 2\r
+ UARTSerialBus( // Pin 17, 19 of JP1, for SIO_UART2\r
+ 115200, // InitialBaudRate: in bits ber second\r
+ , // BitsPerByte: default to 8 bits\r
+ , // StopBits: Defaults to one bit\r
+ 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled\r
+ , // IsBigEndian: default to LittleEndian\r
+ , // Parity: Defaults to no parity\r
+ , // FlowControl: Defaults to no flow control\r
+ 32, // ReceiveBufferSize\r
+ 32, // TransmitBufferSize\r
+ "\\_SB.URT2", // ResourceSource: UART bus controller name\r
+ ,\r
+ ,\r
+ UAR2, // DescriptorName: creates name for offset of resource descriptor\r
+ ) \r
+ \r
+ // Index 3\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {0} // Pin 21 of JP1 (GPIO_S5[00])\r
+ // Index 4\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {0} \r
+ \r
+ // Index 5\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {1} // Pin 23 of JP1 (GPIO_S5[01])\r
+ // Index 6\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {1}\r
+ \r
+ // Index 7\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {2} // Pin 25 of JP1 (GPIO_S5[02])\r
+ // Index 8\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {2} \r
+ \r
+ // Index 9\r
+ UARTSerialBus( // Pin 6, 8, 10, 12 of JP1, for SIO_UART1\r
+ 115200, // InitialBaudRate: in bits ber second\r
+ , // BitsPerByte: default to 8 bits\r
+ , // StopBits: Defaults to one bit\r
+ 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled\r
+ , // IsBigEndian: default to LittleEndian\r
+ , // Parity: Defaults to no parity\r
+ FlowControlHardware, // FlowControl: Defaults to no flow control\r
+ 32, // ReceiveBufferSize\r
+ 32, // TransmitBufferSize\r
+ "\\_SB.URT1", // ResourceSource: UART bus controller name\r
+ ,\r
+ ,\r
+ UAR1, // DescriptorName: creates name for offset of resource descriptor\r
+ ) \r
+ \r
+ // Index 10\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {62} // Pin 14 of JP1 (GPIO_SC[62])\r
+ // Index 11\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {62} \r
+\r
+ // Index 12\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {63} // Pin 16 of JP1 (GPIO_SC[63])\r
+ // Index 13\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {63} \r
+ \r
+ // Index 14\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {65} // Pin 18 of JP1 (GPIO_SC[65])\r
+ // Index 15\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {65} \r
+ \r
+ // Index 16\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {64} // Pin 20 of JP1 (GPIO_SC[64])\r
+ // Index 17\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {64} \r
+ \r
+ // Index 18\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {94} // Pin 22 of JP1 (GPIO_SC[94])\r
+ // Index 19\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {94} \r
+ \r
+ // Index 20\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {95} // Pin 24 of JP1 (GPIO_SC[95])\r
+ // Index 21\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {95} \r
+ \r
+ // Index 22\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {54} // Pin 26 of JP1 (GPIO_SC[54])\r
+ // Index 23\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {54}\r
+ })\r
+ \r
+ Name(_DSD, Package() \r
+ {\r
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),\r
+ Package() \r
+ {\r
+ // SPI Mapping\r
+ Package(2) { "bus-SPI-SPI0", Package() { 0 }},\r
+\r
+ // TODO: Intel will need to provide the right value for SPI0 properties\r
+ Package(2) { "SPI0-MinClockInHz", 100 },\r
+ Package(2) { "SPI0-MaxClockInHz", 8000000 },\r
+ // SupportedDataBitLengths takes a list of support data bit length\r
+ // Example : Package(2) { "SPI0-SupportedDataBitLengths", Package() { 8, 7, 16 }},\r
+ Package(2) { "SPI0-SupportedDataBitLengths", Package() { 8 }},\r
+ // I2C Mapping\r
+ Package(2) { "bus-I2C-I2C5", Package() { 1 }},\r
+ // UART Mapping\r
+ Package(2) { "bus-UART-UART2", Package() { 2 }},\r
+ Package(2) { "bus-UART-UART1", Package() { 9 }},\r
+ }\r
+ })\r
+ }\r
+ }\r
+}
\ No newline at end of file
projects / mirror_edk2.git / commitdiff