}\r
}\r
\r
- if ((*IoSize == 0) || (*Mmio32Size == 0)) {\r
- DEBUG ((\r
- DEBUG_ERROR,\r
- "%a: %a space empty\n",\r
- __FUNCTION__,\r
- (*IoSize == 0) ? "IO" : "MMIO32"\r
- ));\r
+ if (*Mmio32Size == 0) {\r
+ DEBUG ((DEBUG_ERROR, "%a: MMIO32 space empty\n", __FUNCTION__));\r
return EFI_PROTOCOL_ERROR;\r
}\r
\r
return Status;\r
}\r
\r
- //\r
- // Map the MMIO window that provides I/O access - the PCI host bridge code\r
- // is not aware of this translation and so it will only map the I/O view\r
- // in the GCD I/O map.\r
- //\r
- Status = MapGcdMmioSpace (*IoBase + IoTranslation, *IoSize);\r
- ASSERT_EFI_ERROR (Status);\r
+ if (*IoSize != 0) {\r
+ //\r
+ // Map the MMIO window that provides I/O access - the PCI host bridge code\r
+ // is not aware of this translation and so it will only map the I/O view\r
+ // in the GCD I/O map.\r
+ //\r
+ Status = MapGcdMmioSpace (*IoBase + IoTranslation, *IoSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
\r
return Status;\r
}\r
\r
AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;\r
\r
- Io.Base = IoBase;\r
- Io.Limit = IoBase + IoSize - 1;\r
+ if (IoSize != 0) {\r
+ Io.Base = IoBase;\r
+ Io.Limit = IoBase + IoSize - 1;\r
+ } else {\r
+ Io.Base = MAX_UINT64;\r
+ Io.Limit = 0;\r
+ }\r
+\r
Mem.Base = Mmio32Base;\r
Mem.Limit = Mmio32Base + Mmio32Size - 1;\r
\r
- if (sizeof (UINTN) == sizeof (UINT64)) {\r
- MemAbove4G.Base = Mmio64Base;\r
- MemAbove4G.Limit = Mmio64Base + Mmio64Size - 1;\r
- if (Mmio64Size > 0) {\r
- AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;\r
- }\r
+ if ((sizeof (UINTN) == sizeof (UINT64)) && (Mmio64Size != 0)) {\r
+ MemAbove4G.Base = Mmio64Base;\r
+ MemAbove4G.Limit = Mmio64Base + Mmio64Size - 1;\r
+ AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;\r
} else {\r
//\r
// UEFI mandates a 1:1 virtual-to-physical mapping, so on a 32-bit\r