Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))\r
ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr)\r
\r
+.equ MSR_IA32_MISC_ENABLE, 0x1A0\r
.equ MSR_EFER, 0xc0000080\r
.equ MSR_EFER_XD, 0x800\r
\r
call eax\r
add esp, 4\r
\r
- mov eax, mXdSupported\r
+ mov eax, offset mXdSupported\r
mov al, [eax]\r
cmp al, 0\r
jz @f\r
rdmsr\r
orw $MSR_EFER_XD,%ax # enable NXE\r
wrmsr\r
- jmp @NxeDone\r
+ jmp NxeDone\r
SkipNxe:\r
subl $8, %esp\r
NxeDone:\r
\r
add rsp, 200h\r
\r
- mov rax, ASM_PFX(mXdSupported)\r
+ mov rax, offset ASM_PFX(mXdSupported)\r
mov al, [rax]\r
cmp al, 0\r
jz @f\r