]> git.proxmox.com Git - mirror_edk2.git/commitdiff
UefiCpuPkg/PiSmmCpuDxeSmm: Fix .S & .asm build failure
authorFeng Tian <feng.tian@intel.com>
Thu, 15 Dec 2016 05:25:30 +0000 (13:25 +0800)
committerFeng Tian <feng.tian@intel.com>
Fri, 16 Dec 2016 00:27:59 +0000 (08:27 +0800)
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm

index 378e06520c831d1dc059784380231290b7ed0bfe..62f1697eface3cd0303dca7128db777e7b62820b 100644 (file)
@@ -28,6 +28,7 @@ ASM_GLOBAL  ASM_PFX(mXdSupported)
 ASM_GLOBAL  ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))\r
 ASM_GLOBAL  ASM_PFX(gSmiHandlerIdtr)\r
 \r
+.equ            MSR_IA32_MISC_ENABLE, 0x1A0\r
 .equ            MSR_EFER, 0xc0000080\r
 .equ            MSR_EFER_XD, 0x800\r
 \r
index a4f4dcbda6d840904ec78cc06efb1f8bd052ef0e..8296f36d26381fef25dbd83f39e8c35cdac72d48 100644 (file)
@@ -202,7 +202,7 @@ _SmiHandler PROC
     call    eax\r
     add     esp, 4\r
 \r
-    mov     eax, mXdSupported\r
+    mov     eax, offset mXdSupported\r
     mov     al, [eax]\r
     cmp     al, 0\r
     jz      @f\r
index f4761b01608c3710e42706361869a60f83056706..600d8623cd2690b6526d46c0d9e1823f170fb528 100644 (file)
@@ -158,7 +158,7 @@ L13:
     rdmsr\r
     orw     $MSR_EFER_XD,%ax            # enable NXE\r
     wrmsr\r
-    jmp     @NxeDone\r
+    jmp     NxeDone\r
 SkipNxe:\r
     subl    $8, %esp\r
 NxeDone:\r
index e2fcb6f0d590db487443844e792bc323f8c753de..c74f82aac8e01e9745ff92539775e184a338636a 100644 (file)
@@ -222,7 +222,7 @@ _SmiHandler:
 \r
     add     rsp, 200h\r
 \r
-    mov     rax, ASM_PFX(mXdSupported)\r
+    mov     rax, offset ASM_PFX(mXdSupported)\r
     mov     al, [rax]\r
     cmp     al, 0\r
     jz      @f\r