PI 1.1 SMM Feature Check-in

1. Add SmmServicesTableLib library class/instance.
2. Add SmmIoLibCpuIo/SmmPciLibPciRootBridgeIo library instance.
3. Update some library INF to support SMM_CORE module type.
4. Update dec/dsc to include new modules.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9590 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdePkg/Include/Guid/EventGroup.h b/MdePkg/Include/Guid/EventGroup.h
index d601c0519a0ec2f3dd1ea26e435f8b5fcdcc40cf..47671f756536554a5847e48c36a6ab0cde57509c 100644 (file)
--- a/MdePkg/Include/Guid/EventGroup.h
+++ b/MdePkg/Include/Guid/EventGroup.h
@@ -1,7 +1,7 @@
 /** @file\r
 /** @file\r

-  GUIDs for gBS->CreateEventEx Event Groups. Defined in UEFI spec 2.0.\r
+  GUIDs for gBS->CreateEventEx Event Groups. Defined in UEFI spec 2.0 and PI 1.2.\r

 \r
 \r

-  Copyright (c) 2006, Intel Corporation                                                         \r
+  Copyright (c) 2006 - 2009, Intel Corporation                                                         \r

   All rights reserved. This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
   which accompanies this distribution.  The full text of the license may be found at        \r
   All rights reserved. This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
   which accompanies this distribution.  The full text of the license may be found at        \r


@@ -39,5 +39,9 @@ extern EFI_GUID gEfiEventMemoryMapChangeGuid;
 \r
 extern EFI_GUID gEfiEventReadyToBootGuid;\r
 \r
 \r
 extern EFI_GUID gEfiEventReadyToBootGuid;\r
 \r

+#define EFI_EVENT_GROUP_DXE_DISPATCH \\r
+  { 0x7081e22f, 0xcac6, 0x4053, { 0x94, 0x68, 0x67, 0x57, 0x82, 0xcf, 0x88, 0xe5 }}\r
+\r
+extern EFI_GUID gEfiEventDxeDispatchGuid;\r

 \r
 #endif\r
 \r
 #endif\r

diff --git a/MdePkg/Include/Library/SmmServicesTableLib.h b/MdePkg/Include/Library/SmmServicesTableLib.h
new file mode 100644 (file)
index 0000000..b840ddf
--- /dev/null
+++ b/MdePkg/Include/Library/SmmServicesTableLib.h
@@ -0,0 +1,43 @@
+/** @file\r
+  Provides a service to retrieve a pointer to the SMM Services Table.\r
+  Only available to SMM module types.\r
+\r
+Copyright (c) 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __SMM_SERVICES_TABLE_LIB_H__\r
+#define __SMM_SERVICES_TABLE_LIB_H__\r
+\r
+#include <PiSmm.h>\r
+\r
+///\r
+/// Cache pointer to the SMM Services Table\r
+///\r
+extern EFI_SMM_SYSTEM_TABLE2   *gSmst;\r
+\r
+/**\r
+  This function allows the caller to determine if the driver is executing in \r
+  System Management Mode(SMM).\r
+\r
+  This function returns TRUE if the driver is executing in SMM and FALSE if the \r
+  driver is not executing in SMM.\r
+\r
+  @retval  TRUE  The driver is executing in System Management Mode (SMM).\r
+  @retval  FALSE The driver is not executing in System Management Mode (SMM). \r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+InSmm (\r
+  VOID\r
+  );\r
+\r
+#endif\r

diff --git a/MdePkg/Include/PiSmm.h b/MdePkg/Include/PiSmm.h
new file mode 100644 (file)
index 0000000..2e9c84c
--- /dev/null
+++ b/MdePkg/Include/PiSmm.h
@@ -0,0 +1,25 @@
+/** @file\r
+\r
+  Root include file for Mde Package SMM modules.\r
+\r
+Copyright (c) 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __PI_SMM_H__\r
+#define __PI_SMM_H__\r
+\r
+#include <Uefi/UefiBaseType.h>\r
+#include <Uefi/UefiSpec.h>\r
+\r
+#include <Pi/PiSmmCis.h>\r
+\r
+#endif\r
+\r

diff --git a/MdePkg/Library/DxePcdLib/DxePcdLib.inf b/MdePkg/Library/DxePcdLib/DxePcdLib.inf
index 2958ed0a7cf723a554223b9f2dc51e5686512dbc..78b1a7b34abc0b98c7096c98b92048051c5e909c 100644 (file)
--- a/MdePkg/Library/DxePcdLib/DxePcdLib.inf
+++ b/MdePkg/Library/DxePcdLib/DxePcdLib.inf
@@ -31,7 +31,7 @@
   FILE_GUID                      = af97eb89-4cc6-45f8-a514-ca025b346480\r
   MODULE_TYPE                    = DXE_DRIVER\r
   VERSION_STRING                 = 1.0\r
   FILE_GUID                      = af97eb89-4cc6-45f8-a514-ca025b346480\r
   MODULE_TYPE                    = DXE_DRIVER\r
   VERSION_STRING                 = 1.0\r

-  LIBRARY_CLASS                  = PcdLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER \r
+  LIBRARY_CLASS                  = PcdLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER SMM_CORE UEFI_APPLICATION UEFI_DRIVER \r

   CONSTRUCTOR                    = PcdLibConstructor\r
 \r
 #\r
   CONSTRUCTOR                    = PcdLibConstructor\r
 \r
 #\r

diff --git a/MdePkg/Library/SmmIoLibCpuIo/IoHighLevel.c b/MdePkg/Library/SmmIoLibCpuIo/IoHighLevel.c
new file mode 100644 (file)
index 0000000..72ea425
--- /dev/null
+++ b/MdePkg/Library/SmmIoLibCpuIo/IoHighLevel.c
@@ -0,0 +1,2275 @@
+/** @file\r
+  High-level Io/Mmio functions.\r
+\r
+  All assertions for bit field operations are handled bit field functions in the\r
+  Base Library.\r
+\r
+  Copyright (c) 2009, Intel Corporation<BR>\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+  Module Name:  IoHighLevel.c\r
+\r
+  The following IoLib instances share the same version of this file:\r
+\r
+    BaseIoLibIntrinsic\r
+    DxeIoLibCpuIo\r
+    PeiIoLibCpuIo\r
+    SmmIoLibCpuIo\r
+**/\r
+\r
+\r
+#include "SmmCpuIoLibInternal.h"\r
+\r
+/**\r
+  Reads an 8-bit I/O port, performs a bitwise OR, and writes the\r
+  result back to the 8-bit I/O port.\r
+\r
+  Reads the 8-bit I/O port specified by Port, performs a bitwise OR\r
+  between the read result and the value specified by OrData, and writes the\r
+  result to the 8-bit I/O port specified by Port. The value written to the I/O\r
+  port is returned. This function must guarantee that all I/O read and write\r
+  operations are serialized.\r
+\r
+  If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port    The I/O port to write.\r
+  @param  OrData  The value to OR with the read value from the I/O port.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoOr8 (\r
+  IN      UINTN                     Port,\r
+  IN      UINT8                     OrData\r
+  )\r
+{\r
+  return IoWrite8 (Port, (UINT8) (IoRead8 (Port) | OrData));\r
+}\r
+\r
+/**\r
+  Reads an 8-bit I/O port, performs a bitwise AND, and writes the result back\r
+  to the 8-bit I/O port.\r
+\r
+  Reads the 8-bit I/O port specified by Port, performs a bitwise AND between\r
+  the read result and the value specified by AndData, and writes the result to\r
+  the 8-bit I/O port specified by Port. The value written to the I/O port is\r
+  returned. This function must guarantee that all I/O read and write operations\r
+  are serialized.\r
+\r
+  If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port    The I/O port to write.\r
+  @param  AndData The value to AND with the read value from the I/O port.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoAnd8 (\r
+  IN      UINTN                     Port,\r
+  IN      UINT8                     AndData\r
+  )\r
+{\r
+  return IoWrite8 (Port, (UINT8) (IoRead8 (Port) & AndData));\r
+}\r
+\r
+/**\r
+  Reads an 8-bit I/O port, performs a bitwise AND followed by a bitwise\r
+  inclusive OR, and writes the result back to the 8-bit I/O port.\r
+\r
+  Reads the 8-bit I/O port specified by Port, performs a bitwise AND between\r
+  the read result and the value specified by AndData, performs a bitwise OR\r
+  between the result of the AND operation and the value specified by OrData,\r
+  and writes the result to the 8-bit I/O port specified by Port. The value\r
+  written to the I/O port is returned. This function must guarantee that all\r
+  I/O read and write operations are serialized.\r
+\r
+  If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port    The I/O port to write.\r
+  @param  AndData The value to AND with the read value from the I/O port.\r
+  @param  OrData  The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoAndThenOr8 (\r
+  IN      UINTN                     Port,\r
+  IN      UINT8                     AndData,\r
+  IN      UINT8                     OrData\r
+  )\r
+{\r
+  return IoWrite8 (Port, (UINT8) ((IoRead8 (Port) & AndData) | OrData));\r
+}\r
+\r
+/**\r
+  Reads a bit field of an I/O register.\r
+\r
+  Reads the bit field in an 8-bit I/O register. The bit field is specified by\r
+  the StartBit and the EndBit. The value of the bit field is returned.\r
+\r
+  If 8-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 7, then ASSERT().\r
+  If EndBit is greater than 7, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to read.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..7.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoBitFieldRead8 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit\r
+  )\r
+{\r
+  return BitFieldRead8 (IoRead8 (Port), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+  Writes a bit field to an I/O register.\r
+\r
+  Writes Value to the bit field of the I/O register. The bit field is specified\r
+  by the StartBit and the EndBit. All other bits in the destination I/O\r
+  register are preserved. The value written to the I/O port is returned. Extra\r
+  left bits in Value are stripped.\r
+\r
+  If 8-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 7, then ASSERT().\r
+  If EndBit is greater than 7, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  Value     New value of the bit field.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoBitFieldWrite8 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT8                     Value\r
+  )\r
+{\r
+  return IoWrite8 (\r
+           Port,\r
+           BitFieldWrite8 (IoRead8 (Port), StartBit, EndBit, Value)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in an 8-bit port, performs a bitwise OR, and writes the\r
+  result back to the bit field in the 8-bit port.\r
+\r
+  Reads the 8-bit I/O port specified by Port, performs a bitwise OR\r
+  between the read result and the value specified by OrData, and writes the\r
+  result to the 8-bit I/O port specified by Port. The value written to the I/O\r
+  port is returned. This function must guarantee that all I/O read and write\r
+  operations are serialized. Extra left bits in OrData are stripped.\r
+\r
+  If 8-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 7, then ASSERT().\r
+  If EndBit is greater than 7, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  OrData    The value to OR with the read value from the I/O port.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoBitFieldOr8 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT8                     OrData\r
+  )\r
+{\r
+  return IoWrite8 (\r
+           Port,\r
+           BitFieldOr8 (IoRead8 (Port), StartBit, EndBit, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in an 8-bit port, performs a bitwise AND, and writes the\r
+  result back to the bit field in the 8-bit port.\r
+\r
+  Reads the 8-bit I/O port specified by Port, performs a bitwise AND between\r
+  the read result and the value specified by AndData, and writes the result to\r
+  the 8-bit I/O port specified by Port. The value written to the I/O port is\r
+  returned. This function must guarantee that all I/O read and write operations\r
+  are serialized. Extra left bits in AndData are stripped.\r
+\r
+  If 8-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 7, then ASSERT().\r
+  If EndBit is greater than 7, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  AndData   The value to AND with the read value from the I/O port.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoBitFieldAnd8 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT8                     AndData\r
+  )\r
+{\r
+  return IoWrite8 (\r
+           Port,\r
+           BitFieldAnd8 (IoRead8 (Port), StartBit, EndBit, AndData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
+  bitwise OR, and writes the result back to the bit field in the\r
+  8-bit port.\r
+\r
+  Reads the 8-bit I/O port specified by Port, performs a bitwise AND followed\r
+  by a bitwise OR between the read result and the value specified by\r
+  AndData, and writes the result to the 8-bit I/O port specified by Port. The\r
+  value written to the I/O port is returned. This function must guarantee that\r
+  all I/O read and write operations are serialized. Extra left bits in both\r
+  AndData and OrData are stripped.\r
+\r
+  If 8-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 7, then ASSERT().\r
+  If EndBit is greater than 7, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  AndData   The value to AND with the read value from the I/O port.\r
+  @param  OrData    The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoBitFieldAndThenOr8 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT8                     AndData,\r
+  IN      UINT8                     OrData\r
+  )\r
+{\r
+  return IoWrite8 (\r
+           Port,\r
+           BitFieldAndThenOr8 (IoRead8 (Port), StartBit, EndBit, AndData, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a 16-bit I/O port, performs a bitwise OR, and writes the\r
+  result back to the 16-bit I/O port.\r
+\r
+  Reads the 16-bit I/O port specified by Port, performs a bitwise OR\r
+  between the read result and the value specified by OrData, and writes the\r
+  result to the 16-bit I/O port specified by Port. The value written to the I/O\r
+  port is returned. This function must guarantee that all I/O read and write\r
+  operations are serialized.\r
+\r
+  If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port    The I/O port to write.\r
+  @param  OrData  The value to OR with the read value from the I/O port.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoOr16 (\r
+  IN      UINTN                     Port,\r
+  IN      UINT16                    OrData\r
+  )\r
+{\r
+  return IoWrite16 (Port, (UINT16) (IoRead16 (Port) | OrData));\r
+}\r
+\r
+/**\r
+  Reads a 16-bit I/O port, performs a bitwise AND, and writes the result back\r
+  to the 16-bit I/O port.\r
+\r
+  Reads the 16-bit I/O port specified by Port, performs a bitwise AND between\r
+  the read result and the value specified by AndData, and writes the result to\r
+  the 16-bit I/O port specified by Port. The value written to the I/O port is\r
+  returned. This function must guarantee that all I/O read and write operations\r
+  are serialized.\r
+\r
+  If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port    The I/O port to write.\r
+  @param  AndData The value to AND with the read value from the I/O port.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoAnd16 (\r
+  IN      UINTN                     Port,\r
+  IN      UINT16                    AndData\r
+  )\r
+{\r
+  return IoWrite16 (Port, (UINT16) (IoRead16 (Port) & AndData));\r
+}\r
+\r
+/**\r
+  Reads a 16-bit I/O port, performs a bitwise AND followed by a bitwise\r
+  inclusive OR, and writes the result back to the 16-bit I/O port.\r
+\r
+  Reads the 16-bit I/O port specified by Port, performs a bitwise AND between\r
+  the read result and the value specified by AndData, performs a bitwise OR\r
+  between the result of the AND operation and the value specified by OrData,\r
+  and writes the result to the 16-bit I/O port specified by Port. The value\r
+  written to the I/O port is returned. This function must guarantee that all\r
+  I/O read and write operations are serialized.\r
+\r
+  If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port    The I/O port to write.\r
+  @param  AndData The value to AND with the read value from the I/O port.\r
+  @param  OrData  The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoAndThenOr16 (\r
+  IN      UINTN                     Port,\r
+  IN      UINT16                    AndData,\r
+  IN      UINT16                    OrData\r
+  )\r
+{\r
+  return IoWrite16 (Port, (UINT16) ((IoRead16 (Port) & AndData) | OrData));\r
+}\r
+\r
+/**\r
+  Reads a bit field of an I/O register.\r
+\r
+  Reads the bit field in a 16-bit I/O register. The bit field is specified by\r
+  the StartBit and the EndBit. The value of the bit field is returned.\r
+\r
+  If 16-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 15, then ASSERT().\r
+  If EndBit is greater than 15, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to read.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..15.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoBitFieldRead16 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit\r
+  )\r
+{\r
+  return BitFieldRead16 (IoRead16 (Port), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+  Writes a bit field to an I/O register.\r
+\r
+  Writes Value to the bit field of the I/O register. The bit field is specified\r
+  by the StartBit and the EndBit. All other bits in the destination I/O\r
+  register are preserved. The value written to the I/O port is returned. Extra\r
+  left bits in Value are stripped.\r
+\r
+  If 16-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 15, then ASSERT().\r
+  If EndBit is greater than 15, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  Value     New value of the bit field.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoBitFieldWrite16 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT16                    Value\r
+  )\r
+{\r
+  return IoWrite16 (\r
+           Port,\r
+           BitFieldWrite16 (IoRead16 (Port), StartBit, EndBit, Value)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 16-bit port, performs a bitwise OR, and writes the\r
+  result back to the bit field in the 16-bit port.\r
+\r
+  Reads the 16-bit I/O port specified by Port, performs a bitwise OR\r
+  between the read result and the value specified by OrData, and writes the\r
+  result to the 16-bit I/O port specified by Port. The value written to the I/O\r
+  port is returned. This function must guarantee that all I/O read and write\r
+  operations are serialized. Extra left bits in OrData are stripped.\r
+\r
+  If 16-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 15, then ASSERT().\r
+  If EndBit is greater than 15, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  OrData    The value to OR with the read value from the I/O port.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoBitFieldOr16 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT16                    OrData\r
+  )\r
+{\r
+  return IoWrite16 (\r
+           Port,\r
+           BitFieldOr16 (IoRead16 (Port), StartBit, EndBit, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 16-bit port, performs a bitwise AND, and writes the\r
+  result back to the bit field in the 16-bit port.\r
+\r
+  Reads the 16-bit I/O port specified by Port, performs a bitwise AND between\r
+  the read result and the value specified by AndData, and writes the result to\r
+  the 16-bit I/O port specified by Port. The value written to the I/O port is\r
+  returned. This function must guarantee that all I/O read and write operations\r
+  are serialized. Extra left bits in AndData are stripped.\r
+\r
+  If 16-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 15, then ASSERT().\r
+  If EndBit is greater than 15, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  AndData   The value to AND with the read value from the I/O port.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoBitFieldAnd16 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT16                    AndData\r
+  )\r
+{\r
+  return IoWrite16 (\r
+           Port,\r
+           BitFieldAnd16 (IoRead16 (Port), StartBit, EndBit, AndData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
+  bitwise OR, and writes the result back to the bit field in the\r
+  16-bit port.\r
+\r
+  Reads the 16-bit I/O port specified by Port, performs a bitwise AND followed\r
+  by a bitwise OR between the read result and the value specified by\r
+  AndData, and writes the result to the 16-bit I/O port specified by Port. The\r
+  value written to the I/O port is returned. This function must guarantee that\r
+  all I/O read and write operations are serialized. Extra left bits in both\r
+  AndData and OrData are stripped.\r
+\r
+  If 16-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 15, then ASSERT().\r
+  If EndBit is greater than 15, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  AndData   The value to AND with the read value from the I/O port.\r
+  @param  OrData    The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoBitFieldAndThenOr16 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT16                    AndData,\r
+  IN      UINT16                    OrData\r
+  )\r
+{\r
+  return IoWrite16 (\r
+           Port,\r
+           BitFieldAndThenOr16 (IoRead16 (Port), StartBit, EndBit, AndData, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a 32-bit I/O port, performs a bitwise OR, and writes the\r
+  result back to the 32-bit I/O port.\r
+\r
+  Reads the 32-bit I/O port specified by Port, performs a bitwise OR\r
+  between the read result and the value specified by OrData, and writes the\r
+  result to the 32-bit I/O port specified by Port. The value written to the I/O\r
+  port is returned. This function must guarantee that all I/O read and write\r
+  operations are serialized.\r
+\r
+  If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port    The I/O port to write.\r
+  @param  OrData  The value to OR with the read value from the I/O port.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoOr32 (\r
+  IN      UINTN                     Port,\r
+  IN      UINT32                    OrData\r
+  )\r
+{\r
+  return IoWrite32 (Port, IoRead32 (Port) | OrData);\r
+}\r
+\r
+/**\r
+  Reads a 32-bit I/O port, performs a bitwise AND, and writes the result back\r
+  to the 32-bit I/O port.\r
+\r
+  Reads the 32-bit I/O port specified by Port, performs a bitwise AND between\r
+  the read result and the value specified by AndData, and writes the result to\r
+  the 32-bit I/O port specified by Port. The value written to the I/O port is\r
+  returned. This function must guarantee that all I/O read and write operations\r
+  are serialized.\r
+\r
+  If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port    The I/O port to write.\r
+  @param  AndData The value to AND with the read value from the I/O port.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoAnd32 (\r
+  IN      UINTN                     Port,\r
+  IN      UINT32                    AndData\r
+  )\r
+{\r
+  return IoWrite32 (Port, IoRead32 (Port) & AndData);\r
+}\r
+\r
+/**\r
+  Reads a 32-bit I/O port, performs a bitwise AND followed by a bitwise\r
+  inclusive OR, and writes the result back to the 32-bit I/O port.\r
+\r
+  Reads the 32-bit I/O port specified by Port, performs a bitwise AND between\r
+  the read result and the value specified by AndData, performs a bitwise OR\r
+  between the result of the AND operation and the value specified by OrData,\r
+  and writes the result to the 32-bit I/O port specified by Port. The value\r
+  written to the I/O port is returned. This function must guarantee that all\r
+  I/O read and write operations are serialized.\r
+\r
+  If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port    The I/O port to write.\r
+  @param  AndData The value to AND with the read value from the I/O port.\r
+  @param  OrData  The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoAndThenOr32 (\r
+  IN      UINTN                     Port,\r
+  IN      UINT32                    AndData,\r
+  IN      UINT32                    OrData\r
+  )\r
+{\r
+  return IoWrite32 (Port, (IoRead32 (Port) & AndData) | OrData);\r
+}\r
+\r
+/**\r
+  Reads a bit field of an I/O register.\r
+\r
+  Reads the bit field in a 32-bit I/O register. The bit field is specified by\r
+  the StartBit and the EndBit. The value of the bit field is returned.\r
+\r
+  If 32-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 31, then ASSERT().\r
+  If EndBit is greater than 31, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to read.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..31.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoBitFieldRead32 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit\r
+  )\r
+{\r
+  return BitFieldRead32 (IoRead32 (Port), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+  Writes a bit field to an I/O register.\r
+\r
+  Writes Value to the bit field of the I/O register. The bit field is specified\r
+  by the StartBit and the EndBit. All other bits in the destination I/O\r
+  register are preserved. The value written to the I/O port is returned. Extra\r
+  left bits in Value are stripped.\r
+\r
+  If 32-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 31, then ASSERT().\r
+  If EndBit is greater than 31, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  Value     New value of the bit field.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoBitFieldWrite32 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT32                    Value\r
+  )\r
+{\r
+  return IoWrite32 (\r
+           Port,\r
+           BitFieldWrite32 (IoRead32 (Port), StartBit, EndBit, Value)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 32-bit port, performs a bitwise OR, and writes the\r
+  result back to the bit field in the 32-bit port.\r
+\r
+  Reads the 32-bit I/O port specified by Port, performs a bitwise OR\r
+  between the read result and the value specified by OrData, and writes the\r
+  result to the 32-bit I/O port specified by Port. The value written to the I/O\r
+  port is returned. This function must guarantee that all I/O read and write\r
+  operations are serialized. Extra left bits in OrData are stripped.\r
+\r
+  If 32-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 31, then ASSERT().\r
+  If EndBit is greater than 31, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  OrData    The value to OR with the read value from the I/O port.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoBitFieldOr32 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT32                    OrData\r
+  )\r
+{\r
+  return IoWrite32 (\r
+           Port,\r
+           BitFieldOr32 (IoRead32 (Port), StartBit, EndBit, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 32-bit port, performs a bitwise AND, and writes the\r
+  result back to the bit field in the 32-bit port.\r
+\r
+  Reads the 32-bit I/O port specified by Port, performs a bitwise AND between\r
+  the read result and the value specified by AndData, and writes the result to\r
+  the 32-bit I/O port specified by Port. The value written to the I/O port is\r
+  returned. This function must guarantee that all I/O read and write operations\r
+  are serialized. Extra left bits in AndData are stripped.\r
+\r
+  If 32-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 31, then ASSERT().\r
+  If EndBit is greater than 31, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  AndData   The value to AND with the read value from the I/O port.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoBitFieldAnd32 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT32                    AndData\r
+  )\r
+{\r
+  return IoWrite32 (\r
+           Port,\r
+           BitFieldAnd32 (IoRead32 (Port), StartBit, EndBit, AndData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
+  bitwise OR, and writes the result back to the bit field in the\r
+  32-bit port.\r
+\r
+  Reads the 32-bit I/O port specified by Port, performs a bitwise AND followed\r
+  by a bitwise OR between the read result and the value specified by\r
+  AndData, and writes the result to the 32-bit I/O port specified by Port. The\r
+  value written to the I/O port is returned. This function must guarantee that\r
+  all I/O read and write operations are serialized. Extra left bits in both\r
+  AndData and OrData are stripped.\r
+\r
+  If 32-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 31, then ASSERT().\r
+  If EndBit is greater than 31, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  AndData   The value to AND with the read value from the I/O port.\r
+  @param  OrData    The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoBitFieldAndThenOr32 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT32                    AndData,\r
+  IN      UINT32                    OrData\r
+  )\r
+{\r
+  return IoWrite32 (\r
+           Port,\r
+           BitFieldAndThenOr32 (IoRead32 (Port), StartBit, EndBit, AndData, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a 64-bit I/O port, performs a bitwise OR, and writes the\r
+  result back to the 64-bit I/O port.\r
+\r
+  Reads the 64-bit I/O port specified by Port, performs a bitwise OR\r
+  between the read result and the value specified by OrData, and writes the\r
+  result to the 64-bit I/O port specified by Port. The value written to the I/O\r
+  port is returned. This function must guarantee that all I/O read and write\r
+  operations are serialized.\r
+\r
+  If 64-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port    The I/O port to write.\r
+  @param  OrData  The value to OR with the read value from the I/O port.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoOr64 (\r
+  IN      UINTN                     Port,\r
+  IN      UINT64                    OrData\r
+  )\r
+{\r
+  return IoWrite64 (Port, IoRead64 (Port) | OrData);\r
+}\r
+\r
+/**\r
+  Reads a 64-bit I/O port, performs a bitwise AND, and writes the result back\r
+  to the 64-bit I/O port.\r
+\r
+  Reads the 64-bit I/O port specified by Port, performs a bitwise AND between\r
+  the read result and the value specified by AndData, and writes the result to\r
+  the 64-bit I/O port specified by Port. The value written to the I/O port is\r
+  returned. This function must guarantee that all I/O read and write operations\r
+  are serialized.\r
+\r
+  If 64-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port    The I/O port to write.\r
+  @param  AndData The value to AND with the read value from the I/O port.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoAnd64 (\r
+  IN      UINTN                     Port,\r
+  IN      UINT64                    AndData\r
+  )\r
+{\r
+  return IoWrite64 (Port, IoRead64 (Port) & AndData);\r
+}\r
+\r
+/**\r
+  Reads a 64-bit I/O port, performs a bitwise AND followed by a bitwise\r
+  inclusive OR, and writes the result back to the 64-bit I/O port.\r
+\r
+  Reads the 64-bit I/O port specified by Port, performs a bitwise AND between\r
+  the read result and the value specified by AndData, performs a bitwise OR\r
+  between the result of the AND operation and the value specified by OrData,\r
+  and writes the result to the 64-bit I/O port specified by Port. The value\r
+  written to the I/O port is returned. This function must guarantee that all\r
+  I/O read and write operations are serialized.\r
+\r
+  If 64-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port    The I/O port to write.\r
+  @param  AndData The value to AND with the read value from the I/O port.\r
+  @param  OrData  The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoAndThenOr64 (\r
+  IN      UINTN                     Port,\r
+  IN      UINT64                    AndData,\r
+  IN      UINT64                    OrData\r
+  )\r
+{\r
+  return IoWrite64 (Port, (IoRead64 (Port) & AndData) | OrData);\r
+}\r
+\r
+/**\r
+  Reads a bit field of an I/O register.\r
+\r
+  Reads the bit field in a 64-bit I/O register. The bit field is specified by\r
+  the StartBit and the EndBit. The value of the bit field is returned.\r
+\r
+  If 64-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 63, then ASSERT().\r
+  If EndBit is greater than 63, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to read.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..63.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoBitFieldRead64 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit\r
+  )\r
+{\r
+  return BitFieldRead64 (IoRead64 (Port), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+  Writes a bit field to an I/O register.\r
+\r
+  Writes Value to the bit field of the I/O register. The bit field is specified\r
+  by the StartBit and the EndBit. All other bits in the destination I/O\r
+  register are preserved. The value written to the I/O port is returned. Extra\r
+  left bits in Value are stripped.\r
+\r
+  If 64-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 63, then ASSERT().\r
+  If EndBit is greater than 63, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  Value     New value of the bit field.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoBitFieldWrite64 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT64                    Value\r
+  )\r
+{\r
+  return IoWrite64 (\r
+           Port,\r
+           BitFieldWrite64 (IoRead64 (Port), StartBit, EndBit, Value)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 64-bit port, performs a bitwise OR, and writes the\r
+  result back to the bit field in the 64-bit port.\r
+\r
+  Reads the 64-bit I/O port specified by Port, performs a bitwise OR\r
+  between the read result and the value specified by OrData, and writes the\r
+  result to the 64-bit I/O port specified by Port. The value written to the I/O\r
+  port is returned. This function must guarantee that all I/O read and write\r
+  operations are serialized. Extra left bits in OrData are stripped.\r
+\r
+  If 64-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 63, then ASSERT().\r
+  If EndBit is greater than 63, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  OrData    The value to OR with the read value from the I/O port.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoBitFieldOr64 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT64                    OrData\r
+  )\r
+{\r
+  return IoWrite64 (\r
+           Port,\r
+           BitFieldOr64 (IoRead64 (Port), StartBit, EndBit, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 64-bit port, performs a bitwise AND, and writes the\r
+  result back to the bit field in the 64-bit port.\r
+\r
+  Reads the 64-bit I/O port specified by Port, performs a bitwise AND between\r
+  the read result and the value specified by AndData, and writes the result to\r
+  the 64-bit I/O port specified by Port. The value written to the I/O port is\r
+  returned. This function must guarantee that all I/O read and write operations\r
+  are serialized. Extra left bits in AndData are stripped.\r
+\r
+  If 64-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 63, then ASSERT().\r
+  If EndBit is greater than 63, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  AndData   The value to AND with the read value from the I/O port.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoBitFieldAnd64 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT64                    AndData\r
+  )\r
+{\r
+  return IoWrite64 (\r
+           Port,\r
+           BitFieldAnd64 (IoRead64 (Port), StartBit, EndBit, AndData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 64-bit port, performs a bitwise AND followed by a\r
+  bitwise OR, and writes the result back to the bit field in the\r
+  64-bit port.\r
+\r
+  Reads the 64-bit I/O port specified by Port, performs a bitwise AND followed\r
+  by a bitwise OR between the read result and the value specified by\r
+  AndData, and writes the result to the 64-bit I/O port specified by Port. The\r
+  value written to the I/O port is returned. This function must guarantee that\r
+  all I/O read and write operations are serialized. Extra left bits in both\r
+  AndData and OrData are stripped.\r
+\r
+  If 64-bit I/O port operations are not supported, then ASSERT().\r
+  If StartBit is greater than 63, then ASSERT().\r
+  If EndBit is greater than 63, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Port      The I/O port to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  AndData   The value to AND with the read value from the I/O port.\r
+  @param  OrData    The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoBitFieldAndThenOr64 (\r
+  IN      UINTN                     Port,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT64                    AndData,\r
+  IN      UINT64                    OrData\r
+  )\r
+{\r
+  return IoWrite64 (\r
+           Port,\r
+           BitFieldAndThenOr64 (IoRead64 (Port), StartBit, EndBit, AndData, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads an 8-bit MMIO register, performs a bitwise OR, and writes the\r
+  result back to the 8-bit MMIO register.\r
+\r
+  Reads the 8-bit MMIO register specified by Address, performs a bitwise\r
+  inclusive OR between the read result and the value specified by OrData, and\r
+  writes the result to the 8-bit MMIO register specified by Address. The value\r
+  written to the MMIO register is returned. This function must guarantee that\r
+  all MMIO read and write operations are serialized.\r
+\r
+  If 8-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+  @param  Address The MMIO register to write.\r
+  @param  OrData  The value to OR with the read value from the MMIO register.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioOr8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT8                     OrData\r
+  )\r
+{\r
+  return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) | OrData));\r
+}\r
+\r
+/**\r
+  Reads an 8-bit MMIO register, performs a bitwise AND, and writes the result\r
+  back to the 8-bit MMIO register.\r
+\r
+  Reads the 8-bit MMIO register specified by Address, performs a bitwise AND\r
+  between the read result and the value specified by AndData, and writes the\r
+  result to the 8-bit MMIO register specified by Address. The value written to\r
+  the MMIO register is returned. This function must guarantee that all MMIO\r
+  read and write operations are serialized.\r
+\r
+  If 8-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+  @param  Address The MMIO register to write.\r
+  @param  AndData The value to AND with the read value from the MMIO register.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioAnd8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT8                     AndData\r
+  )\r
+{\r
+  return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) & AndData));\r
+}\r
+\r
+/**\r
+  Reads an 8-bit MMIO register, performs a bitwise AND followed by a bitwise\r
+  inclusive OR, and writes the result back to the 8-bit MMIO register.\r
+\r
+  Reads the 8-bit MMIO register specified by Address, performs a bitwise AND\r
+  between the read result and the value specified by AndData, performs a\r
+  bitwise OR between the result of the AND operation and the value specified by\r
+  OrData, and writes the result to the 8-bit MMIO register specified by\r
+  Address. The value written to the MMIO register is returned. This function\r
+  must guarantee that all MMIO read and write operations are serialized.\r
+\r
+  If 8-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+\r
+  @param  Address The MMIO register to write.\r
+  @param  AndData The value to AND with the read value from the MMIO register.\r
+  @param  OrData  The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioAndThenOr8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT8                     AndData,\r
+  IN      UINT8                     OrData\r
+  )\r
+{\r
+  return MmioWrite8 (Address, (UINT8) ((MmioRead8 (Address) & AndData) | OrData));\r
+}\r
+\r
+/**\r
+  Reads a bit field of a MMIO register.\r
+\r
+  Reads the bit field in an 8-bit MMIO register. The bit field is specified by\r
+  the StartBit and the EndBit. The value of the bit field is returned.\r
+\r
+  If 8-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 7, then ASSERT().\r
+  If EndBit is greater than 7, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to read.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..7.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioBitFieldRead8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit\r
+  )\r
+{\r
+  return BitFieldRead8 (MmioRead8 (Address), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+  Writes a bit field to a MMIO register.\r
+\r
+  Writes Value to the bit field of the MMIO register. The bit field is\r
+  specified by the StartBit and the EndBit. All other bits in the destination\r
+  MMIO register are preserved. The new value of the 8-bit register is returned.\r
+\r
+  If 8-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 7, then ASSERT().\r
+  If EndBit is greater than 7, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  Value     New value of the bit field.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioBitFieldWrite8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT8                     Value\r
+  )\r
+{\r
+  return MmioWrite8 (\r
+           Address,\r
+           BitFieldWrite8 (MmioRead8 (Address), StartBit, EndBit, Value)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in an 8-bit MMIO register, performs a bitwise OR, and\r
+  writes the result back to the bit field in the 8-bit MMIO register.\r
+\r
+  Reads the 8-bit MMIO register specified by Address, performs a bitwise\r
+  inclusive OR between the read result and the value specified by OrData, and\r
+  writes the result to the 8-bit MMIO register specified by Address. The value\r
+  written to the MMIO register is returned. This function must guarantee that\r
+  all MMIO read and write operations are serialized. Extra left bits in OrData\r
+  are stripped.\r
+\r
+  If 8-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 7, then ASSERT().\r
+  If EndBit is greater than 7, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  OrData    The value to OR with read value from the MMIO register.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioBitFieldOr8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT8                     OrData\r
+  )\r
+{\r
+  return MmioWrite8 (\r
+           Address,\r
+           BitFieldOr8 (MmioRead8 (Address), StartBit, EndBit, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in an 8-bit MMIO register, performs a bitwise AND, and\r
+  writes the result back to the bit field in the 8-bit MMIO register.\r
+\r
+  Reads the 8-bit MMIO register specified by Address, performs a bitwise AND\r
+  between the read result and the value specified by AndData, and writes the\r
+  result to the 8-bit MMIO register specified by Address. The value written to\r
+  the MMIO register is returned. This function must guarantee that all MMIO\r
+  read and write operations are serialized. Extra left bits in AndData are\r
+  stripped.\r
+\r
+  If 8-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 7, then ASSERT().\r
+  If EndBit is greater than 7, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  AndData   The value to AND with read value from the MMIO register.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioBitFieldAnd8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT8                     AndData\r
+  )\r
+{\r
+  return MmioWrite8 (\r
+           Address,\r
+           BitFieldAnd8 (MmioRead8 (Address), StartBit, EndBit, AndData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in an 8-bit MMIO register, performs a bitwise AND followed\r
+  by a bitwise OR, and writes the result back to the bit field in the\r
+  8-bit MMIO register.\r
+\r
+  Reads the 8-bit MMIO register specified by Address, performs a bitwise AND\r
+  followed by a bitwise OR between the read result and the value\r
+  specified by AndData, and writes the result to the 8-bit MMIO register\r
+  specified by Address. The value written to the MMIO register is returned.\r
+  This function must guarantee that all MMIO read and write operations are\r
+  serialized. Extra left bits in both AndData and OrData are stripped.\r
+\r
+  If 8-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 7, then ASSERT().\r
+  If EndBit is greater than 7, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  AndData   The value to AND with read value from the MMIO register.\r
+  @param  OrData    The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioBitFieldAndThenOr8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT8                     AndData,\r
+  IN      UINT8                     OrData\r
+  )\r
+{\r
+  return MmioWrite8 (\r
+           Address,\r
+           BitFieldAndThenOr8 (MmioRead8 (Address), StartBit, EndBit, AndData, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a 16-bit MMIO register, performs a bitwise OR, and writes the\r
+  result back to the 16-bit MMIO register.\r
+\r
+  Reads the 16-bit MMIO register specified by Address, performs a bitwise\r
+  inclusive OR between the read result and the value specified by OrData, and\r
+  writes the result to the 16-bit MMIO register specified by Address. The value\r
+  written to the MMIO register is returned. This function must guarantee that\r
+  all MMIO read and write operations are serialized.\r
+\r
+  If 16-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+  @param  Address The MMIO register to write.\r
+  @param  OrData  The value to OR with the read value from the MMIO register.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioOr16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT16                    OrData\r
+  )\r
+{\r
+  return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) | OrData));\r
+}\r
+\r
+/**\r
+  Reads a 16-bit MMIO register, performs a bitwise AND, and writes the result\r
+  back to the 16-bit MMIO register.\r
+\r
+  Reads the 16-bit MMIO register specified by Address, performs a bitwise AND\r
+  between the read result and the value specified by AndData, and writes the\r
+  result to the 16-bit MMIO register specified by Address. The value written to\r
+  the MMIO register is returned. This function must guarantee that all MMIO\r
+  read and write operations are serialized.\r
+\r
+  If 16-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+  @param  Address The MMIO register to write.\r
+  @param  AndData The value to AND with the read value from the MMIO register.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioAnd16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT16                    AndData\r
+  )\r
+{\r
+  return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) & AndData));\r
+}\r
+\r
+/**\r
+  Reads a 16-bit MMIO register, performs a bitwise AND followed by a bitwise\r
+  inclusive OR, and writes the result back to the 16-bit MMIO register.\r
+\r
+  Reads the 16-bit MMIO register specified by Address, performs a bitwise AND\r
+  between the read result and the value specified by AndData, performs a\r
+  bitwise OR between the result of the AND operation and the value specified by\r
+  OrData, and writes the result to the 16-bit MMIO register specified by\r
+  Address. The value written to the MMIO register is returned. This function\r
+  must guarantee that all MMIO read and write operations are serialized.\r
+\r
+  If 16-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+\r
+  @param  Address The MMIO register to write.\r
+  @param  AndData The value to AND with the read value from the MMIO register.\r
+  @param  OrData  The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioAndThenOr16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT16                    AndData,\r
+  IN      UINT16                    OrData\r
+  )\r
+{\r
+  return MmioWrite16 (Address, (UINT16) ((MmioRead16 (Address) & AndData) | OrData));\r
+}\r
+\r
+/**\r
+  Reads a bit field of a MMIO register.\r
+\r
+  Reads the bit field in a 16-bit MMIO register. The bit field is specified by\r
+  the StartBit and the EndBit. The value of the bit field is returned.\r
+\r
+  If 16-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 15, then ASSERT().\r
+  If EndBit is greater than 15, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to read.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..15.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioBitFieldRead16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit\r
+  )\r
+{\r
+  return BitFieldRead16 (MmioRead16 (Address), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+  Writes a bit field to a MMIO register.\r
+\r
+  Writes Value to the bit field of the MMIO register. The bit field is\r
+  specified by the StartBit and the EndBit. All other bits in the destination\r
+  MMIO register are preserved. The new value of the 16-bit register is returned.\r
+\r
+  If 16-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 15, then ASSERT().\r
+  If EndBit is greater than 15, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  Value     New value of the bit field.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioBitFieldWrite16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT16                    Value\r
+  )\r
+{\r
+  return MmioWrite16 (\r
+           Address,\r
+           BitFieldWrite16 (MmioRead16 (Address), StartBit, EndBit, Value)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 16-bit MMIO register, performs a bitwise OR, and\r
+  writes the result back to the bit field in the 16-bit MMIO register.\r
+\r
+  Reads the 16-bit MMIO register specified by Address, performs a bitwise\r
+  inclusive OR between the read result and the value specified by OrData, and\r
+  writes the result to the 16-bit MMIO register specified by Address. The value\r
+  written to the MMIO register is returned. This function must guarantee that\r
+  all MMIO read and write operations are serialized. Extra left bits in OrData\r
+  are stripped.\r
+\r
+  If 16-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 15, then ASSERT().\r
+  If EndBit is greater than 15, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  OrData    The value to OR with read value from the MMIO register.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioBitFieldOr16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT16                    OrData\r
+  )\r
+{\r
+  return MmioWrite16 (\r
+           Address,\r
+           BitFieldOr16 (MmioRead16 (Address), StartBit, EndBit, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 16-bit MMIO register, performs a bitwise AND, and\r
+  writes the result back to the bit field in the 16-bit MMIO register.\r
+\r
+  Reads the 16-bit MMIO register specified by Address, performs a bitwise AND\r
+  between the read result and the value specified by AndData, and writes the\r
+  result to the 16-bit MMIO register specified by Address. The value written to\r
+  the MMIO register is returned. This function must guarantee that all MMIO\r
+  read and write operations are serialized. Extra left bits in AndData are\r
+  stripped.\r
+\r
+  If 16-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 15, then ASSERT().\r
+  If EndBit is greater than 15, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  AndData   The value to AND with read value from the MMIO register.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioBitFieldAnd16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT16                    AndData\r
+  )\r
+{\r
+  return MmioWrite16 (\r
+           Address,\r
+           BitFieldAnd16 (MmioRead16 (Address), StartBit, EndBit, AndData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 16-bit MMIO register, performs a bitwise AND followed\r
+  by a bitwise OR, and writes the result back to the bit field in the\r
+  16-bit MMIO register.\r
+\r
+  Reads the 16-bit MMIO register specified by Address, performs a bitwise AND\r
+  followed by a bitwise OR between the read result and the value\r
+  specified by AndData, and writes the result to the 16-bit MMIO register\r
+  specified by Address. The value written to the MMIO register is returned.\r
+  This function must guarantee that all MMIO read and write operations are\r
+  serialized. Extra left bits in both AndData and OrData are stripped.\r
+\r
+  If 16-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 15, then ASSERT().\r
+  If EndBit is greater than 15, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  AndData   The value to AND with read value from the MMIO register.\r
+  @param  OrData    The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioBitFieldAndThenOr16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT16                    AndData,\r
+  IN      UINT16                    OrData\r
+  )\r
+{\r
+  return MmioWrite16 (\r
+           Address,\r
+           BitFieldAndThenOr16 (MmioRead16 (Address), StartBit, EndBit, AndData, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a 32-bit MMIO register, performs a bitwise OR, and writes the\r
+  result back to the 32-bit MMIO register.\r
+\r
+  Reads the 32-bit MMIO register specified by Address, performs a bitwise\r
+  inclusive OR between the read result and the value specified by OrData, and\r
+  writes the result to the 32-bit MMIO register specified by Address. The value\r
+  written to the MMIO register is returned. This function must guarantee that\r
+  all MMIO read and write operations are serialized.\r
+\r
+  If 32-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+  @param  Address The MMIO register to write.\r
+  @param  OrData  The value to OR with the read value from the MMIO register.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioOr32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT32                    OrData\r
+  )\r
+{\r
+  return MmioWrite32 (Address, MmioRead32 (Address) | OrData);\r
+}\r
+\r
+/**\r
+  Reads a 32-bit MMIO register, performs a bitwise AND, and writes the result\r
+  back to the 32-bit MMIO register.\r
+\r
+  Reads the 32-bit MMIO register specified by Address, performs a bitwise AND\r
+  between the read result and the value specified by AndData, and writes the\r
+  result to the 32-bit MMIO register specified by Address. The value written to\r
+  the MMIO register is returned. This function must guarantee that all MMIO\r
+  read and write operations are serialized.\r
+\r
+  If 32-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+  @param  Address The MMIO register to write.\r
+  @param  AndData The value to AND with the read value from the MMIO register.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioAnd32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT32                    AndData\r
+  )\r
+{\r
+  return MmioWrite32 (Address, MmioRead32 (Address) & AndData);\r
+}\r
+\r
+/**\r
+  Reads a 32-bit MMIO register, performs a bitwise AND followed by a bitwise\r
+  inclusive OR, and writes the result back to the 32-bit MMIO register.\r
+\r
+  Reads the 32-bit MMIO register specified by Address, performs a bitwise AND\r
+  between the read result and the value specified by AndData, performs a\r
+  bitwise OR between the result of the AND operation and the value specified by\r
+  OrData, and writes the result to the 32-bit MMIO register specified by\r
+  Address. The value written to the MMIO register is returned. This function\r
+  must guarantee that all MMIO read and write operations are serialized.\r
+\r
+  If 32-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+\r
+  @param  Address The MMIO register to write.\r
+  @param  AndData The value to AND with the read value from the MMIO register.\r
+  @param  OrData  The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioAndThenOr32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT32                    AndData,\r
+  IN      UINT32                    OrData\r
+  )\r
+{\r
+  return MmioWrite32 (Address, (MmioRead32 (Address) & AndData) | OrData);\r
+}\r
+\r
+/**\r
+  Reads a bit field of a MMIO register.\r
+\r
+  Reads the bit field in a 32-bit MMIO register. The bit field is specified by\r
+  the StartBit and the EndBit. The value of the bit field is returned.\r
+\r
+  If 32-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 31, then ASSERT().\r
+  If EndBit is greater than 31, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to read.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..31.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioBitFieldRead32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit\r
+  )\r
+{\r
+  return BitFieldRead32 (MmioRead32 (Address), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+  Writes a bit field to a MMIO register.\r
+\r
+  Writes Value to the bit field of the MMIO register. The bit field is\r
+  specified by the StartBit and the EndBit. All other bits in the destination\r
+  MMIO register are preserved. The new value of the 32-bit register is returned.\r
+\r
+  If 32-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 31, then ASSERT().\r
+  If EndBit is greater than 31, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  Value     New value of the bit field.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioBitFieldWrite32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT32                    Value\r
+  )\r
+{\r
+  return MmioWrite32 (\r
+           Address,\r
+           BitFieldWrite32 (MmioRead32 (Address), StartBit, EndBit, Value)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 32-bit MMIO register, performs a bitwise OR, and\r
+  writes the result back to the bit field in the 32-bit MMIO register.\r
+\r
+  Reads the 32-bit MMIO register specified by Address, performs a bitwise\r
+  inclusive OR between the read result and the value specified by OrData, and\r
+  writes the result to the 32-bit MMIO register specified by Address. The value\r
+  written to the MMIO register is returned. This function must guarantee that\r
+  all MMIO read and write operations are serialized. Extra left bits in OrData\r
+  are stripped.\r
+\r
+  If 32-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 31, then ASSERT().\r
+  If EndBit is greater than 31, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  OrData    The value to OR with read value from the MMIO register.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioBitFieldOr32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT32                    OrData\r
+  )\r
+{\r
+  return MmioWrite32 (\r
+           Address,\r
+           BitFieldOr32 (MmioRead32 (Address), StartBit, EndBit, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 32-bit MMIO register, performs a bitwise AND, and\r
+  writes the result back to the bit field in the 32-bit MMIO register.\r
+\r
+  Reads the 32-bit MMIO register specified by Address, performs a bitwise AND\r
+  between the read result and the value specified by AndData, and writes the\r
+  result to the 32-bit MMIO register specified by Address. The value written to\r
+  the MMIO register is returned. This function must guarantee that all MMIO\r
+  read and write operations are serialized. Extra left bits in AndData are\r
+  stripped.\r
+\r
+  If 32-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 31, then ASSERT().\r
+  If EndBit is greater than 31, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  AndData   The value to AND with read value from the MMIO register.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioBitFieldAnd32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT32                    AndData\r
+  )\r
+{\r
+  return MmioWrite32 (\r
+           Address,\r
+           BitFieldAnd32 (MmioRead32 (Address), StartBit, EndBit, AndData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 32-bit MMIO register, performs a bitwise AND followed\r
+  by a bitwise OR, and writes the result back to the bit field in the\r
+  32-bit MMIO register.\r
+\r
+  Reads the 32-bit MMIO register specified by Address, performs a bitwise AND\r
+  followed by a bitwise OR between the read result and the value\r
+  specified by AndData, and writes the result to the 32-bit MMIO register\r
+  specified by Address. The value written to the MMIO register is returned.\r
+  This function must guarantee that all MMIO read and write operations are\r
+  serialized. Extra left bits in both AndData and OrData are stripped.\r
+\r
+  If 32-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 31, then ASSERT().\r
+  If EndBit is greater than 31, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  AndData   The value to AND with read value from the MMIO register.\r
+  @param  OrData    The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioBitFieldAndThenOr32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT32                    AndData,\r
+  IN      UINT32                    OrData\r
+  )\r
+{\r
+  return MmioWrite32 (\r
+           Address,\r
+           BitFieldAndThenOr32 (MmioRead32 (Address), StartBit, EndBit, AndData, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a 64-bit MMIO register, performs a bitwise OR, and writes the\r
+  result back to the 64-bit MMIO register.\r
+\r
+  Reads the 64-bit MMIO register specified by Address, performs a bitwise\r
+  inclusive OR between the read result and the value specified by OrData, and\r
+  writes the result to the 64-bit MMIO register specified by Address. The value\r
+  written to the MMIO register is returned. This function must guarantee that\r
+  all MMIO read and write operations are serialized.\r
+\r
+  If 64-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+  @param  Address The MMIO register to write.\r
+  @param  OrData  The value to OR with the read value from the MMIO register.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioOr64 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT64                    OrData\r
+  )\r
+{\r
+  return MmioWrite64 (Address, MmioRead64 (Address) | OrData);\r
+}\r
+\r
+/**\r
+  Reads a 64-bit MMIO register, performs a bitwise AND, and writes the result\r
+  back to the 64-bit MMIO register.\r
+\r
+  Reads the 64-bit MMIO register specified by Address, performs a bitwise AND\r
+  between the read result and the value specified by AndData, and writes the\r
+  result to the 64-bit MMIO register specified by Address. The value written to\r
+  the MMIO register is returned. This function must guarantee that all MMIO\r
+  read and write operations are serialized.\r
+\r
+  If 64-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+  @param  Address The MMIO register to write.\r
+  @param  AndData The value to AND with the read value from the MMIO register.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioAnd64 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT64                    AndData\r
+  )\r
+{\r
+  return MmioWrite64 (Address, MmioRead64 (Address) & AndData);\r
+}\r
+\r
+/**\r
+  Reads a 64-bit MMIO register, performs a bitwise AND followed by a bitwise\r
+  inclusive OR, and writes the result back to the 64-bit MMIO register.\r
+\r
+  Reads the 64-bit MMIO register specified by Address, performs a bitwise AND\r
+  between the read result and the value specified by AndData, performs a\r
+  bitwise OR between the result of the AND operation and the value specified by\r
+  OrData, and writes the result to the 64-bit MMIO register specified by\r
+  Address. The value written to the MMIO register is returned. This function\r
+  must guarantee that all MMIO read and write operations are serialized.\r
+\r
+  If 64-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+\r
+  @param  Address The MMIO register to write.\r
+  @param  AndData The value to AND with the read value from the MMIO register.\r
+  @param  OrData  The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioAndThenOr64 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT64                    AndData,\r
+  IN      UINT64                    OrData\r
+  )\r
+{\r
+  return MmioWrite64 (Address, (MmioRead64 (Address) & AndData) | OrData);\r
+}\r
+\r
+/**\r
+  Reads a bit field of a MMIO register.\r
+\r
+  Reads the bit field in a 64-bit MMIO register. The bit field is specified by\r
+  the StartBit and the EndBit. The value of the bit field is returned.\r
+\r
+  If 64-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 63, then ASSERT().\r
+  If EndBit is greater than 63, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to read.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..63.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioBitFieldRead64 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit\r
+  )\r
+{\r
+  return BitFieldRead64 (MmioRead64 (Address), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+  Writes a bit field to a MMIO register.\r
+\r
+  Writes Value to the bit field of the MMIO register. The bit field is\r
+  specified by the StartBit and the EndBit. All other bits in the destination\r
+  MMIO register are preserved. The new value of the 64-bit register is returned.\r
+\r
+  If 64-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 63, then ASSERT().\r
+  If EndBit is greater than 63, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  Value     New value of the bit field.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioBitFieldWrite64 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT64                    Value\r
+  )\r
+{\r
+  return MmioWrite64 (\r
+           Address,\r
+           BitFieldWrite64 (MmioRead64 (Address), StartBit, EndBit, Value)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 64-bit MMIO register, performs a bitwise OR, and\r
+  writes the result back to the bit field in the 64-bit MMIO register.\r
+\r
+  Reads the 64-bit MMIO register specified by Address, performs a bitwise\r
+  inclusive OR between the read result and the value specified by OrData, and\r
+  writes the result to the 64-bit MMIO register specified by Address. The value\r
+  written to the MMIO register is returned. This function must guarantee that\r
+  all MMIO read and write operations are serialized. Extra left bits in OrData\r
+  are stripped.\r
+\r
+  If 64-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 63, then ASSERT().\r
+  If EndBit is greater than 63, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  OrData    The value to OR with read value from the MMIO register.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioBitFieldOr64 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT64                    OrData\r
+  )\r
+{\r
+  return MmioWrite64 (\r
+           Address,\r
+           BitFieldOr64 (MmioRead64 (Address), StartBit, EndBit, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 64-bit MMIO register, performs a bitwise AND, and\r
+  writes the result back to the bit field in the 64-bit MMIO register.\r
+\r
+  Reads the 64-bit MMIO register specified by Address, performs a bitwise AND\r
+  between the read result and the value specified by AndData, and writes the\r
+  result to the 64-bit MMIO register specified by Address. The value written to\r
+  the MMIO register is returned. This function must guarantee that all MMIO\r
+  read and write operations are serialized. Extra left bits in AndData are\r
+  stripped.\r
+\r
+  If 64-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 63, then ASSERT().\r
+  If EndBit is greater than 63, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  AndData   The value to AND with read value from the MMIO register.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioBitFieldAnd64 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT64                    AndData\r
+  )\r
+{\r
+  return MmioWrite64 (\r
+           Address,\r
+           BitFieldAnd64 (MmioRead64 (Address), StartBit, EndBit, AndData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 64-bit MMIO register, performs a bitwise AND followed\r
+  by a bitwise OR, and writes the result back to the bit field in the\r
+  64-bit MMIO register.\r
+\r
+  Reads the 64-bit MMIO register specified by Address, performs a bitwise AND\r
+  followed by a bitwise OR between the read result and the value\r
+  specified by AndData, and writes the result to the 64-bit MMIO register\r
+  specified by Address. The value written to the MMIO register is returned.\r
+  This function must guarantee that all MMIO read and write operations are\r
+  serialized. Extra left bits in both AndData and OrData are stripped.\r
+\r
+  If 64-bit MMIO register operations are not supported, then ASSERT().\r
+  If StartBit is greater than 63, then ASSERT().\r
+  If EndBit is greater than 63, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   MMIO register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..63.\r
+  @param  AndData   The value to AND with read value from the MMIO register.\r
+  @param  OrData    The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioBitFieldAndThenOr64 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT64                    AndData,\r
+  IN      UINT64                    OrData\r
+  )\r
+{\r
+  return MmioWrite64 (\r
+           Address,\r
+           BitFieldAndThenOr64 (MmioRead64 (Address), StartBit, EndBit, AndData, OrData)\r
+           );\r
+}\r

diff --git a/MdePkg/Library/SmmIoLibCpuIo/IoLib.c b/MdePkg/Library/SmmIoLibCpuIo/IoLib.c
new file mode 100644 (file)
index 0000000..4b74e9c
--- /dev/null
+++ b/MdePkg/Library/SmmIoLibCpuIo/IoLib.c
@@ -0,0 +1,642 @@
+/** @file\r
+  I/O Library.\r
+  The implementation of I/O operation for this library instance \r
+  are based on EFI_CPU_IO_PROTOCOL.\r
+  \r
+  Copyright (c) 2009, Intel Corporation<BR>\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+  Module Name:  IoLib.c\r
+\r
+**/\r
+\r
+\r
+#include "SmmCpuIoLibInternal.h"\r
+\r
+//\r
+// Globle varible to cache pointer to CpuIo protocol.\r
+//\r
+EFI_SMM_CPU_IO_PROTOCOL              *mCpuIo = NULL;\r
+EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL  *mPciRootBridgeIo = NULL;\r
+\r
+/**\r
+  The constructor function caches the pointer to CpuIo protocol.\r
+\r
+  The constructor function locates CpuIo protocol from protocol database.\r
+  It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.\r
+\r
+  @param  ImageHandle   The firmware allocated handle for the EFI image.\r
+  @param  SystemTable   A pointer to the EFI System Table.\r
+\r
+  @retval EFI_SUCCESS   The constructor always returns EFI_SUCCESS.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+IoLibConstructor (\r
+  IN      EFI_HANDLE                ImageHandle,\r
+  IN      EFI_SYSTEM_TABLE          *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS                        Status;\r
+\r
+  Status = gSmst->SmmLocateProtocol (&gEfiSmmPciRootBridgeIoProtocolGuid, NULL, (VOID **) &mPciRootBridgeIo);\r
+  if (EFI_ERROR (Status)) {\r
+    Status = gSmst->SmmLocateProtocol (&gEfiSmmCpuIoProtocolGuid, NULL, (VOID **) &mCpuIo);\r
+  }\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Reads registers in the EFI CPU I/O space.\r
+\r
+  Reads the I/O port specified by Port with registers width specified by Width.\r
+  The read value is returned. If such operations are not supported, then ASSERT().\r
+  This function must guarantee that all I/O read and write operations are serialized.\r
+\r
+  @param  Port          The base address of the I/O operation.\r
+                        The caller is responsible for aligning the Address if required.\r
+  @param  Width         The width of the I/O operation.\r
+\r
+  @return Data read from registers in the EFI CPU I/O space.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoReadWorker (\r
+  IN      UINTN                     Port,\r
+  IN      EFI_SMM_IO_WIDTH          Width\r
+  )\r
+{\r
+  EFI_STATUS                        Status;\r
+  UINT64                            Data;\r
+\r
+  if (mPciRootBridgeIo != NULL) {\r
+    Status = mPciRootBridgeIo->Io.Read (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Port, 1, &Data);\r
+  } else {\r
+    Status = mCpuIo->Io.Read (mCpuIo, Width, Port, 1, &Data);\r
+  }\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return Data;\r
+}\r
+\r
+/**\r
+  Writes registers in the EFI CPU I/O space.\r
+\r
+  Writes the I/O port specified by Port with registers width and value specified by Width\r
+  and Data respectively.  Data is returned. If such operations are not supported, then ASSERT().\r
+  This function must guarantee that all I/O read and write operations are serialized.\r
+\r
+  @param  Port          The base address of the I/O operation.\r
+                        The caller is responsible for aligning the Address if required.\r
+  @param  Width         The width of the I/O operation.\r
+  @param  Data          The value to write to the I/O port.\r
+\r
+  @return The paramter of Data.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoWriteWorker (\r
+  IN      UINTN                     Port,\r
+  IN      EFI_SMM_IO_WIDTH          Width,\r
+  IN      UINT64                    Data\r
+  )\r
+{\r
+  EFI_STATUS                        Status;\r
+\r
+  if (mPciRootBridgeIo != NULL) {\r
+    Status = mPciRootBridgeIo->Io.Write (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Port, 1, &Data);\r
+  } else {\r
+    Status = mCpuIo->Io.Write (mCpuIo, Width, Port, 1, &Data);\r
+  }\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return Data;\r
+}\r
+\r
+/**\r
+  Reads memory-mapped registers in the EFI system memory space.\r
+\r
+  Reads the MMIO registers specified by Address with registers width specified by Width.\r
+  The read value is returned. If such operations are not supported, then ASSERT().\r
+  This function must guarantee that all MMIO read and write operations are serialized.\r
+\r
+  @param  Address       The MMIO register to read.\r
+                        The caller is responsible for aligning the Address if required.\r
+  @param  Width         The width of the I/O operation.\r
+\r
+  @return Data read from registers in the EFI system memory space.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioReadWorker (\r
+  IN      UINTN                     Address,\r
+  IN      EFI_SMM_IO_WIDTH          Width\r
+  )\r
+{\r
+  EFI_STATUS                        Status;\r
+  UINT64                            Data;\r
+\r
+  if (mPciRootBridgeIo != NULL) {\r
+    Status = mPciRootBridgeIo->Mem.Read (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Address, 1, &Data);\r
+  } else {\r
+    Status = mCpuIo->Mem.Read (mCpuIo, Width, Address, 1, &Data);\r
+  }\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return Data;\r
+}\r
+\r
+/**\r
+  Writes memory-mapped registers in the EFI system memory space.\r
+\r
+  Writes the MMIO registers specified by Address with registers width and value specified by Width\r
+  and Data respectively. Data is returned. If such operations are not supported, then ASSERT().\r
+  This function must guarantee that all MMIO read and write operations are serialized.\r
+\r
+  @param  Address       The MMIO register to read.\r
+                        The caller is responsible for aligning the Address if required.\r
+  @param  Width         The width of the I/O operation.\r
+  @param  Data          The value to write to the I/O port.\r
+  \r
+  @return Data read from registers in the EFI system memory space.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioWriteWorker (\r
+  IN      UINTN                     Address,\r
+  IN      EFI_SMM_IO_WIDTH          Width,\r
+  IN      UINT64                    Data\r
+  )\r
+{\r
+  EFI_STATUS                        Status;\r
+\r
+  if (mPciRootBridgeIo != NULL) {\r
+    Status = mPciRootBridgeIo->Mem.Write (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Address, 1, &Data);\r
+  } else {\r
+    Status = mCpuIo->Mem.Write (mCpuIo, Width, Address, 1, &Data);\r
+  }\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return Data;\r
+}\r
+\r
+/**\r
+  Reads an 8-bit I/O port.\r
+\r
+  Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.\r
+  This function must guarantee that all I/O read and write operations are\r
+  serialized.\r
+\r
+  If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port  The I/O port to read.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoRead8 (\r
+  IN      UINTN                     Port\r
+  )\r
+{\r
+  return (UINT8)IoReadWorker (Port, SMM_IO_UINT8);\r
+}\r
+\r
+/**\r
+  Writes an 8-bit I/O port.\r
+\r
+  Writes the 8-bit I/O port specified by Port with the value specified by Value\r
+  and returns Value. This function must guarantee that all I/O read and write\r
+  operations are serialized.\r
+\r
+  If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port  The I/O port to write.\r
+  @param  Value The value to write to the I/O port.\r
+\r
+  @return The value written the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoWrite8 (\r
+  IN      UINTN                     Port,\r
+  IN      UINT8                     Value\r
+  )\r
+{\r
+  return (UINT8)IoWriteWorker (Port, SMM_IO_UINT8, Value);\r
+}\r
+\r
+/**\r
+  Reads a 16-bit I/O port.\r
+\r
+  Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.\r
+  This function must guarantee that all I/O read and write operations are\r
+  serialized.\r
+\r
+  If Port is not aligned on a 16-bit boundary, then ASSERT().\r
+ \r
+  If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port  The I/O port to read.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoRead16 (\r
+  IN      UINTN                     Port\r
+  )\r
+{\r
+  //\r
+  // Make sure Port is aligned on a 16-bit boundary.\r
+  //\r
+  ASSERT ((Port & 1) == 0);\r
+  return (UINT16)IoReadWorker (Port, SMM_IO_UINT16);\r
+}\r
+\r
+/**\r
+  Writes a 16-bit I/O port.\r
+\r
+  Writes the 16-bit I/O port specified by Port with the value specified by Value\r
+  and returns Value. This function must guarantee that all I/O read and write\r
+  operations are serialized.\r
+\r
+  If Port is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+  If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port  The I/O port to write.\r
+  @param  Value The value to write to the I/O port.\r
+\r
+  @return The value written the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoWrite16 (\r
+  IN      UINTN                     Port,\r
+  IN      UINT16                    Value\r
+  )\r
+{\r
+  //\r
+  // Make sure Port is aligned on a 16-bit boundary.\r
+  //\r
+  ASSERT ((Port & 1) == 0);\r
+  return (UINT16)IoWriteWorker (Port, SMM_IO_UINT16, Value);\r
+}\r
+\r
+/**\r
+  Reads a 32-bit I/O port.\r
+\r
+  Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.\r
+  This function must guarantee that all I/O read and write operations are\r
+  serialized.\r
+ \r
+  If Port is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+  If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port  The I/O port to read.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoRead32 (\r
+  IN      UINTN                     Port\r
+  )\r
+{\r
+  //\r
+  // Make sure Port is aligned on a 32-bit boundary.\r
+  //\r
+  ASSERT ((Port & 3) == 0);\r
+  return (UINT32)IoReadWorker (Port, SMM_IO_UINT32);\r
+}\r
+\r
+/**\r
+  Writes a 32-bit I/O port.\r
+\r
+  Writes the 32-bit I/O port specified by Port with the value specified by Value\r
+  and returns Value. This function must guarantee that all I/O read and write\r
+  operations are serialized.\r
+\r
+  If Port is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+  If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port  The I/O port to write.\r
+  @param  Value The value to write to the I/O port.\r
+\r
+  @return The value written the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoWrite32 (\r
+  IN      UINTN                     Port,\r
+  IN      UINT32                    Value\r
+  )\r
+{\r
+  //\r
+  // Make sure Port is aligned on a 32-bit boundary.\r
+  //\r
+  ASSERT ((Port & 3) == 0);\r
+  return (UINT32)IoWriteWorker (Port, SMM_IO_UINT32, Value);\r
+}\r
+\r
+/**\r
+  Reads a 64-bit I/O port.\r
+\r
+  Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.\r
+  This function must guarantee that all I/O read and write operations are\r
+  serialized.\r
+\r
+  If Port is not aligned on a 64-bit boundary, then ASSERT().\r
+\r
+  If 64-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port  The I/O port to read.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoRead64 (\r
+  IN      UINTN                     Port\r
+  )\r
+{\r
+  //\r
+  // Make sure Port is aligned on a 64-bit boundary.\r
+  //\r
+  ASSERT ((Port & 7) == 0);\r
+  return IoReadWorker (Port, SMM_IO_UINT64);\r
+}\r
+\r
+/**\r
+  Writes a 64-bit I/O port.\r
+\r
+  Writes the 64-bit I/O port specified by Port with the value specified by Value\r
+  and returns Value. This function must guarantee that all I/O read and write\r
+  operations are serialized.\r
+\r
+  If Port is not aligned on a 64-bit boundary, then ASSERT().\r
+ \r
+  If 64-bit I/O port operations are not supported, then ASSERT().\r
+\r
+  @param  Port  The I/O port to write.\r
+  @param  Value The value to write to the I/O port.\r
+\r
+  @return The value written the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoWrite64 (\r
+  IN      UINTN                     Port,\r
+  IN      UINT64                    Value\r
+  )\r
+{\r
+  //\r
+  // Make sure Port is aligned on a 64-bit boundary.\r
+  //\r
+  ASSERT ((Port & 7) == 0);\r
+  return IoWriteWorker (Port, SMM_IO_UINT64, Value);\r
+}\r
+\r
+/**\r
+  Reads an 8-bit MMIO register.\r
+\r
+  Reads the 8-bit MMIO register specified by Address. The 8-bit read value is\r
+  returned. This function must guarantee that all MMIO read and write\r
+  operations are serialized.\r
+\r
+  If 8-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+  @param  Address The MMIO register to read.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioRead8 (\r
+  IN      UINTN                     Address\r
+  )\r
+{\r
+  return (UINT8)MmioReadWorker (Address, SMM_IO_UINT8);\r
+}\r
+\r
+/**\r
+  Writes an 8-bit MMIO register.\r
+\r
+  Writes the 8-bit MMIO register specified by Address with the value specified\r
+  by Value and returns Value. This function must guarantee that all MMIO read\r
+  and write operations are serialized.\r
+\r
+  If 8-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+  @param  Address The MMIO register to write.\r
+  @param  Value   The value to write to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioWrite8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT8                     Value\r
+  )\r
+{\r
+  return (UINT8)MmioWriteWorker (Address, SMM_IO_UINT8, Value);\r
+}\r
+\r
+/**\r
+  Reads a 16-bit MMIO register.\r
+\r
+  Reads the 16-bit MMIO register specified by Address. The 16-bit read value is\r
+  returned. This function must guarantee that all MMIO read and write\r
+  operations are serialized.\r
+\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ \r
+  If 16-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+  @param  Address The MMIO register to read.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioRead16 (\r
+  IN      UINTN                     Address\r
+  )\r
+{\r
+  //\r
+  // Make sure Address is aligned on a 16-bit boundary.\r
+  //\r
+  ASSERT ((Address & 1) == 0);\r
+  return (UINT16)MmioReadWorker (Address, SMM_IO_UINT16);\r
+}\r
+\r
+/**\r
+  Writes a 16-bit MMIO register.\r
+\r
+  Writes the 16-bit MMIO register specified by Address with the value specified\r
+  by Value and returns Value. This function must guarantee that all MMIO read\r
+  and write operations are serialized.\r
+\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ \r
+  If 16-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+  @param  Address The MMIO register to write.\r
+  @param  Value   The value to write to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioWrite16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT16                    Value\r
+  )\r
+{\r
+  //\r
+  // Make sure Address is aligned on a 16-bit boundary.\r
+  //\r
+  ASSERT ((Address & 1) == 0);\r
+  return (UINT16)MmioWriteWorker (Address, SMM_IO_UINT16, Value);\r
+}\r
+\r
+/**\r
+  Reads a 32-bit MMIO register.\r
+\r
+  Reads the 32-bit MMIO register specified by Address. The 32-bit read value is\r
+  returned. This function must guarantee that all MMIO read and write\r
+  operations are serialized.\r
+\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+  \r
+  If 32-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+  @param  Address The MMIO register to read.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioRead32 (\r
+  IN      UINTN                     Address\r
+  )\r
+{\r
+  //\r
+  // Make sure Address is aligned on a 32-bit boundary.\r
+  //\r
+  ASSERT ((Address & 3) == 0);\r
+  return (UINT32)MmioReadWorker (Address, SMM_IO_UINT32);\r
+}\r
+\r
+/**\r
+  Writes a 32-bit MMIO register.\r
+\r
+  Writes the 32-bit MMIO register specified by Address with the value specified\r
+  by Value and returns Value. This function must guarantee that all MMIO read\r
+  and write operations are serialized.\r
+\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+ \r
+  If 32-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+  @param  Address The MMIO register to write.\r
+  @param  Value   The value to write to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioWrite32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT32                    Value\r
+  )\r
+{\r
+  //\r
+  // Make sure Address is aligned on a 32-bit boundary.\r
+  //\r
+  ASSERT ((Address & 3) == 0);\r
+  return (UINT32)MmioWriteWorker (Address, SMM_IO_UINT32, Value);\r
+}\r
+\r
+/**\r
+  Reads a 64-bit MMIO register.\r
+\r
+  Reads the 64-bit MMIO register specified by Address. The 64-bit read value is\r
+  returned. This function must guarantee that all MMIO read and write\r
+  operations are serialized.\r
+\r
+  If Address is not aligned on a 64-bit boundary, then ASSERT().\r
+ \r
+  If 64-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+  @param  Address The MMIO register to read.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioRead64 (\r
+  IN      UINTN                     Address\r
+  )\r
+{\r
+  //\r
+  // Make sure Address is aligned on a 64-bit boundary.\r
+  //\r
+  ASSERT ((Address & 7) == 0);\r
+  return (UINT64)MmioReadWorker (Address, SMM_IO_UINT64);\r
+}\r
+\r
+/**\r
+  Writes a 64-bit MMIO register.\r
+\r
+  Writes the 64-bit MMIO register specified by Address with the value specified\r
+  by Value and returns Value. This function must guarantee that all MMIO read\r
+  and write operations are serialized.\r
+\r
+  If Address is not aligned on a 64-bit boundary, then ASSERT().\r
+ \r
+  If 64-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+  @param  Address The MMIO register to write.\r
+  @param  Value   The value to write to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioWrite64 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT64                    Value\r
+  )\r
+{\r
+  //\r
+  // Make sure Address is aligned on a 64-bit boundary.\r
+  //\r
+  ASSERT ((Address & 7) == 0);\r
+  return (UINT64)MmioWriteWorker (Address, SMM_IO_UINT64, Value);\r
+}\r

diff --git a/MdePkg/Library/SmmIoLibCpuIo/IoLibMmioBuffer.c b/MdePkg/Library/SmmIoLibCpuIo/IoLibMmioBuffer.c
new file mode 100644 (file)
index 0000000..e4effa9
--- /dev/null
+++ b/MdePkg/Library/SmmIoLibCpuIo/IoLibMmioBuffer.c
@@ -0,0 +1,416 @@
+/** @file\r
+  I/O Library MMIO Buffer Functions.\r
+\r
+  Copyright (c) 2009, Intel Corporation<BR>\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+  Module Name:  IoLibMmioBuffer.c\r
+\r
+**/\r
+\r
+\r
+#include "SmmCpuIoLibInternal.h"\r
+\r
+/**\r
+  Copy data from MMIO region to system memory by using 8-bit access.\r
+\r
+  Copy data from MMIO region specified by starting address StartAddress\r
+  to system memory specified by Buffer by using 8-bit access. The total\r
+  number of byte to be copied is specified by Length. Buffer is returned.\r
+\r
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().\r
+  If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+\r
+  @param  StartAddress    Starting address for the MMIO region to be copied from.\r
+  @param  Length          Size in bytes of the copy.\r
+  @param  Buffer          Pointer to a system memory buffer receiving the data read.\r
+\r
+  @return Buffer\r
+\r
+**/\r
+UINT8 *\r
+EFIAPI\r
+MmioReadBuffer8 (\r
+  IN  UINTN       StartAddress,\r
+  IN  UINTN       Length,\r
+  OUT UINT8       *Buffer\r
+  )\r
+{\r
+  UINT8   *ReturnBuffer;\r
+\r
+  ASSERT ((Length - 1) <=  (MAX_ADDRESS - StartAddress));\r
+  ASSERT ((Length - 1) <=  (MAX_ADDRESS - (UINTN) Buffer));\r
+\r
+  ReturnBuffer = Buffer;\r
+\r
+  while (Length-- > 0) {\r
+    *(Buffer++) = MmioRead8 (StartAddress++);\r
+  }\r
+\r
+  return ReturnBuffer;\r
+}\r
+\r
+/**\r
+  Copy data from MMIO region to system memory by using 16-bit access.\r
+\r
+  Copy data from MMIO region specified by starting address StartAddress\r
+  to system memory specified by Buffer by using 16-bit access. The total\r
+  number of byte to be copied is specified by Length. Buffer is returned.\r
+\r
+  If StartAddress is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().\r
+  If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+  If Length is not aligned on a 16-bit boundary, then ASSERT().\r
+  \r
+  If Buffer is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+  @param  StartAddress    Starting address for the MMIO region to be copied from.\r
+  @param  Length          Size in bytes of the copy.\r
+  @param  Buffer          Pointer to a system memory buffer receiving the data read.\r
+\r
+  @return Buffer\r
+\r
+**/\r
+UINT16 *\r
+EFIAPI\r
+MmioReadBuffer16 (\r
+  IN  UINTN       StartAddress,\r
+  IN  UINTN       Length,\r
+  OUT UINT16      *Buffer\r
+  )\r
+{\r
+  UINT16    *ReturnBuffer;\r
+\r
+  ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);\r
+\r
+  ASSERT ((Length - 1) <=  (MAX_ADDRESS - StartAddress));\r
+  ASSERT ((Length - 1) <=  (MAX_ADDRESS - (UINTN) Buffer));\r
+\r
+  ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);\r
+  ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);\r
+\r
+  ReturnBuffer = Buffer;\r
+\r
+  while (Length > 0) {\r
+    *(Buffer++) = MmioRead16 (StartAddress);\r
+    StartAddress += sizeof (UINT16);\r
+    Length -= sizeof (UINT16);\r
+  }\r
+\r
+  return ReturnBuffer;\r
+}\r
+\r
+/**\r
+  Copy data from MMIO region to system memory by using 32-bit access.\r
+\r
+  Copy data from MMIO region specified by starting address StartAddress\r
+  to system memory specified by Buffer by using 32-bit access. The total\r
+  number of byte to be copied is specified by Length. Buffer is returned.\r
+\r
+  If StartAddress is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().\r
+  If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+  If Length is not aligned on a 32-bit boundary, then ASSERT().\r
+  If Buffer is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+  @param  StartAddress    Starting address for the MMIO region to be copied from.\r
+  @param  Length          Size in bytes of the copy.\r
+  @param  Buffer          Pointer to a system memory buffer receiving the data read.\r
+\r
+  @return Buffer\r
+\r
+**/\r
+UINT32 *\r
+EFIAPI\r
+MmioReadBuffer32 (\r
+  IN  UINTN       StartAddress,\r
+  IN  UINTN       Length,\r
+  OUT UINT32      *Buffer\r
+  )\r
+{\r
+  UINT32    *ReturnBuffer;\r
+\r
+  ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);\r
+\r
+  ASSERT ((Length - 1) <=  (MAX_ADDRESS - StartAddress));\r
+  ASSERT ((Length - 1) <=  (MAX_ADDRESS - (UINTN) Buffer));\r
+\r
+  ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);\r
+  ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);\r
+\r
+  ReturnBuffer = Buffer;\r
+\r
+  while (Length > 0) {\r
+    *(Buffer++) = MmioRead32 (StartAddress);\r
+    StartAddress += sizeof (UINT32);\r
+    Length -= sizeof (UINT32);\r
+  }\r
+\r
+  return ReturnBuffer;\r
+}\r
+\r
+/**\r
+  Copy data from MMIO region to system memory by using 64-bit access.\r
+\r
+  Copy data from MMIO region specified by starting address StartAddress\r
+  to system memory specified by Buffer by using 64-bit access. The total\r
+  number of byte to be copied is specified by Length. Buffer is returned.\r
+\r
+  If StartAddress is not aligned on a 64-bit boundary, then ASSERT().\r
+\r
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().\r
+  If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+  If Length is not aligned on a 64-bit boundary, then ASSERT().\r
+ \r
+  If Buffer is not aligned on a 64-bit boundary, then ASSERT().\r
+\r
+  @param  StartAddress    Starting address for the MMIO region to be copied from.\r
+  @param  Length          Size in bytes of the copy.\r
+  @param  Buffer          Pointer to a system memory buffer receiving the data read.\r
+\r
+  @return Buffer\r
+\r
+**/\r
+UINT64 *\r
+EFIAPI\r
+MmioReadBuffer64 (\r
+  IN  UINTN       StartAddress,\r
+  IN  UINTN       Length,\r
+  OUT UINT64      *Buffer\r
+  )\r
+{\r
+  UINT64    *ReturnBuffer;\r
+\r
+  ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);\r
+\r
+  ASSERT ((Length - 1) <=  (MAX_ADDRESS - StartAddress));\r
+  ASSERT ((Length - 1) <=  (MAX_ADDRESS - (UINTN) Buffer));\r
+\r
+  ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);\r
+  ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);\r
+\r
+  ReturnBuffer = Buffer;\r
+\r
+  while (Length > 0) {\r
+    *(Buffer++) = MmioRead64 (StartAddress);\r
+    StartAddress += sizeof (UINT64);\r
+    Length -= sizeof (UINT64);\r
+  }\r
+\r
+  return ReturnBuffer;\r
+}\r
+\r
+\r
+/**\r
+  Copy data from system memory to MMIO region by using 8-bit access.\r
+\r
+  Copy data from system memory specified by Buffer to MMIO region specified\r
+  by starting address StartAddress by using 8-bit access. The total number\r
+  of byte to be copied is specified by Length. Buffer is returned.\r
+\r
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().\r
+  If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().\r
+\r
+\r
+  @param  StartAddress    Starting address for the MMIO region to be copied to.\r
+  @param  Length     Size in bytes of the copy.\r
+  @param  Buffer          Pointer to a system memory buffer containing the data to write.\r
+\r
+  @return Buffer\r
+\r
+**/\r
+UINT8 *\r
+EFIAPI\r
+MmioWriteBuffer8 (\r
+  IN  UINTN         StartAddress,\r
+  IN  UINTN         Length,\r
+  IN  CONST UINT8   *Buffer\r
+  )\r
+{\r
+  VOID* ReturnBuffer;\r
+\r
+  ASSERT ((Length - 1) <=  (MAX_ADDRESS - StartAddress));\r
+  ASSERT ((Length - 1) <=  (MAX_ADDRESS - (UINTN) Buffer));\r
+\r
+  ReturnBuffer = (UINT8 *) Buffer;\r
+\r
+  while (Length-- > 0) {\r
+     MmioWrite8 (StartAddress++, *(Buffer++));\r
+  }\r
+\r
+  return ReturnBuffer;\r
+\r
+}\r
+\r
+/**\r
+  Copy data from system memory to MMIO region by using 16-bit access.\r
+\r
+  Copy data from system memory specified by Buffer to MMIO region specified\r
+  by starting address StartAddress by using 16-bit access. The total number\r
+  of byte to be copied is specified by Length. Buffer is returned.\r
+\r
+  If StartAddress is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().\r
+  If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().\r
+\r
+  If Length is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+  If Buffer is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+  @param  StartAddress    Starting address for the MMIO region to be copied to.\r
+  @param  Length     Size in bytes of the copy.\r
+  @param  Buffer          Pointer to a system memory buffer containing the data to write.\r
+\r
+  @return Buffer\r
+\r
+**/\r
+UINT16 *\r
+EFIAPI\r
+MmioWriteBuffer16 (\r
+  IN  UINTN        StartAddress,\r
+  IN  UINTN        Length,\r
+  IN  CONST UINT16 *Buffer\r
+  )\r
+{\r
+  UINT16    *ReturnBuffer;\r
+\r
+  ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);\r
+\r
+  ASSERT ((Length - 1) <=  (MAX_ADDRESS - StartAddress));\r
+  ASSERT ((Length - 1) <=  (MAX_ADDRESS - (UINTN) Buffer));\r
+\r
+  ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);\r
+  ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);\r
+\r
+  ReturnBuffer = (UINT16 *) Buffer;\r
+\r
+  while (Length > 0) {\r
+    MmioWrite16 (StartAddress, *(Buffer++));\r
+\r
+    StartAddress += sizeof (UINT16);\r
+    Length -= sizeof (UINT16);\r
+  }\r
+\r
+  return ReturnBuffer;\r
+}\r
+\r
+\r
+/**\r
+  Copy data from system memory to MMIO region by using 32-bit access.\r
+\r
+  Copy data from system memory specified by Buffer to MMIO region specified\r
+  by starting address StartAddress by using 32-bit access. The total number\r
+  of byte to be copied is specified by Length. Buffer is returned.\r
+\r
+  If StartAddress is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().\r
+  If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().\r
+\r
+  If Length is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+  If Buffer is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+  @param  StartAddress    Starting address for the MMIO region to be copied to.\r
+  @param  Length     Size in bytes of the copy.\r
+  @param  Buffer          Pointer to a system memory buffer containing the data to write.\r
+\r
+  @return Buffer\r
+\r
+**/\r
+UINT32 *\r
+EFIAPI\r
+MmioWriteBuffer32 (\r
+  IN  UINTN        StartAddress,\r
+  IN  UINTN        Length,\r
+  IN  CONST UINT32 *Buffer\r
+  )\r
+{\r
+  UINT32    *ReturnBuffer;\r
+\r
+  ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);\r
+\r
+  ASSERT ((Length - 1) <=  (MAX_ADDRESS - StartAddress));\r
+  ASSERT ((Length - 1) <=  (MAX_ADDRESS - (UINTN) Buffer));\r
+\r
+  ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);\r
+  ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);\r
+\r
+  ReturnBuffer = (UINT32 *) Buffer;\r
+\r
+  while (Length > 0) {\r
+    MmioWrite32 (StartAddress, *(Buffer++));\r
+\r
+    StartAddress += sizeof (UINT32);\r
+    Length -= sizeof (UINT32);\r
+  }\r
+\r
+  return ReturnBuffer;\r
+}\r
+\r
+/**\r
+  Copy data from system memory to MMIO region by using 64-bit access.\r
+\r
+  Copy data from system memory specified by Buffer to MMIO region specified\r
+  by starting address StartAddress by using 64-bit access. The total number\r
+  of byte to be copied is specified by Length. Buffer is returned.\r
+\r
+  If StartAddress is not aligned on a 64-bit boundary, then ASSERT().\r
+\r
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().\r
+  If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().\r
+\r
+  If Length is not aligned on a 64-bit boundary, then ASSERT().\r
+\r
+  If Buffer is not aligned on a 64-bit boundary, then ASSERT().\r
+\r
+  @param  StartAddress    Starting address for the MMIO region to be copied to.\r
+  @param  Length     Size in bytes of the copy.\r
+  @param  Buffer          Pointer to a system memory buffer containing the data to write.\r
+\r
+  @return Buffer\r
+\r
+**/\r
+UINT64 *\r
+EFIAPI\r
+MmioWriteBuffer64 (\r
+  IN  UINTN        StartAddress,\r
+  IN  UINTN        Length,\r
+  IN  CONST UINT64 *Buffer\r
+  )\r
+{\r
+  UINT64    *ReturnBuffer;\r
+\r
+  ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);\r
+\r
+  ASSERT ((Length - 1) <=  (MAX_ADDRESS - StartAddress));\r
+  ASSERT ((Length - 1) <=  (MAX_ADDRESS - (UINTN) Buffer));\r
+\r
+  ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);\r
+  ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);\r
+\r
+  ReturnBuffer = (UINT64 *) Buffer;\r
+\r
+  while (Length > 0) {\r
+    MmioWrite64 (StartAddress, *(Buffer++));\r
+\r
+    StartAddress += sizeof (UINT64);\r
+    Length -= sizeof (UINT64);\r
+  }\r
+\r
+  return ReturnBuffer;\r
+}\r
+\r

diff --git a/MdePkg/Library/SmmIoLibCpuIo/SmmCpuIoLibInternal.h b/MdePkg/Library/SmmIoLibCpuIo/SmmCpuIoLibInternal.h
new file mode 100644 (file)
index 0000000..e221bc8
--- /dev/null
+++ b/MdePkg/Library/SmmIoLibCpuIo/SmmCpuIoLibInternal.h
@@ -0,0 +1,121 @@
+/** @file\r
+  Internal include file of SMM CPU IO Library.\r
+  It includes all necessary protocol/library class's header file\r
+  for implementation of IoLib library instance. It is included \r
+  all source code of this library instance.\r
+  \r
+  Copyright (c) 2009, Intel Corporation\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+  Module Name:  DxeCpuIoLibInternal.h\r
+\r
+**/\r
+\r
+#ifndef _SMM_CPUIO_LIB_INTERNAL_H_\r
+#define _SMM_CPUIO_LIB_INTERNAL_H_\r
+\r
+\r
+#include <PiSmm.h>\r
+#include <Protocol/SmmCpuIo.h>\r
+#include <Protocol/SmmPciRootBridgeIo.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/SmmServicesTableLib.h>\r
+\r
+\r
+/**\r
+  Reads registers in the EFI CPU I/O space.\r
+\r
+  Reads the I/O port specified by Port with registers width specified by Width.\r
+  The read value is returned. If such operations are not supported, then ASSERT().\r
+  This function must guarantee that all I/O read and write operations are serialized.\r
+\r
+  @param  Port          The base address of the I/O operation.\r
+                        The caller is responsible for aligning the Address if required.\r
+  @param  Width         The width of the I/O operation.\r
+\r
+  @return Data read from registers in the EFI CPU I/O space.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoReadWorker (\r
+  IN      UINTN                     Port,\r
+  IN      EFI_SMM_IO_WIDTH          Width\r
+  );\r
+\r
+/**\r
+  Writes registers in the EFI CPU I/O space.\r
+\r
+  Writes the I/O port specified by Port with registers width and value specified by Width\r
+  and Data respectively.  Data is returned. If such operations are not supported, then ASSERT().\r
+  This function must guarantee that all I/O read and write operations are serialized.\r
+\r
+  @param  Port          The base address of the I/O operation.\r
+                        The caller is responsible for aligning the Address if required.\r
+  @param  Width         The width of the I/O operation.\r
+  @param  Data          The value to write to the I/O port.\r
+\r
+  @return The paramter of Data.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoWriteWorker (\r
+  IN      UINTN                     Port,\r
+  IN      EFI_SMM_IO_WIDTH          Width,\r
+  IN      UINT64                    Data\r
+  );\r
+\r
+/**\r
+  Reads memory-mapped registers in the EFI system memory space.\r
+\r
+  Reads the MMIO registers specified by Address with registers width specified by Width.\r
+  The read value is returned. If such operations are not supported, then ASSERT().\r
+  This function must guarantee that all MMIO read and write operations are serialized.\r
+\r
+  @param  Address       The MMIO register to read.\r
+                        The caller is responsible for aligning the Address if required.\r
+  @param  Width         The width of the I/O operation.\r
+\r
+  @return Data read from registers in the EFI system memory space.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioReadWorker (\r
+  IN      UINTN                     Address,\r
+  IN      EFI_SMM_IO_WIDTH          Width\r
+  );\r
+\r
+/**\r
+  Writes memory-mapped registers in the EFI system memory space.\r
+\r
+  Writes the MMIO registers specified by Address with registers width and value specified by Width\r
+  and Data respectively. Data is returned. If such operations are not supported, then ASSERT().\r
+  This function must guarantee that all MMIO read and write operations are serialized.\r
+\r
+  @param  Address       The MMIO register to read.\r
+                        The caller is responsible for aligning the Address if required.\r
+  @param  Width         The width of the I/O operation.\r
+  @param  Data          The value to write to the I/O port.\r
+  \r
+  @return Data read from registers in the EFI system memory space.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioWriteWorker (\r
+  IN      UINTN                     Address,\r
+  IN      EFI_SMM_IO_WIDTH          Width,\r
+  IN      UINT64                    Data\r
+  );\r
+\r
+#endif\r

diff --git a/MdePkg/Library/SmmIoLibCpuIo/SmmIoLibCpuIo.inf b/MdePkg/Library/SmmIoLibCpuIo/SmmIoLibCpuIo.inf
new file mode 100644 (file)
index 0000000..7be09dc
--- /dev/null
+++ b/MdePkg/Library/SmmIoLibCpuIo/SmmIoLibCpuIo.inf
@@ -0,0 +1,56 @@
+#/** @file\r
+# Component description file for Cpu Io SMM Io Library.\r
+#\r
+# I/O Library implementation that uses the CPU I/O Protocol for I/O\r
+#  and MMIO operations.\r
+# Copyright (c) 2009, Intel Corporation.\r
+#\r
+#  All rights reserved. This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution. The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = SmmIoLibCpuIo\r
+  FILE_GUID                      = DEEEA15E-4A77-4513-BA75-71D26FEF78A1\r
+  MODULE_TYPE                    = DXE_SMM_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = IoLib|DXE_SMM_DRIVER SMM_CORE\r
+  EFI_SPECIFICATION_VERSION      = 0x00020000\r
+  PI_SPECIFICATION_VERSION       = 0x0001000A\r
+  \r
+  CONSTRUCTOR                    = IoLibConstructor\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64\r
+#\r
+\r
+[Sources.common]\r
+  IoLibMmioBuffer.c\r
+  SmmCpuIoLibInternal.h\r
+  IoHighLevel.c\r
+  IoLib.c\r
+\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+  BaseLib\r
+  DebugLib\r
+  SmmServicesTableLib\r
+\r
+[Protocols]\r
+  gEfiSmmCpuIoProtocolGuid                         ## CONSUMES\r
+  gEfiSmmPciRootBridgeIoProtocolGuid               ## CONSUMES\r
+\r
+[Depex]\r
+  gEfiSmmCpuIoProtocolGuid OR gEfiSmmPciRootBridgeIoProtocolGuid      
\ No newline at end of file

diff --git a/MdePkg/Library/SmmPciLibPciRootBridgeIo/PciLib.c b/MdePkg/Library/SmmPciLibPciRootBridgeIo/PciLib.c
new file mode 100644 (file)
index 0000000..5e16327
--- /dev/null
+++ b/MdePkg/Library/SmmPciLibPciRootBridgeIo/PciLib.c
@@ -0,0 +1,1420 @@
+/** @file\r
+  PCI Library using SMM PCI Root Bridge I/O Protocol.\r
+\r
+  Copyright (c) 2009, Intel Corporation All rights\r
+  reserved. This program and the accompanying materials are\r
+  licensed and made available under the terms and conditions of\r
+  the BSD License which accompanies this distribution.  The full\r
+  text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+  \r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+#include <PiSmm.h>\r
+#include <Protocol/SmmCpuIo.h>\r
+#include <Protocol/SmmPciRootBridgeIo.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/SmmServicesTableLib.h>\r
+\r
+\r
+/**\r
+  Assert the validity of a PCI address. A valid PCI address should contain 1's\r
+  only in the low 28 bits.\r
+\r
+  @param  A The address to validate.\r
+  @param  M Additional bits to assert to be zero.\r
+\r
+**/\r
+#define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r
+  ASSERT (((A) & (~0xfffffff | (M))) == 0)\r
+\r
+/**\r
+  Translate PCI Lib address into format of PCI Root Bridge I/O Protocol.\r
+\r
+  @param  A  Address that encodes the PCI Bus, Device, Function and\r
+             Register.\r
+\r
+**/\r
+#define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \\r
+  ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r
+\r
+//\r
+// Global varible to cache pointer to PCI Root Bridge I/O protocol.\r
+//\r
+EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL      *mSmmPciRootBridgeIo = NULL; \r
+\r
+/**\r
+  The constructor function caches the pointer to PCI Root Bridge I/O protocol.\r
+  \r
+  The constructor function locates PCI Root Bridge I/O protocol from protocol database.\r
+  It will ASSERT() if that operation fails and it will always return EFI_SUCCESS. \r
+\r
+  @param  ImageHandle   The firmware allocated handle for the EFI image.\r
+  @param  SystemTable   A pointer to the EFI System Table.\r
+  \r
+  @retval EFI_SUCCESS   The constructor always returns EFI_SUCCESS.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciLibConstructor (\r
+  IN EFI_HANDLE                ImageHandle,\r
+  IN EFI_SYSTEM_TABLE          *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  \r
+  Status = gSmst->SmmLocateProtocol (&gEfiSmmPciRootBridgeIoProtocolGuid, NULL, (VOID**) &mSmmPciRootBridgeIo);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (mSmmPciRootBridgeIo != NULL);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Internal worker function to read a PCI configuration register.\r
+\r
+  This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() service.\r
+  It reads and returns the PCI configuration register specified by Address,\r
+  the width of data is specified by Width.\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+  @param  Width   Width of data to read\r
+\r
+  @return The value read from the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+SmmPciLibPciRootBridgeIoReadWorker (\r
+  IN    UINTN                                  Address,\r
+  IN    EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width\r
+  )\r
+{\r
+  UINT32  Data;\r
+\r
+  mSmmPciRootBridgeIo->Pci.Read (\r
+                          mSmmPciRootBridgeIo,\r
+                          Width,\r
+                          PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
+                          1,\r
+                          &Data\r
+                          );\r
+\r
+  return Data;\r
+}\r
+\r
+/**\r
+  Internal worker function to writes a PCI configuration register.\r
+\r
+  This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.\r
+  It writes the PCI configuration register specified by Address with the\r
+  value specified by Data. The width of data is specifed by Width.\r
+  Data is returned.\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+  @param  Width   Width of data to write\r
+  @param  Data    The value to write.\r
+\r
+  @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+SmmPciLibPciRootBridgeIoWriteWorker (\r
+  IN    UINTN                                  Address,\r
+  IN    EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
+  IN    UINT32                                 Data\r
+  )\r
+{\r
+  mSmmPciRootBridgeIo->Pci.Write (\r
+                          mSmmPciRootBridgeIo,\r
+                          Width,\r
+                          PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
+                          1,\r
+                          &Data\r
+                          );\r
+  return Data;\r
+}\r
+\r
+/**\r
+  Registers a PCI device so PCI configuration registers may be accessed after \r
+  SetVirtualAddressMap().\r
+  \r
+  Registers the PCI device specified by Address so all the PCI configuration registers \r
+  associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r
+  \r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+  \r
+  @retval RETURN_SUCCESS           The PCI device was registered for runtime access.\r
+  @retval RETURN_UNSUPPORTED       An attempt was made to call this function \r
+                                   after ExitBootServices().\r
+  @retval RETURN_UNSUPPORTED       The resources required to access the PCI device\r
+                                   at runtime could not be mapped.\r
+  @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to\r
+                                   complete the registration.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PciRegisterForRuntimeAccess (\r
+  IN UINTN  Address\r
+  )\r
+{\r
+  ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
+  return RETURN_UNSUPPORTED;\r
+}\r
+\r
+/**\r
+  Reads an 8-bit PCI configuration register.\r
+\r
+  Reads and returns the 8-bit PCI configuration register specified by Address.\r
+  This function must guarantee that all PCI read and write operations are\r
+  serialized.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+\r
+  @return The read value from the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciRead8 (\r
+  IN      UINTN                     Address\r
+  )\r
+{\r
+  ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
+\r
+  return (UINT8) SmmPciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);\r
+}\r
+\r
+/**\r
+  Writes an 8-bit PCI configuration register.\r
+\r
+  Writes the 8-bit PCI configuration register specified by Address with the\r
+  value specified by Value. Value is returned. This function must guarantee\r
+  that all PCI read and write operations are serialized.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+  @param  Value   The value to write.\r
+\r
+  @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciWrite8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT8                     Value\r
+  )\r
+{\r
+  ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
+\r
+  return (UINT8) SmmPciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);\r
+}\r
+\r
+/**\r
+  Performs a bitwise OR of an 8-bit PCI configuration register with\r
+  an 8-bit value.\r
+\r
+  Reads the 8-bit PCI configuration register specified by Address, performs a\r
+  bitwise OR between the read result and the value specified by\r
+  OrData, and writes the result to the 8-bit PCI configuration register\r
+  specified by Address. The value written to the PCI configuration register is\r
+  returned. This function must guarantee that all PCI read and write operations\r
+  are serialized.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+  @param  OrData  The value to OR with the PCI configuration register.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciOr8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT8                     OrData\r
+  )\r
+{\r
+  return PciWrite8 (Address, (UINT8) (PciRead8 (Address) | OrData));\r
+}\r
+\r
+/**\r
+  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
+  value.\r
+\r
+  Reads the 8-bit PCI configuration register specified by Address, performs a\r
+  bitwise AND between the read result and the value specified by AndData, and\r
+  writes the result to the 8-bit PCI configuration register specified by\r
+  Address. The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are\r
+  serialized.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+  @param  AndData The value to AND with the PCI configuration register.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciAnd8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT8                     AndData\r
+  )\r
+{\r
+  return PciWrite8 (Address, (UINT8) (PciRead8 (Address) & AndData));\r
+}\r
+\r
+/**\r
+  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
+  value, followed a  bitwise OR with another 8-bit value.\r
+\r
+  Reads the 8-bit PCI configuration register specified by Address, performs a\r
+  bitwise AND between the read result and the value specified by AndData,\r
+  performs a bitwise OR between the result of the AND operation and\r
+  the value specified by OrData, and writes the result to the 8-bit PCI\r
+  configuration register specified by Address. The value written to the PCI\r
+  configuration register is returned. This function must guarantee that all PCI\r
+  read and write operations are serialized.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+  @param  AndData The value to AND with the PCI configuration register.\r
+  @param  OrData  The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciAndThenOr8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT8                     AndData,\r
+  IN      UINT8                     OrData\r
+  )\r
+{\r
+  return PciWrite8 (Address, (UINT8) ((PciRead8 (Address) & AndData) | OrData));\r
+}\r
+\r
+/**\r
+  Reads a bit field of a PCI configuration register.\r
+\r
+  Reads the bit field in an 8-bit PCI configuration register. The bit field is\r
+  specified by the StartBit and the EndBit. The value of the bit field is\r
+  returned.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If StartBit is greater than 7, then ASSERT().\r
+  If EndBit is greater than 7, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   PCI configuration register to read.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..7.\r
+\r
+  @return The value of the bit field read from the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciBitFieldRead8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit\r
+  )\r
+{\r
+  return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+  Writes a bit field to a PCI configuration register.\r
+\r
+  Writes Value to the bit field of the PCI configuration register. The bit\r
+  field is specified by the StartBit and the EndBit. All other bits in the\r
+  destination PCI configuration register are preserved. The new value of the\r
+  8-bit register is returned.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If StartBit is greater than 7, then ASSERT().\r
+  If EndBit is greater than 7, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   PCI configuration register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  Value     New value of the bit field.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciBitFieldWrite8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT8                     Value\r
+  )\r
+{\r
+  return PciWrite8 (\r
+           Address,\r
+           BitFieldWrite8 (PciRead8 (Address), StartBit, EndBit, Value)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r
+  writes the result back to the bit field in the 8-bit port.\r
+\r
+  Reads the 8-bit PCI configuration register specified by Address, performs a\r
+  bitwise OR between the read result and the value specified by\r
+  OrData, and writes the result to the 8-bit PCI configuration register\r
+  specified by Address. The value written to the PCI configuration register is\r
+  returned. This function must guarantee that all PCI read and write operations\r
+  are serialized. Extra left bits in OrData are stripped.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If StartBit is greater than 7, then ASSERT().\r
+  If EndBit is greater than 7, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   PCI configuration register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  OrData    The value to OR with the PCI configuration register.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciBitFieldOr8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT8                     OrData\r
+  )\r
+{\r
+  return PciWrite8 (\r
+           Address,\r
+           BitFieldOr8 (PciRead8 (Address), StartBit, EndBit, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r
+  AND, and writes the result back to the bit field in the 8-bit register.\r
+\r
+  Reads the 8-bit PCI configuration register specified by Address, performs a\r
+  bitwise AND between the read result and the value specified by AndData, and\r
+  writes the result to the 8-bit PCI configuration register specified by\r
+  Address. The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are\r
+  serialized. Extra left bits in AndData are stripped.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If StartBit is greater than 7, then ASSERT().\r
+  If EndBit is greater than 7, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   PCI configuration register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  AndData   The value to AND with the PCI configuration register.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciBitFieldAnd8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT8                     AndData\r
+  )\r
+{\r
+  return PciWrite8 (\r
+           Address,\r
+           BitFieldAnd8 (PciRead8 (Address), StartBit, EndBit, AndData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
+  bitwise OR, and writes the result back to the bit field in the\r
+  8-bit port.\r
+\r
+  Reads the 8-bit PCI configuration register specified by Address, performs a\r
+  bitwise AND followed by a bitwise OR between the read result and\r
+  the value specified by AndData, and writes the result to the 8-bit PCI\r
+  configuration register specified by Address. The value written to the PCI\r
+  configuration register is returned. This function must guarantee that all PCI\r
+  read and write operations are serialized. Extra left bits in both AndData and\r
+  OrData are stripped.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If StartBit is greater than 7, then ASSERT().\r
+  If EndBit is greater than 7, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   PCI configuration register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..7.\r
+  @param  AndData   The value to AND with the PCI configuration register.\r
+  @param  OrData    The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciBitFieldAndThenOr8 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT8                     AndData,\r
+  IN      UINT8                     OrData\r
+  )\r
+{\r
+  return PciWrite8 (\r
+           Address,\r
+           BitFieldAndThenOr8 (PciRead8 (Address), StartBit, EndBit, AndData, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a 16-bit PCI configuration register.\r
+\r
+  Reads and returns the 16-bit PCI configuration register specified by Address.\r
+  This function must guarantee that all PCI read and write operations are\r
+  serialized.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+\r
+  @return The read value from the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciRead16 (\r
+  IN      UINTN                     Address\r
+  )\r
+{\r
+  ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
+\r
+  return (UINT16) SmmPciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);\r
+}\r
+\r
+/**\r
+  Writes a 16-bit PCI configuration register.\r
+\r
+  Writes the 16-bit PCI configuration register specified by Address with the\r
+  value specified by Value. Value is returned. This function must guarantee\r
+  that all PCI read and write operations are serialized.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+  @param  Value   The value to write.\r
+\r
+  @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciWrite16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT16                    Value\r
+  )\r
+{\r
+  ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
+\r
+  return (UINT16) SmmPciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);\r
+}\r
+\r
+/**\r
+  Performs a bitwise OR of a 16-bit PCI configuration register with\r
+  a 16-bit value.\r
+\r
+  Reads the 16-bit PCI configuration register specified by Address, performs a\r
+  bitwise OR between the read result and the value specified by\r
+  OrData, and writes the result to the 16-bit PCI configuration register\r
+  specified by Address. The value written to the PCI configuration register is\r
+  returned. This function must guarantee that all PCI read and write operations\r
+  are serialized.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+  @param  OrData  The value to OR with the PCI configuration register.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciOr16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT16                    OrData\r
+  )\r
+{\r
+  return PciWrite16 (Address, (UINT16) (PciRead16 (Address) | OrData));\r
+}\r
+\r
+/**\r
+  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
+  value.\r
+\r
+  Reads the 16-bit PCI configuration register specified by Address, performs a\r
+  bitwise AND between the read result and the value specified by AndData, and\r
+  writes the result to the 16-bit PCI configuration register specified by\r
+  Address. The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are\r
+  serialized.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+  @param  AndData The value to AND with the PCI configuration register.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciAnd16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT16                    AndData\r
+  )\r
+{\r
+  return PciWrite16 (Address, (UINT16) (PciRead16 (Address) & AndData));\r
+}\r
+\r
+/**\r
+  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
+  value, followed a  bitwise OR with another 16-bit value.\r
+\r
+  Reads the 16-bit PCI configuration register specified by Address, performs a\r
+  bitwise AND between the read result and the value specified by AndData,\r
+  performs a bitwise OR between the result of the AND operation and\r
+  the value specified by OrData, and writes the result to the 16-bit PCI\r
+  configuration register specified by Address. The value written to the PCI\r
+  configuration register is returned. This function must guarantee that all PCI\r
+  read and write operations are serialized.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+  @param  AndData The value to AND with the PCI configuration register.\r
+  @param  OrData  The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciAndThenOr16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT16                    AndData,\r
+  IN      UINT16                    OrData\r
+  )\r
+{\r
+  return PciWrite16 (Address, (UINT16) ((PciRead16 (Address) & AndData) | OrData));\r
+}\r
+\r
+/**\r
+  Reads a bit field of a PCI configuration register.\r
+\r
+  Reads the bit field in a 16-bit PCI configuration register. The bit field is\r
+  specified by the StartBit and the EndBit. The value of the bit field is\r
+  returned.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+  If StartBit is greater than 15, then ASSERT().\r
+  If EndBit is greater than 15, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   PCI configuration register to read.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..15.\r
+\r
+  @return The value of the bit field read from the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciBitFieldRead16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit\r
+  )\r
+{\r
+  return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+  Writes a bit field to a PCI configuration register.\r
+\r
+  Writes Value to the bit field of the PCI configuration register. The bit\r
+  field is specified by the StartBit and the EndBit. All other bits in the\r
+  destination PCI configuration register are preserved. The new value of the\r
+  16-bit register is returned.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+  If StartBit is greater than 15, then ASSERT().\r
+  If EndBit is greater than 15, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   PCI configuration register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  Value     New value of the bit field.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciBitFieldWrite16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT16                    Value\r
+  )\r
+{\r
+  return PciWrite16 (\r
+           Address,\r
+           BitFieldWrite16 (PciRead16 (Address), StartBit, EndBit, Value)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r
+  writes the result back to the bit field in the 16-bit port.\r
+\r
+  Reads the 16-bit PCI configuration register specified by Address, performs a\r
+  bitwise OR between the read result and the value specified by\r
+  OrData, and writes the result to the 16-bit PCI configuration register\r
+  specified by Address. The value written to the PCI configuration register is\r
+  returned. This function must guarantee that all PCI read and write operations\r
+  are serialized. Extra left bits in OrData are stripped.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+  If StartBit is greater than 15, then ASSERT().\r
+  If EndBit is greater than 15, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   PCI configuration register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  OrData    The value to OR with the PCI configuration register.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciBitFieldOr16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT16                    OrData\r
+  )\r
+{\r
+  return PciWrite16 (\r
+           Address,\r
+           BitFieldOr16 (PciRead16 (Address), StartBit, EndBit, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
+  AND, and writes the result back to the bit field in the 16-bit register.\r
+\r
+  Reads the 16-bit PCI configuration register specified by Address, performs a\r
+  bitwise AND between the read result and the value specified by AndData, and\r
+  writes the result to the 16-bit PCI configuration register specified by\r
+  Address. The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are\r
+  serialized. Extra left bits in AndData are stripped.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+  If StartBit is greater than 15, then ASSERT().\r
+  If EndBit is greater than 15, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   PCI configuration register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  AndData   The value to AND with the PCI configuration register.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciBitFieldAnd16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT16                    AndData\r
+  )\r
+{\r
+  return PciWrite16 (\r
+           Address,\r
+           BitFieldAnd16 (PciRead16 (Address), StartBit, EndBit, AndData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
+  bitwise OR, and writes the result back to the bit field in the\r
+  16-bit port.\r
+\r
+  Reads the 16-bit PCI configuration register specified by Address, performs a\r
+  bitwise AND followed by a bitwise OR between the read result and\r
+  the value specified by AndData, and writes the result to the 16-bit PCI\r
+  configuration register specified by Address. The value written to the PCI\r
+  configuration register is returned. This function must guarantee that all PCI\r
+  read and write operations are serialized. Extra left bits in both AndData and\r
+  OrData are stripped.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+  If StartBit is greater than 15, then ASSERT().\r
+  If EndBit is greater than 15, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   PCI configuration register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..15.\r
+  @param  AndData   The value to AND with the PCI configuration register.\r
+  @param  OrData    The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciBitFieldAndThenOr16 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT16                    AndData,\r
+  IN      UINT16                    OrData\r
+  )\r
+{\r
+  return PciWrite16 (\r
+           Address,\r
+           BitFieldAndThenOr16 (PciRead16 (Address), StartBit, EndBit, AndData, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a 32-bit PCI configuration register.\r
+\r
+  Reads and returns the 32-bit PCI configuration register specified by Address.\r
+  This function must guarantee that all PCI read and write operations are\r
+  serialized.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+\r
+  @return The read value from the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciRead32 (\r
+  IN      UINTN                     Address\r
+  )\r
+{\r
+  ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
+\r
+  return SmmPciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint32);\r
+}\r
+\r
+/**\r
+  Writes a 32-bit PCI configuration register.\r
+\r
+  Writes the 32-bit PCI configuration register specified by Address with the\r
+  value specified by Value. Value is returned. This function must guarantee\r
+  that all PCI read and write operations are serialized.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+  @param  Value   The value to write.\r
+\r
+  @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciWrite32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT32                    Value\r
+  )\r
+{\r
+  ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
+\r
+  return SmmPciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Value);\r
+}\r
+\r
+/**\r
+  Performs a bitwise OR of a 32-bit PCI configuration register with\r
+  a 32-bit value.\r
+\r
+  Reads the 32-bit PCI configuration register specified by Address, performs a\r
+  bitwise OR between the read result and the value specified by\r
+  OrData, and writes the result to the 32-bit PCI configuration register\r
+  specified by Address. The value written to the PCI configuration register is\r
+  returned. This function must guarantee that all PCI read and write operations\r
+  are serialized.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+  @param  OrData  The value to OR with the PCI configuration register.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciOr32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT32                    OrData\r
+  )\r
+{\r
+  return PciWrite32 (Address, PciRead32 (Address) | OrData);\r
+}\r
+\r
+/**\r
+  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
+  value.\r
+\r
+  Reads the 32-bit PCI configuration register specified by Address, performs a\r
+  bitwise AND between the read result and the value specified by AndData, and\r
+  writes the result to the 32-bit PCI configuration register specified by\r
+  Address. The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are\r
+  serialized.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+  @param  AndData The value to AND with the PCI configuration register.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciAnd32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT32                    AndData\r
+  )\r
+{\r
+  return PciWrite32 (Address, PciRead32 (Address) & AndData);\r
+}\r
+\r
+/**\r
+  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
+  value, followed a  bitwise OR with another 32-bit value.\r
+\r
+  Reads the 32-bit PCI configuration register specified by Address, performs a\r
+  bitwise AND between the read result and the value specified by AndData,\r
+  performs a bitwise OR between the result of the AND operation and\r
+  the value specified by OrData, and writes the result to the 32-bit PCI\r
+  configuration register specified by Address. The value written to the PCI\r
+  configuration register is returned. This function must guarantee that all PCI\r
+  read and write operations are serialized.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+  @param  AndData The value to AND with the PCI configuration register.\r
+  @param  OrData  The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciAndThenOr32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINT32                    AndData,\r
+  IN      UINT32                    OrData\r
+  )\r
+{\r
+  return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);\r
+}\r
+\r
+/**\r
+  Reads a bit field of a PCI configuration register.\r
+\r
+  Reads the bit field in a 32-bit PCI configuration register. The bit field is\r
+  specified by the StartBit and the EndBit. The value of the bit field is\r
+  returned.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+  If StartBit is greater than 31, then ASSERT().\r
+  If EndBit is greater than 31, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   PCI configuration register to read.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..31.\r
+\r
+  @return The value of the bit field read from the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciBitFieldRead32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit\r
+  )\r
+{\r
+  return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+  Writes a bit field to a PCI configuration register.\r
+\r
+  Writes Value to the bit field of the PCI configuration register. The bit\r
+  field is specified by the StartBit and the EndBit. All other bits in the\r
+  destination PCI configuration register are preserved. The new value of the\r
+  32-bit register is returned.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+  If StartBit is greater than 31, then ASSERT().\r
+  If EndBit is greater than 31, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   PCI configuration register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  Value     New value of the bit field.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciBitFieldWrite32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT32                    Value\r
+  )\r
+{\r
+  return PciWrite32 (\r
+           Address,\r
+           BitFieldWrite32 (PciRead32 (Address), StartBit, EndBit, Value)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r
+  writes the result back to the bit field in the 32-bit port.\r
+\r
+  Reads the 32-bit PCI configuration register specified by Address, performs a\r
+  bitwise OR between the read result and the value specified by\r
+  OrData, and writes the result to the 32-bit PCI configuration register\r
+  specified by Address. The value written to the PCI configuration register is\r
+  returned. This function must guarantee that all PCI read and write operations\r
+  are serialized. Extra left bits in OrData are stripped.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+  If StartBit is greater than 31, then ASSERT().\r
+  If EndBit is greater than 31, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   PCI configuration register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  OrData    The value to OR with the PCI configuration register.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciBitFieldOr32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT32                    OrData\r
+  )\r
+{\r
+  return PciWrite32 (\r
+           Address,\r
+           BitFieldOr32 (PciRead32 (Address), StartBit, EndBit, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
+  AND, and writes the result back to the bit field in the 32-bit register.\r
+\r
+  Reads the 32-bit PCI configuration register specified by Address, performs a\r
+  bitwise AND between the read result and the value specified by AndData, and\r
+  writes the result to the 32-bit PCI configuration register specified by\r
+  Address. The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are\r
+  serialized. Extra left bits in AndData are stripped.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+  If StartBit is greater than 31, then ASSERT().\r
+  If EndBit is greater than 31, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   PCI configuration register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  AndData   The value to AND with the PCI configuration register.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciBitFieldAnd32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT32                    AndData\r
+  )\r
+{\r
+  return PciWrite32 (\r
+           Address,\r
+           BitFieldAnd32 (PciRead32 (Address), StartBit, EndBit, AndData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
+  bitwise OR, and writes the result back to the bit field in the\r
+  32-bit port.\r
+\r
+  Reads the 32-bit PCI configuration register specified by Address, performs a\r
+  bitwise AND followed by a bitwise OR between the read result and\r
+  the value specified by AndData, and writes the result to the 32-bit PCI\r
+  configuration register specified by Address. The value written to the PCI\r
+  configuration register is returned. This function must guarantee that all PCI\r
+  read and write operations are serialized. Extra left bits in both AndData and\r
+  OrData are stripped.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+  If StartBit is greater than 31, then ASSERT().\r
+  If EndBit is greater than 31, then ASSERT().\r
+  If EndBit is less than StartBit, then ASSERT().\r
+\r
+  @param  Address   PCI configuration register to write.\r
+  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
+                    Range 0..31.\r
+  @param  AndData   The value to AND with the PCI configuration register.\r
+  @param  OrData    The value to OR with the result of the AND operation.\r
+\r
+  @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciBitFieldAndThenOr32 (\r
+  IN      UINTN                     Address,\r
+  IN      UINTN                     StartBit,\r
+  IN      UINTN                     EndBit,\r
+  IN      UINT32                    AndData,\r
+  IN      UINT32                    OrData\r
+  )\r
+{\r
+  return PciWrite32 (\r
+           Address,\r
+           BitFieldAndThenOr32 (PciRead32 (Address), StartBit, EndBit, AndData, OrData)\r
+           );\r
+}\r
+\r
+/**\r
+  Reads a range of PCI configuration registers into a caller supplied buffer.\r
+\r
+  Reads the range of PCI configuration registers specified by StartAddress and\r
+  Size into the buffer specified by Buffer. This function only allows the PCI\r
+  configuration registers from a single PCI function to be read. Size is\r
+  returned. When possible 32-bit PCI configuration read cycles are used to read\r
+  from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
+  and 16-bit PCI configuration read cycles may be used at the beginning and the\r
+  end of the range.\r
+\r
+  If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+  If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
+  If Size > 0 and Buffer is NULL, then ASSERT().\r
+\r
+  @param  StartAddress  Starting address that encodes the PCI Bus, Device,\r
+                        Function and Register.\r
+  @param  Size          Size in bytes of the transfer.\r
+  @param  Buffer        Pointer to a buffer receiving the data read.\r
+\r
+  @return Size\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+PciReadBuffer (\r
+  IN      UINTN                     StartAddress,\r
+  IN      UINTN                     Size,\r
+  OUT     VOID                      *Buffer\r
+  )\r
+{\r
+  UINTN                             ReturnValue;\r
+\r
+  ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
+  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
+\r
+  if (Size == 0) {\r
+    return Size;\r
+  }\r
+\r
+  ASSERT (Buffer != NULL);\r
+\r
+  //\r
+  // Save Size for return\r
+  //\r
+  ReturnValue = Size;\r
+\r
+  if ((StartAddress & BIT0) != 0) {\r
+    //\r
+    // Read a byte if StartAddress is byte aligned\r
+    //\r
+    *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r
+    StartAddress += sizeof (UINT8);\r
+    Size -= sizeof (UINT8);\r
+    Buffer = (UINT8*)Buffer + 1;\r
+  }\r
+\r
+  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+    //\r
+    // Read a word if StartAddress is word aligned\r
+    //\r
+    WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r
+    StartAddress += sizeof (UINT16);\r
+    Size -= sizeof (UINT16);\r
+    Buffer = (UINT16*)Buffer + 1;\r
+  }\r
+\r
+  while (Size >= sizeof (UINT32)) {\r
+    //\r
+    // Read as many double words as possible\r
+    //\r
+    WriteUnaligned32 (Buffer, PciRead32 (StartAddress));\r
+    StartAddress += sizeof (UINT32);\r
+    Size -= sizeof (UINT32);\r
+    Buffer = (UINT32*)Buffer + 1;\r
+  }\r
+\r
+  if (Size >= sizeof (UINT16)) {\r
+    //\r
+    // Read the last remaining word if exist\r
+    //\r
+    WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r
+    StartAddress += sizeof (UINT16);\r
+    Size -= sizeof (UINT16);\r
+    Buffer = (UINT16*)Buffer + 1;\r
+  }\r
+\r
+  if (Size >= sizeof (UINT8)) {\r
+    //\r
+    // Read the last remaining byte if exist\r
+    //\r
+    *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r
+  }\r
+\r
+  return ReturnValue;\r
+}\r
+\r
+/**\r
+  Copies the data in a caller supplied buffer to a specified range of PCI\r
+  configuration space.\r
+\r
+  Writes the range of PCI configuration registers specified by StartAddress and\r
+  Size from the buffer specified by Buffer. This function only allows the PCI\r
+  configuration registers from a single PCI function to be written. Size is\r
+  returned. When possible 32-bit PCI configuration write cycles are used to\r
+  write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
+  8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
+  and the end of the range.\r
+\r
+  If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+  If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
+  If Size > 0 and Buffer is NULL, then ASSERT().\r
+\r
+  @param  StartAddress  Starting address that encodes the PCI Bus, Device,\r
+                        Function and Register.\r
+  @param  Size          Size in bytes of the transfer.\r
+  @param  Buffer        Pointer to a buffer containing the data to write.\r
+\r
+  @return Size written to StartAddress.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+PciWriteBuffer (\r
+  IN      UINTN                     StartAddress,\r
+  IN      UINTN                     Size,\r
+  IN      VOID                      *Buffer\r
+  )\r
+{\r
+  UINTN                             ReturnValue;\r
+\r
+  ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
+  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
+\r
+  if (Size == 0) {\r
+    return 0;\r
+  }\r
+\r
+  ASSERT (Buffer != NULL);\r
+\r
+  //\r
+  // Save Size for return\r
+  //\r
+  ReturnValue = Size;\r
+\r
+  if ((StartAddress & BIT0) != 0) {\r
+    //\r
+    // Write a byte if StartAddress is byte aligned\r
+    //\r
+    PciWrite8 (StartAddress, *(UINT8*)Buffer);\r
+    StartAddress += sizeof (UINT8);\r
+    Size -= sizeof (UINT8);\r
+    Buffer = (UINT8*)Buffer + 1;\r
+  }\r
+\r
+  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+    //\r
+    // Write a word if StartAddress is word aligned\r
+    //\r
+    PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
+    StartAddress += sizeof (UINT16);\r
+    Size -= sizeof (UINT16);\r
+    Buffer = (UINT16*)Buffer + 1;\r
+  }\r
+\r
+  while (Size >= sizeof (UINT32)) {\r
+    //\r
+    // Write as many double words as possible\r
+    //\r
+    PciWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r
+    StartAddress += sizeof (UINT32);\r
+    Size -= sizeof (UINT32);\r
+    Buffer = (UINT32*)Buffer + 1;\r
+  }\r
+\r
+  if (Size >= sizeof (UINT16)) {\r
+    //\r
+    // Write the last remaining word if exist\r
+    //\r
+    PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
+    StartAddress += sizeof (UINT16);\r
+    Size -= sizeof (UINT16);\r
+    Buffer = (UINT16*)Buffer + 1;\r
+  }\r
+\r
+  if (Size >= sizeof (UINT8)) {\r
+    //\r
+    // Write the last remaining byte if exist\r
+    //\r
+    PciWrite8 (StartAddress, *(UINT8*)Buffer);\r
+  }\r
+\r
+  return ReturnValue;\r
+}\r

diff --git a/MdePkg/Library/SmmPciLibPciRootBridgeIo/SmmPciLibPciRootBridgeIo.inf b/MdePkg/Library/SmmPciLibPciRootBridgeIo/SmmPciLibPciRootBridgeIo.inf
new file mode 100644 (file)
index 0000000..97f9a20
--- /dev/null
+++ b/MdePkg/Library/SmmPciLibPciRootBridgeIo/SmmPciLibPciRootBridgeIo.inf
@@ -0,0 +1,54 @@
+# @file\r
+# PCI Library that layers on top of the SMM PCI Root Bridge I/O Protocol.\r
+#\r
+# This library produces the APIs from the PCI Library and implements these APIs\r
+#  by calling into the PCI Root Bridge I/O Protocol. The PCI Root Bridge I/O Protocol is\r
+#  typically produced by a chipset specific DXE driver.\r
+#  This library binds to the first PCI Root Bridge I/O Protocol in the platform. As a result,\r
+#  it should only be used on platforms that contain a single PCI root bridge.\r
+#\r
+# Copyright (c) 2009, Intel Corporation.\r
+#\r
+#  All rights reserved. This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution. The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = SmmPciLibPciRootBridgeIo\r
+  FILE_GUID                      = F6994CBA-2351-4ebc-A2DA-20BAC2FE2CF3\r
+  MODULE_TYPE                    = DXE_SMM_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = PciLib|DXE_SMM_DRIVER SMM_CORE\r
+  PI_SPECIFICATION_VERSION       = 0x0001000A\r
+\r
+  CONSTRUCTOR                    = PciLibConstructor\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64\r
+#\r
+\r
+[Sources.common]\r
+  PciLib.c\r
+\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+\r
+\r
+[LibraryClasses]\r
+  BaseLib\r
+  SmmServicesTableLib\r
+  DebugLib\r
+\r
+[Protocols]\r
+  gEfiSmmPciRootBridgeIoProtocolGuid               ## CONSUMES\r
+\r

diff --git a/MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.c b/MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.c
new file mode 100644 (file)
index 0000000..f44dd6e
--- /dev/null
+++ b/MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.c
@@ -0,0 +1,104 @@
+/** @file\r
+  SMM Services Table Library.\r
+\r
+  Copyright (c) 2009, Intel Corporation<BR>\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+#include <PiSmm.h>\r
+#include <Protocol/SmmBase2.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/SmmServicesTableLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+EFI_SMM_SYSTEM_TABLE2        *gSmst              = NULL;\r
+EFI_SMM_BASE2_PROTOCOL       *mInternalSmmBase2  = NULL;\r
+\r
+\r
+/**\r
+  The constructor function caches the pointer of Smm Services Table.\r
+\r
+  @param  ImageHandle   The firmware allocated handle for the EFI image.\r
+  @param  SystemTable   A pointer to the EFI System Table.\r
+\r
+  @retval EFI_SUCCESS   The constructor always returns EFI_SUCCESS.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SmmServicesTableLibConstructor (\r
+  IN EFI_HANDLE        ImageHandle,\r
+  IN EFI_SYSTEM_TABLE  *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS                   Status;\r
+  BOOLEAN                      InSmm;\r
+\r
+  //\r
+  // Retrieve SMM Base2 Protocol\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiSmmBase2ProtocolGuid,\r
+                  NULL,\r
+                  (VOID **) &mInternalSmmBase2\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (mInternalSmmBase2 != NULL);\r
+\r
+  //\r
+  // Check to see if we are already in SMM\r
+  //\r
+  mInternalSmmBase2->InSmm (mInternalSmmBase2, &InSmm);\r
+\r
+  if (!InSmm) {\r
+    //\r
+    // We are not in SMM, so SMST is not needed\r
+    //\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  //\r
+  // We are in SMM, retrieve the pointer to SMM System Table\r
+  //\r
+  mInternalSmmBase2->GetSmstLocation (mInternalSmmBase2, &gSmst);\r
+\r
+  ASSERT (gSmst != NULL);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  This function allows the caller to determine if the driver is executing in \r
+  System Management Mode(SMM).\r
+\r
+  This function returns TRUE if the driver is executing in SMM and FALSE if the \r
+  driver is not executing in SMM.\r
+\r
+  @retval  TRUE  The driver is executing in System Management Mode (SMM).\r
+  @retval  FALSE The driver is not executing in System Management Mode (SMM). \r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+InSmm (\r
+  VOID\r
+  )\r
+{\r
+  BOOLEAN                      InSmm;\r
+\r
+  //\r
+  // Check to see if we are already in SMM\r
+  //\r
+  mInternalSmmBase2->InSmm (mInternalSmmBase2, &InSmm);\r
+\r
+  return InSmm;\r
+}\r

diff --git a/MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf b/MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf
new file mode 100644 (file)
index 0000000..e0e699b
--- /dev/null
+++ b/MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf
@@ -0,0 +1,47 @@
+#/** @file\r
+# SMM Services Table Library.\r
+#\r
+# Copyright (c) 2009, Intel Corporation.\r
+#\r
+#  All rights reserved. This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution. The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = SmmServicesTableLib\r
+  FILE_GUID                      = 064B4C5B-C5EF-4eff-85DF-65518EF1314D\r
+  MODULE_TYPE                    = DXE_SMM_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = SmmServicesTableLib|SMM_CORE DXE_SMM_DRIVER\r
+  EDK_RELEASE_VERSION            = 0x00020000\r
+  EFI_SPECIFICATION_VERSION      = 0x00020000\r
+  PI_SPECIFICATION_VERSION       = 0x0001000A\r
+\r
+  CONSTRUCTOR                    = SmmServicesTableLibConstructor\r
+\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64\r
+#\r
+\r
+[Sources.common]\r
+  SmmServicesTableLib.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+  UefiBootServicesTableLib\r
+  DebugLib\r
+\r
+[Protocols]\r
+  gEfiSmmBase2ProtocolGuid                      # PROTOCOL ALWAYS_CONSUMED\r
+\r
+[Depex.common.DXE_DRIVER]\r
+  gEfiSmmBase2ProtocolGuid\r

diff --git a/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf b/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
index 297739c177f33366a5e24aa8169d4becfbab37ff..74e80b7e39278e63caf32a3ab4d2b189d6128e47 100644 (file)
--- a/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+++ b/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
@@ -1,7 +1,7 @@
 #/** @file\r
 # UEFI Boot Services Table Library implementation.\r
 # \r
 #/** @file\r
 # UEFI Boot Services Table Library implementation.\r
 # \r

-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2009, Intel Corporation.\r

 #\r
 #  All rights reserved. This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
 #\r
 #  All rights reserved. This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r


@@ -19,7 +19,7 @@
   FILE_GUID                      = ff5c7a2c-ab7a-4366-8616-11c6e53247b6\r
   MODULE_TYPE                    = UEFI_DRIVER\r
   VERSION_STRING                 = 1.0\r
   FILE_GUID                      = ff5c7a2c-ab7a-4366-8616-11c6e53247b6\r
   MODULE_TYPE                    = UEFI_DRIVER\r
   VERSION_STRING                 = 1.0\r

-  LIBRARY_CLASS                  = UefiBootServicesTableLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER \r
+  LIBRARY_CLASS                  = UefiBootServicesTableLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r

 \r
   CONSTRUCTOR                    = UefiBootServicesTableLibConstructor\r
 \r
 \r
   CONSTRUCTOR                    = UefiBootServicesTableLibConstructor\r
 \r

diff --git a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
index 1ca67c6814cf10708d0b730123df1bd96a21dff2..7ba1a9e7514098467f6fd38f4655eaffccd15214 100644 (file)
--- a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+++ b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
@@ -3,7 +3,7 @@
 #\r
 # Device Path Library that layers on top of the Memory Allocation Library.\r
 #\r
 #\r
 # Device Path Library that layers on top of the Memory Allocation Library.\r
 #\r

-# Copyright (c) 2007 - 2008, Intel Corporation\r
+# Copyright (c) 2007 - 2009, Intel Corporation\r

 #\r
 #  All rights reserved. This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
 #\r
 #  All rights reserved. This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r


@@ -21,7 +21,7 @@
   FILE_GUID                      = 91c1677a-e57f-4191-8b8e-eb7711a716e0\r
   MODULE_TYPE                    = UEFI_DRIVER\r
   VERSION_STRING                 = 1.0\r
   FILE_GUID                      = 91c1677a-e57f-4191-8b8e-eb7711a716e0\r
   MODULE_TYPE                    = UEFI_DRIVER\r
   VERSION_STRING                 = 1.0\r

-  LIBRARY_CLASS                  = DevicePathLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER \r
+  LIBRARY_CLASS                  = DevicePathLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r

 \r
 \r
 #\r
 \r
 \r
 #\r

diff --git a/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf b/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
index 72ff4e11885206039d019472eff4366449afdd0f..8e55bf6b5f00739c3459de6a6b94fe819c9bcb79 100644 (file)
--- a/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+++ b/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
@@ -1,7 +1,7 @@
 #/** @file\r
 # Module entry point library for UEFI driver.\r
 #\r
 #/** @file\r
 # Module entry point library for UEFI driver.\r
 #\r

-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2009, Intel Corporation.\r

 #\r
 #  All rights reserved. This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
 #\r
 #  All rights reserved. This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r


@@ -19,7 +19,7 @@
   FILE_GUID                      = 331deb15-454b-48d8-9b74-70d01f3f3556\r
   MODULE_TYPE                    = UEFI_DRIVER\r
   VERSION_STRING                 = 1.0\r
   FILE_GUID                      = 331deb15-454b-48d8-9b74-70d01f3f3556\r
   MODULE_TYPE                    = UEFI_DRIVER\r
   VERSION_STRING                 = 1.0\r

-  LIBRARY_CLASS                  = UefiDriverEntryPoint|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER UEFI_DRIVER \r
+  LIBRARY_CLASS                  = UefiDriverEntryPoint|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER UEFI_DRIVER SMM_CORE DXE_SMM_DRIVER\r

   EFI_SPECIFICATION_VERSION      = 0x00020000\r
 \r
 \r
   EFI_SPECIFICATION_VERSION      = 0x00020000\r
 \r
 \r

diff --git a/MdePkg/Library/UefiLib/UefiLib.inf b/MdePkg/Library/UefiLib/UefiLib.inf
index 11a2a63f3497352a1a2e28e61b1312909cc64c82..15b56d68cd947db6e47f4ba556a61fd1620df130 100644 (file)
--- a/MdePkg/Library/UefiLib/UefiLib.inf
+++ b/MdePkg/Library/UefiLib/UefiLib.inf
@@ -7,7 +7,7 @@
 #  EFI Driver Model related protocols, manage Unicode string tables for UEFI Drivers, \r
 #  and print messages on the console output and standard error devices.\r
 #\r
 #  EFI Driver Model related protocols, manage Unicode string tables for UEFI Drivers, \r
 #  and print messages on the console output and standard error devices.\r
 #\r

-# Copyright (c) 2007 - 2008, Intel Corporation\r
+# Copyright (c) 2007 - 2009, Intel Corporation\r

 #\r
 #  All rights reserved. This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
 #\r
 #  All rights reserved. This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r


@@ -25,7 +25,7 @@
   FILE_GUID                      = 3a004ba5-efe0-4a61-9f1a-267a46ae5ba9\r
   MODULE_TYPE                    = UEFI_DRIVER\r
   VERSION_STRING                 = 1.0\r
   FILE_GUID                      = 3a004ba5-efe0-4a61-9f1a-267a46ae5ba9\r
   MODULE_TYPE                    = UEFI_DRIVER\r
   VERSION_STRING                 = 1.0\r

-  LIBRARY_CLASS                  = UefiLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
+  LIBRARY_CLASS                  = UefiLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r

 \r
 \r
 #\r
 \r
 \r
 #\r

diff --git a/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf b/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
index 8a0e0744c963413602f4d14c6c1b20e7e8e80cc5..f28819d8b74e7791e7559a643f5d425f932b9384 100644 (file)
--- a/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+++ b/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
@@ -4,7 +4,7 @@
 # Memory Allocation Library that uses EFI Boot Services to allocate\r
 #  and free memory.\r
 #\r
 # Memory Allocation Library that uses EFI Boot Services to allocate\r
 #  and free memory.\r
 #\r

-# Copyright (c) 2007 - 2008, Intel Corporation\r
+# Copyright (c) 2007 - 2009, Intel Corporation\r

 #\r
 #  All rights reserved. This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
 #\r
 #  All rights reserved. This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r


@@ -22,7 +22,7 @@
   FILE_GUID                      = 4674739d-3195-4fb2-8094-ac1d22d00194\r
   MODULE_TYPE                    = UEFI_DRIVER\r
   VERSION_STRING                 = 1.0\r
   FILE_GUID                      = 4674739d-3195-4fb2-8094-ac1d22d00194\r
   MODULE_TYPE                    = UEFI_DRIVER\r
   VERSION_STRING                 = 1.0\r

-  LIBRARY_CLASS                  = MemoryAllocationLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER \r
+  LIBRARY_CLASS                  = MemoryAllocationLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r

 \r
 \r
 #\r
 \r
 \r
 #\r

diff --git a/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf b/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
index 82126db448272ffe55ea25d4c89c79484a13109b..212ae638757fb54e339d8706ad288e8d317de110 100644 (file)
--- a/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+++ b/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
@@ -1,7 +1,7 @@
 #/** @file\r
 # UEFI Runtime Services Table Library implementation.\r
 #\r
 #/** @file\r
 # UEFI Runtime Services Table Library implementation.\r
 #\r

-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2009, Intel Corporation.\r

 #\r
 #  All rights reserved. This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
 #\r
 #  All rights reserved. This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r


@@ -19,7 +19,7 @@
   FILE_GUID                      = 19cbbb97-ff61-45ff-8c3f-dfa66dd118c8\r
   MODULE_TYPE                    = UEFI_DRIVER\r
   VERSION_STRING                 = 1.0\r
   FILE_GUID                      = 19cbbb97-ff61-45ff-8c3f-dfa66dd118c8\r
   MODULE_TYPE                    = UEFI_DRIVER\r
   VERSION_STRING                 = 1.0\r

-  LIBRARY_CLASS                  = UefiRuntimeServicesTableLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER \r
+  LIBRARY_CLASS                  = UefiRuntimeServicesTableLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r

 \r
   CONSTRUCTOR                    = UefiRuntimeServicesTableLibConstructor\r
 \r
 \r
   CONSTRUCTOR                    = UefiRuntimeServicesTableLibConstructor\r
 \r

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index baf7d556af606575daf4dae807e4a79040496189..6c417d52148dcf8ccef5a0860474d14bf4e6bfb5 100644 (file)
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -74,6 +74,10 @@
   #                  Only available to DXE and UEFI module types.\r
   UefiBootServicesTableLib|Include/Library/UefiBootServicesTableLib.h\r
 \r
   #                  Only available to DXE and UEFI module types.\r
   UefiBootServicesTableLib|Include/Library/UefiBootServicesTableLib.h\r
 \r

+  ##  @libraryclass  Provides a service to retrieve a pointer to the SMM Services Table.\r
+  #                  Only available to SMM/DXE Combined and SMM module types.\r
+  SmmServicesTableLib|Include/Library/SmmServicesTableLib.h\r
+\r

   ##  @libraryclass  Module entry point library for UEFI Applications.\r
   UefiApplicationEntryPoint|Include/Library/UefiApplicationEntryPoint.h\r
 \r
   ##  @libraryclass  Module entry point library for UEFI Applications.\r
   UefiApplicationEntryPoint|Include/Library/UefiApplicationEntryPoint.h\r
 \r


@@ -429,6 +433,8 @@
   #\r
   # GUID defined in PI1.2\r
   #\r
   #\r
   # GUID defined in PI1.2\r
   #\r

+  ## Include/Guid/EventGroup.h\r
+  gEfiEventDxeDispatchGuid       = { 0x7081E22F, 0xCAC6, 0x4053, { 0x94, 0x68, 0x67, 0x57, 0x82, 0xCF, 0x88, 0xE5 }}\r

 \r
   ## Guid for EFI_DISK_INFO_PROTOCOL.Interface to specify Ide interface.\r
   ## Include/Protocol/DiskInfo.h\r
 \r
   ## Guid for EFI_DISK_INFO_PROTOCOL.Interface to specify Ide interface.\r
   ## Include/Protocol/DiskInfo.h\r

diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index f0a7958426f1ffe3b7831fdbf38771cd2213e634..87f2ae2120dcd45b7256205d71e1dcdf00f7066c 100644 (file)
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -148,7 +148,9 @@
   MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf\r
   MdePkg/Library/SecPeiDxeTimerLibCpu/SecPeiDxeTimerLibCpu.inf\r
   MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf\r
   MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf\r
   MdePkg/Library/SecPeiDxeTimerLibCpu/SecPeiDxeTimerLibCpu.inf\r
   MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf\r

-\r
+  MdePkg/Library/SmmIoLibCpuIo/SmmIoLibCpuIo.inf\r
+  MdePkg/Library/SmmPciLibPciRootBridgeIo/SmmPciLibPciRootBridgeIo.inf\r
+  MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf\r

 \r
 [Components.IPF]\r
   MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
 \r
 [Components.IPF]\r
   MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r