ArmPkg/ArmLib: Fixed field shifting in CLIDR_EL1 (AArch64)

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14677 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index ad9fdda5253d9cd49012436033a3b8dfd908490d..27c1d465fd725032c38a37246f6321611ad572f9 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -320,7 +320,7 @@ ASM_PFX(AArch64AllDataCachesOperation):
   mov   x1, x0                  // Save Function call in x1\r
   mrs   x6, clidr_el1           // Read EL1 CLIDR\r
   and   x3, x6, #0x7000000      // Mask out all but Level of Coherency (LoC)\r
-  lsr   x3, x3, #23             // Left align cache level value\r
+  lsr   x3, x3, #24             // Left align cache level value\r
   cbz   x3, L_Finished          // No need to clean if LoC is 0\r
   mov   x10, #0                 // Start clean at cache level 0\r
   b     Loop1\r
@@ -332,7 +332,7 @@ ASM_PFX(AArch64PerformPoUDataCacheOperation):
   mov   x1, x0                  // Save Function call in x1\r
   mrs   x6, clidr_el1           // Read EL1 CLIDR\r
   and   x3, x6, #0x38000000     // Mask out all but Point of Unification (PoU)\r
-  lsr   x3, x3, #26             // Left align cache level value\r
+  lsr   x3, x3, #27             // Left align cache level value\r
   cbz   x3, L_Finished          // No need to clean if LoC is 0\r
   mov   x10, #0                 // Start clean at cache level 0\r
 \r