ArmPkg: update InvalidateInstructionCacheRange to flush only to PoU

This patch updates the ArmPkg variant of InvalidateInstructionCacheRange to
flush the data cache only to the point of unification (PoU). This improves
performance and also allows invalidation in scenarios where it would be
inappropriate to flush to the point of coherency (like when executing code
from L2 configured as cache-as-ram).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Added AARCH64 and ARM/GCC implementations of the above.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19174 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 9622444ec63f61b4d2aaf0653ad7540b96695d56..85fa1f600ba9e40fa09b74b75085ef7a5e7655ce 100644 (file)
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -183,10 +183,16 @@ ArmInvalidateDataCacheEntryByMVA (
 \r
 VOID\r
 EFIAPI\r
-ArmCleanDataCacheEntryByMVA (\r
+ArmCleanDataCacheEntryToPoUByMVA(\r
   IN  UINTN   Address\r
   );\r
 \r
+VOID\r
+EFIAPI\r
+ArmCleanDataCacheEntryByMVA(\r
+IN  UINTN   Address\r
+);\r
+\r
 VOID\r
 EFIAPI\r
 ArmCleanInvalidateDataCacheEntryByMVA (\r

diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
index feab4497ac1ba994766faa354d2e121e495f8ec3..1045f9068f4dc0d71d71785d46f6dac4d053004c 100644 (file)
--- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
+++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
@@ -64,7 +64,7 @@ InvalidateInstructionCacheRange (
   IN      UINTN                     Length\r
   )\r
 {\r
-  CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryByMVA);\r
+  CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA);\r
   ArmInvalidateInstructionCache ();\r
   return Address;\r
 }\r

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index c530d19e897e3548fe28d3461d610c82f6cd268e..db21f73f0ed7ee3b8740cf1abd69325235228aff 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -22,6 +22,7 @@
 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)\r
 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)\r
 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)\r
+GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)\r
 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)\r
 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)\r
 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)\r
@@ -72,6 +73,11 @@ ASM_PFX(ArmCleanDataCacheEntryByMVA):
   ret\r
 \r
 \r
+ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):\r
+  dc      cvau, x0    // Clean single data cache line to PoU\r
+  ret\r
+\r
+\r
 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
   dc      civac, x0   // Clean and invalidate single data cache line\r
   ret\r

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
index 5f030d92de3111f274f36aab9aec0b36991dbd21..7de1b11ef818b604b4d02b718d5efa696e25f751 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
@@ -19,6 +19,7 @@
 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)\r
 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)\r
 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)\r
+GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)\r
 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)\r
 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)\r
 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)\r
@@ -69,6 +70,11 @@ ASM_PFX(ArmCleanDataCacheEntryByMVA):
   bx      lr\r
 \r
 \r
+ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):\r
+  mcr     p15, 0, r0, c7, c11, 1  @clean single data cache line to PoU\r
+  bx      lr\r
+\r
+\r
 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line\r
   bx      lr\r

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
index df7e22dca2d911e6d88fd056ccdd44e5a1c0f752..a460bd2da7a99dedf4377f6761d8e59597051dfe 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
@@ -34,6 +34,11 @@ CTRL_I_BIT      EQU     (1 << 12)
   bx      lr\r
 \r
 \r
+ RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA\r
+  mcr     p15, 0, r0, c7, c11, 1  ; clean single data cache line to PoU\r
+  bx      lr\r
+\r
+\r
  RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
   mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line\r
   bx      lr\r