MdeModulePkg/PciHostBridge: Add RESOURCE_VALID() to simplify code

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.com>

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index 87385aa1726c8ef01d90bc782ec1d2711af0531a..16413b60a65ec48f6271771f1e15f3e39abda32a 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -21,6 +21,8 @@ extern EDKII_IOMMU_PROTOCOL        *mIoMmuProtocol;
 \r
 #define NO_MAPPING  (VOID *) (UINTN) -1\r
 \r
+#define RESOURCE_VALID(Resource) ((Resource)->Base <= (Resource)->Limit)\r
+\r
 //\r
 // Lookup table for increment values based on transfer widths\r
 //\r
@@ -122,25 +124,25 @@ CreateRootBridge (
   //\r
   // Make sure Mem and MemAbove4G apertures are valid\r
   //\r
-  if (Bridge->Mem.Base <= Bridge->Mem.Limit) {\r
+  if (RESOURCE_VALID (&Bridge->Mem)) {\r
     ASSERT (Bridge->Mem.Limit < SIZE_4GB);\r
     if (Bridge->Mem.Limit >= SIZE_4GB) {\r
       return NULL;\r
     }\r
   }\r
-  if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) {\r
+  if (RESOURCE_VALID (&Bridge->MemAbove4G)) {\r
     ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);\r
     if (Bridge->MemAbove4G.Base < SIZE_4GB) {\r
       return NULL;\r
     }\r
   }\r
-  if (Bridge->PMem.Base <= Bridge->PMem.Limit) {\r
+  if (RESOURCE_VALID (&Bridge->PMem)) {\r
     ASSERT (Bridge->PMem.Limit < SIZE_4GB);\r
     if (Bridge->PMem.Limit >= SIZE_4GB) {\r
       return NULL;\r
     }\r
   }\r
-  if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) {\r
+  if (RESOURCE_VALID (&Bridge->PMemAbove4G)) {\r
     ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);\r
     if (Bridge->PMemAbove4G.Base < SIZE_4GB) {\r
       return NULL;\r
@@ -157,11 +159,9 @@ CreateRootBridge (
       // support separate windows for Non-prefetchable and Prefetchable\r
       // memory.\r
       //\r
-      ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);\r
-      ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);\r
-      if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||\r
-          (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)\r
-          ) {\r
+      ASSERT (!RESOURCE_VALID (&Bridge->PMem));\r
+      ASSERT (!RESOURCE_VALID (&Bridge->PMemAbove4G));\r
+      if (RESOURCE_VALID (&Bridge->PMem) || RESOURCE_VALID (&Bridge->PMemAbove4G)) {\r
         return NULL;\r
       }\r
     }\r
@@ -171,11 +171,9 @@ CreateRootBridge (
       // If this bit is not set, then the PCI Root Bridge does not support\r
       // 64 bit memory windows.\r
       //\r
-      ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);\r
-      ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);\r
-      if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||\r
-          (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)\r
-          ) {\r
+      ASSERT (!RESOURCE_VALID (&Bridge->MemAbove4G));\r
+      ASSERT (!RESOURCE_VALID (&Bridge->PMemAbove4G));\r
+      if (RESOURCE_VALID (&Bridge->MemAbove4G) || RESOURCE_VALID (&Bridge->PMemAbove4G)) {\r
         return NULL;\r
       }\r
     }\r