## If set, framebuffer memory will be reserved and mapped in the system RAM\r
gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase|0x0|UINT64|0x00000044\r
\r
+ ## ARM Mali Display Processor DP500/DP550/DP650\r
+ gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase|0x0|UINT64|0x00000050\r
+ gArmPlatformTokenSpaceGuid.PcdArmMaliDpMemoryRegionLength|0x0|UINT32|0x00000051\r
+\r
## PL180 MCI\r
gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028\r
gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029\r
# ARM platform package.\r
#\r
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>\r
+# Copyright (c) 2011 - 2018, ARM Ltd. All rights reserved.<BR>\r
# Copyright (c) 2016 - 2017, Linaro Ltd. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
\r
ArmPlatformPkg/PrePi/PeiMPCore.inf\r
ArmPlatformPkg/PrePi/PeiUniCore.inf\r
+\r
+ ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.inf\r
--- /dev/null
+/** @file\r
+\r
+ ARM Mali DP 500/550/650 display controller driver\r
+\r
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/LcdHwLib.h>\r
+#include <Library/LcdPlatformLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+\r
+#include "ArmMaliDp.h"\r
+\r
+// CORE_ID of the MALI DP\r
+STATIC UINT32 mDpDeviceId;\r
+\r
+/** Disable the graphics layer\r
+\r
+ This is done by clearing the EN bit of the LG_CONTROL register.\r
+**/\r
+STATIC\r
+VOID\r
+LayerGraphicsDisable (VOID)\r
+{\r
+ MmioAnd32 (DP_BASE + DP_DE_LG_CONTROL, ~DP_DE_LG_ENABLE);\r
+}\r
+\r
+/** Enable the graphics layer\r
+\r
+ This is done by setting the EN bit of the LG_CONTROL register.\r
+**/\r
+STATIC\r
+VOID\r
+LayerGraphicsEnable (VOID)\r
+{\r
+ MmioOr32 (DP_BASE + DP_DE_LG_CONTROL, DP_DE_LG_ENABLE);\r
+}\r
+\r
+/** Set the frame address of the graphics layer.\r
+\r
+ @param[in] FrameBaseAddress Address of the data buffer to be used as\r
+ a framebuffer.\r
+**/\r
+STATIC\r
+VOID\r
+LayerGraphicsSetFrame (\r
+ IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress\r
+ )\r
+{\r
+ // Disable the graphics layer.\r
+ LayerGraphicsDisable ();\r
+\r
+ // Set up memory address of the data buffer for graphics layer.\r
+ // write lower bits of the address.\r
+ MmioWrite32 (\r
+ DP_BASE + DP_DE_LG_PTR_LOW,\r
+ DP_DE_LG_PTR_LOW_MASK & FrameBaseAddress\r
+ );\r
+\r
+ // Write higher bits of the address.\r
+ MmioWrite32 (\r
+ DP_BASE + DP_DE_LG_PTR_HIGH,\r
+ (UINT32)(FrameBaseAddress >> DP_DE_LG_PTR_HIGH_SHIFT)\r
+ );\r
+\r
+ // Enable the graphics layer.\r
+ LayerGraphicsEnable ();\r
+}\r
+\r
+/** Configures various graphics layer characteristics.\r
+\r
+ @param[in] UefiGfxPixelFormat This must be either\r
+ PixelBlueGreenRedReserved8BitPerColor\r
+ OR\r
+ PixelRedGreenBlueReserved8BitPerColor\r
+ @param[in] HRes Horizontal resolution of the graphics layer.\r
+ @param[in] VRes Vertical resolution of the graphics layer.\r
+**/\r
+STATIC\r
+VOID\r
+LayerGraphicsConfig (\r
+ IN CONST EFI_GRAPHICS_PIXEL_FORMAT UefiGfxPixelFormat,\r
+ IN CONST UINT32 HRes,\r
+ IN CONST UINT32 VRes\r
+ )\r
+{\r
+ UINT32 PixelFormat;\r
+\r
+ // Disable the graphics layer before configuring any settings.\r
+ LayerGraphicsDisable ();\r
+\r
+ // Setup graphics layer size.\r
+ MmioWrite32 (DP_BASE + DP_DE_LG_IN_SIZE, FRAME_IN_SIZE (HRes, VRes));\r
+\r
+ // Setup graphics layer composition size.\r
+ MmioWrite32 (DP_BASE + DP_DE_LG_CMP_SIZE, FRAME_CMP_SIZE (HRes, VRes));\r
+\r
+ // Setup memory stride (total visible pixels on a line * 4).\r
+ MmioWrite32 (DP_BASE + DP_DE_LG_H_STRIDE, (HRes * sizeof (UINT32)));\r
+\r
+ // Set the format.\r
+\r
+ // In PixelBlueGreenRedReserved8BitPerColor format, byte 0 represents blue,\r
+ // byte 1 represents green, byte 2 represents red, and byte 3 is reserved\r
+ // which is equivalent to XRGB format of the DP500/DP550/DP650. Whereas\r
+ // PixelRedGreenBlueReserved8BitPerColor is equivalent to XBGR of the\r
+ // DP500/DP550/DP650.\r
+ if (UefiGfxPixelFormat == PixelBlueGreenRedReserved8BitPerColor) {\r
+ PixelFormat = (mDpDeviceId == MALIDP_500) ? DP_PIXEL_FORMAT_DP500_XRGB_8888\r
+ : DP_PIXEL_FORMAT_XRGB_8888;\r
+ } else {\r
+ PixelFormat = (mDpDeviceId == MALIDP_500) ? DP_PIXEL_FORMAT_DP500_XBGR_8888\r
+ : DP_PIXEL_FORMAT_XBGR_8888;\r
+ }\r
+\r
+ MmioWrite32 (DP_BASE + DP_DE_LG_FORMAT, PixelFormat);\r
+\r
+ // Enable graphics layer.\r
+ LayerGraphicsEnable ();\r
+}\r
+\r
+/** Configure timing information of the display.\r
+\r
+ @param[in] Horizontal Pointer to horizontal timing parameters.\r
+ (Resolution, Sync, Back porch, Front porch)\r
+ @param[in] Vertical Pointer to vertical timing parameters.\r
+ (Resolution, Sync, Back porch, Front porch)\r
+**/\r
+STATIC\r
+VOID\r
+SetDisplayEngineTiming (\r
+ IN CONST SCAN_TIMINGS * CONST Horizontal,\r
+ IN CONST SCAN_TIMINGS * CONST Vertical\r
+ )\r
+{\r
+ UINTN RegHIntervals;\r
+ UINTN RegVIntervals;\r
+ UINTN RegSyncControl;\r
+ UINTN RegHVActiveSize;\r
+\r
+ if (mDpDeviceId == MALIDP_500) {\r
+ // MALI DP500 timing registers.\r
+ RegHIntervals = DP_BASE + DP_DE_DP500_H_INTERVALS;\r
+ RegVIntervals = DP_BASE + DP_DE_DP500_V_INTERVALS;\r
+ RegSyncControl = DP_BASE + DP_DE_DP500_SYNC_CONTROL;\r
+ RegHVActiveSize = DP_BASE + DP_DE_DP500_HV_ACTIVESIZE;\r
+ } else {\r
+ // MALI DP550/DP650 timing registers.\r
+ RegHIntervals = DP_BASE + DP_DE_H_INTERVALS;\r
+ RegVIntervals = DP_BASE + DP_DE_V_INTERVALS;\r
+ RegSyncControl = DP_BASE + DP_DE_SYNC_CONTROL;\r
+ RegHVActiveSize = DP_BASE + DP_DE_HV_ACTIVESIZE;\r
+ }\r
+\r
+ // Horizontal back porch and front porch.\r
+ MmioWrite32 (\r
+ RegHIntervals,\r
+ H_INTERVALS (Horizontal->FrontPorch, Horizontal->BackPorch)\r
+ );\r
+\r
+ // Vertical back porch and front porch.\r
+ MmioWrite32 (\r
+ RegVIntervals,\r
+ V_INTERVALS (Vertical->FrontPorch, Vertical->BackPorch)\r
+ );\r
+\r
+ // Sync control, Horizontal and Vertical sync.\r
+ MmioWrite32 (\r
+ RegSyncControl,\r
+ SYNC_WIDTH (Horizontal->Sync, Vertical->Sync)\r
+ );\r
+\r
+ // Set up Horizontal and Vertical area size.\r
+ MmioWrite32 (\r
+ RegHVActiveSize,\r
+ HV_ACTIVE (Horizontal->Resolution, Vertical->Resolution)\r
+ );\r
+}\r
+\r
+/** Return CORE_ID of the ARM Mali DP.\r
+\r
+ @retval 0xFFF No Mali DP found.\r
+ @retval 0x500 Mali DP core id for DP500.\r
+ @retval 0x550 Mali DP core id for DP550.\r
+ @retval 0x650 Mali DP core id for DP650.\r
+**/\r
+STATIC\r
+UINT32\r
+ArmMaliDpGetCoreId (\r
+ )\r
+{\r
+ UINT32 DpCoreId;\r
+\r
+ // First check for DP500 as register offset for DP550/DP650 CORE_ID\r
+ // is beyond 3K/4K register space of the DP500.\r
+ DpCoreId = MmioRead32 (DP_BASE + DP_DE_DP500_CORE_ID);\r
+ DpCoreId >>= DP_DE_DP500_CORE_ID_SHIFT;\r
+\r
+ if (DpCoreId == MALIDP_500) {\r
+ return DpCoreId;\r
+ }\r
+\r
+ // Check for DP550 or DP650.\r
+ DpCoreId = MmioRead32 (DP_BASE + DP_DC_CORE_ID);\r
+ DpCoreId >>= DP_DC_CORE_ID_SHIFT;\r
+\r
+ if ((DpCoreId == MALIDP_550) || (DpCoreId == MALIDP_650)) {\r
+ return DpCoreId;\r
+ }\r
+\r
+ return MALIDP_NOT_PRESENT;\r
+}\r
+\r
+/** Check for presence of MALI.\r
+\r
+ This function returns success if the platform implements\r
+ DP500/DP550/DP650 ARM Mali display processor.\r
+\r
+ @retval EFI_SUCCESS DP500/DP550/DP650 display processor found\r
+ on the platform.\r
+ @retval EFI_NOT_FOUND DP500/DP550/DP650 display processor not found\r
+ on the platform.\r
+**/\r
+EFI_STATUS\r
+LcdIdentify (VOID)\r
+{\r
+ DEBUG ((DEBUG_WARN,\r
+ "Probing ARM Mali DP500/DP550/DP650 at base address 0x%p\n",\r
+ DP_BASE\r
+ ));\r
+\r
+ if (mDpDeviceId == 0) {\r
+ mDpDeviceId = ArmMaliDpGetCoreId ();\r
+ }\r
+\r
+ if (mDpDeviceId == MALIDP_NOT_PRESENT) {\r
+ DEBUG ((DEBUG_WARN, "ARM Mali DP not found...\n"));\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ DEBUG ((DEBUG_WARN, "Found ARM Mali DP %x\n", mDpDeviceId));\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/** Initialize platform display.\r
+\r
+ @param[in] FrameBaseAddress Address of the frame buffer.\r
+\r
+ @retval EFI_SUCCESS Display initialization successful.\r
+ @retval !(EFI_SUCCESS) Display initialization failure.\r
+**/\r
+EFI_STATUS\r
+LcdInitialize (\r
+ IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress\r
+ )\r
+{\r
+ DEBUG ((DEBUG_WARN, "Framebuffer base address = %p\n", FrameBaseAddress));\r
+\r
+ if (mDpDeviceId == 0) {\r
+ mDpDeviceId = ArmMaliDpGetCoreId ();\r
+ }\r
+\r
+ if (mDpDeviceId == MALIDP_NOT_PRESENT) {\r
+ DEBUG ((DEBUG_ERROR, "ARM Mali DP initialization failed,"\r
+ "no ARM Mali DP present\n"));\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ // We are using graphics layer of the Mali DP as a main framebuffer.\r
+ LayerGraphicsSetFrame (FrameBaseAddress);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/** Set ARM Mali DP in cofiguration mode.\r
+\r
+ The ARM Mali DP must be in the configuration mode for\r
+ configuration of the H_INTERVALS, V_INTERVALS, SYNC_CONTROL\r
+ and HV_ACTIVESIZE.\r
+**/\r
+STATIC\r
+VOID\r
+SetConfigurationMode (VOID)\r
+{\r
+ // Request configuration Mode.\r
+ if (mDpDeviceId == MALIDP_500) {\r
+ MmioOr32 (DP_BASE + DP_DE_DP500_CONTROL, DP_DE_DP500_CONTROL_CONFIG_REQ);\r
+ } else {\r
+ MmioOr32 (DP_BASE + DP_DC_CONTROL, DP_DC_CONTROL_CM_ACTIVE);\r
+ }\r
+}\r
+\r
+/** Set ARM Mali DP in normal mode.\r
+\r
+ Normal mode is the main operating mode of the display processor\r
+ in which display layer data is fetched from framebuffer and\r
+ displayed.\r
+**/\r
+STATIC\r
+VOID\r
+SetNormalMode (VOID)\r
+{\r
+ // Disable configuration Mode.\r
+ if (mDpDeviceId == MALIDP_500) {\r
+ MmioAnd32 (DP_BASE + DP_DE_DP500_CONTROL, ~DP_DE_DP500_CONTROL_CONFIG_REQ);\r
+ } else {\r
+ MmioAnd32 (DP_BASE + DP_DC_CONTROL, ~DP_DC_CONTROL_CM_ACTIVE);\r
+ }\r
+}\r
+\r
+/** Set the global configuration valid flag.\r
+\r
+ Any new configuration parameters written to the display engine are not\r
+ activated until the global configuration valid flag is set in the\r
+ CONFIG_VALID register.\r
+**/\r
+STATIC\r
+VOID\r
+SetConfigValid (VOID)\r
+{\r
+ if (mDpDeviceId == MALIDP_500) {\r
+ MmioOr32 (DP_BASE + DP_DP500_CONFIG_VALID, DP_DC_CONFIG_VALID);\r
+ } else {\r
+ MmioOr32 (DP_BASE + DP_DC_CONFIG_VALID, DP_DC_CONFIG_VALID);\r
+ }\r
+}\r
+\r
+/** Set requested mode of the display.\r
+\r
+ @param[in] ModeNumber Display mode number.\r
+\r
+ @retval EFI_SUCCESS Display mode set successful.\r
+ @retval EFI_DEVICE_ERROR Display mode not found/supported.\r
+**/\r
+EFI_STATUS\r
+LcdSetMode (\r
+ IN CONST UINT32 ModeNumber\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ SCAN_TIMINGS *Horizontal;\r
+ SCAN_TIMINGS *Vertical;\r
+\r
+ EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo;\r
+\r
+ // Get the display mode timings and other relevant information.\r
+ Status = LcdPlatformGetTimings (\r
+ ModeNumber,\r
+ &Horizontal,\r
+ &Vertical\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ ASSERT_EFI_ERROR (Status);\r
+ return Status;\r
+ }\r
+\r
+ ASSERT (Horizontal != NULL);\r
+ ASSERT (Vertical != NULL);\r
+\r
+ // Get the pixel format information.\r
+ Status = LcdPlatformQueryMode (ModeNumber, &ModeInfo);\r
+ if (EFI_ERROR (Status)) {\r
+ ASSERT_EFI_ERROR (Status);\r
+ return Status;\r
+ }\r
+\r
+ // Request configuration mode.\r
+ SetConfigurationMode ();\r
+\r
+ // Configure the graphics layer.\r
+ LayerGraphicsConfig (\r
+ ModeInfo.PixelFormat,\r
+ Horizontal->Resolution,\r
+ Vertical->Resolution\r
+ );\r
+\r
+ // Set the display engine timings.\r
+ SetDisplayEngineTiming (Horizontal, Vertical);\r
+\r
+ // After configuration, set Mali DP in normal mode.\r
+ SetNormalMode ();\r
+\r
+ // Any parameters written to the display engine are not activated until\r
+ // CONFIG_VALID is set.\r
+ SetConfigValid ();\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/** This function de-initializes the display.\r
+\r
+**/\r
+VOID\r
+LcdShutdown (VOID)\r
+{\r
+ // Disable graphics layer.\r
+ LayerGraphicsDisable ();\r
+}\r
--- /dev/null
+/** @file\r
+\r
+ This header file contains the platform independent parts of ARM Mali DP\r
+\r
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+#ifndef ARMMALIDP_H_\r
+#define ARMMALIDP_H_\r
+\r
+#define DP_BASE (FixedPcdGet64 (PcdArmMaliDpBase))\r
+\r
+// MALI DP Ids\r
+#define MALIDP_NOT_PRESENT 0xFFF\r
+#define MALIDP_500 0x500\r
+#define MALIDP_550 0x550\r
+#define MALIDP_650 0x650\r
+\r
+// DP500 Peripheral Ids\r
+#define DP500_ID_PART_0 0x00\r
+#define DP500_ID_DES_0 0xB\r
+#define DP500_ID_PART_1 0x5\r
+\r
+#define DP500_ID_REVISION 0x1\r
+#define DP500_ID_JEDEC 0x1\r
+#define DP500_ID_DES_1 0x3\r
+\r
+#define DP500_PERIPHERAL_ID0_VAL (DP500_ID_PART_0)\r
+#define DP500_PERIPHERAL_ID1_VAL ((DP500_ID_DES_0 << 4) \\r
+ | DP500_ID_PART_1)\r
+#define DP500_PERIPHERAL_ID2_VAL ((DP500_ID_REVISION << 4) \\r
+ | (DP500_ID_JEDEC << 3) \\r
+ | (DP500_ID_DES_1))\r
+\r
+// DP550 Peripheral Ids\r
+#define DP550_ID_PART_0 0x50\r
+#define DP550_ID_DES_0 0xB\r
+#define DP550_ID_PART_1 0x5\r
+\r
+#define DP550_ID_REVISION 0x0\r
+#define DP550_ID_JEDEC 0x1\r
+#define DP550_ID_DES_1 0x3\r
+\r
+#define DP550_PERIPHERAL_ID0_VAL (DP550_ID_PART_0)\r
+#define DP550_PERIPHERAL_ID1_VAL ((DP550_ID_DES_0 << 4) \\r
+ | DP550_ID_PART_1)\r
+#define DP550_PERIPHERAL_ID2_VAL ((DP550_ID_REVISION << 4) \\r
+ | (DP550_ID_JEDEC << 3) \\r
+ | (DP550_ID_DES_1))\r
+\r
+// DP650 Peripheral Ids\r
+#define DP650_ID_PART_0 0x50\r
+#define DP650_ID_DES_0 0xB\r
+#define DP650_ID_PART_1 0x6\r
+\r
+#define DP650_ID_REVISION 0x0\r
+#define DP650_ID_JEDEC 0x1\r
+#define DP650_ID_DES_1 0x3\r
+\r
+#define DP650_PERIPHERAL_ID0_VAL (DP650_ID_PART_0)\r
+#define DP650_PERIPHERAL_ID1_VAL ((DP650_ID_DES_0 << 4) \\r
+ | DP650_ID_PART_1)\r
+#define DP650_PERIPHERAL_ID2_VAL ((DP650_ID_REVISION << 4) \\r
+ | (DP650_ID_JEDEC << 3) \\r
+ | (DP650_ID_DES_1))\r
+\r
+// Display Engine (DE) control register offsets for DP550/DP650\r
+#define DP_DE_STATUS 0x00000\r
+#define DP_DE_IRQ_SET 0x00004\r
+#define DP_DE_IRQ_MASK 0x00008\r
+#define DP_DE_IRQ_CLEAR 0x0000C\r
+#define DP_DE_CONTROL 0x00010\r
+#define DP_DE_PROG_LINE 0x00014\r
+#define DP_DE_AXI_CONTROL 0x00018\r
+#define DP_DE_AXI_QOS 0x0001C\r
+#define DP_DE_DISPLAY_FUNCTION 0x00020\r
+\r
+#define DP_DE_H_INTERVALS 0x00030\r
+#define DP_DE_V_INTERVALS 0x00034\r
+#define DP_DE_SYNC_CONTROL 0x00038\r
+#define DP_DE_HV_ACTIVESIZE 0x0003C\r
+#define DP_DE_DISPLAY_SIDEBAND 0x00040\r
+#define DP_DE_BACKGROUND_COLOR 0x00044\r
+#define DP_DE_DISPLAY_SPLIT 0x00048\r
+#define DP_DE_OUTPUT_DEPTH 0x0004C\r
+\r
+// Display Engine (DE) control register offsets for DP500\r
+#define DP_DE_DP500_CORE_ID 0x00018\r
+#define DP_DE_DP500_CONTROL 0x0000C\r
+#define DP_DE_DP500_PROG_LINE 0x00010\r
+#define DP_DE_DP500_H_INTERVALS 0x00028\r
+#define DP_DE_DP500_V_INTERVALS 0x0002C\r
+#define DP_DE_DP500_SYNC_CONTROL 0x00030\r
+#define DP_DE_DP500_HV_ACTIVESIZE 0x00034\r
+#define DP_DE_DP500_BG_COLOR_RG 0x0003C\r
+#define DP_DE_DP500_BG_COLOR_B 0x00040\r
+\r
+/* Display Engine (DE) graphics layer (LG) register offsets\r
+ * NOTE: For DP500 it will be LG2.\r
+ */\r
+#define DE_LG_OFFSET 0x00300\r
+#define DP_DE_LG_FORMAT (DE_LG_OFFSET)\r
+#define DP_DE_LG_CONTROL (DE_LG_OFFSET + 0x04)\r
+#define DP_DE_LG_COMPOSE (DE_LG_OFFSET + 0x08)\r
+#define DP_DE_LG_IN_SIZE (DE_LG_OFFSET + 0x0C)\r
+#define DP_DE_LG_CMP_SIZE (DE_LG_OFFSET + 0x10)\r
+#define DP_DE_LG_OFFSET (DE_LG_OFFSET + 0x14)\r
+#define DP_DE_LG_H_STRIDE (DE_LG_OFFSET + 0x18)\r
+#define DP_DE_LG_PTR_LOW (DE_LG_OFFSET + 0x1C)\r
+#define DP_DE_LG_PTR_HIGH (DE_LG_OFFSET + 0x20)\r
+#define DP_DE_LG_CHROMA_KEY (DE_LG_OFFSET + 0x2C)\r
+#define DP_DE_LG_AD_CONTROL (DE_LG_OFFSET + 0x30)\r
+#define DP_DE_LG_MMU_CONTROL (DE_LG_OFFSET + 0x48)\r
+\r
+// Display core (DC) control register offsets.\r
+#define DP_DC_OFFSET 0x0C000\r
+#define DP_DC_STATUS (DP_DC_OFFSET + 0x00)\r
+#define DP_DC_IRQ_SET (DP_DC_OFFSET + 0x04)\r
+#define DP_DC_IRQ_MASK (DP_DC_OFFSET + 0x08)\r
+#define DP_DC_IRQ_CLEAR (DP_DC_OFFSET + 0x0C)\r
+#define DP_DC_CONTROL (DP_DC_OFFSET + 0x10)\r
+#define DP_DC_CONFIG_VALID (DP_DC_OFFSET + 0x14)\r
+#define DP_DC_CORE_ID (DP_DC_OFFSET + 0x18)\r
+\r
+// DP500 has a global configuration register.\r
+#define DP_DP500_CONFIG_VALID (0xF00)\r
+\r
+// Display core ID register offsets.\r
+#define DP_DC_ID_OFFSET 0x0FF00\r
+#define DP_DC_ID_PERIPHERAL_ID4 (DP_DC_ID_OFFSET + 0xD0)\r
+#define DP_DC_CONFIGURATION_ID (DP_DC_ID_OFFSET + 0xD4)\r
+#define DP_DC_PERIPHERAL_ID0 (DP_DC_ID_OFFSET + 0xE0)\r
+#define DP_DC_PERIPHERAL_ID1 (DP_DC_ID_OFFSET + 0xE4)\r
+#define DP_DC_PERIPHERAL_ID2 (DP_DC_ID_OFFSET + 0xE8)\r
+#define DP_DC_COMPONENT_ID0 (DP_DC_ID_OFFSET + 0xF0)\r
+#define DP_DC_COMPONENT_ID1 (DP_DC_ID_OFFSET + 0xF4)\r
+#define DP_DC_COMPONENT_ID2 (DP_DC_ID_OFFSET + 0xF8)\r
+#define DP_DC_COMPONENT_ID3 (DP_DC_ID_OFFSET + 0xFC)\r
+\r
+#define DP_DP500_ID_OFFSET 0x0F00\r
+#define DP_DP500_ID_PERIPHERAL_ID4 (DP_DP500_ID_OFFSET + 0xD0)\r
+#define DP_DP500_CONFIGURATION_ID (DP_DP500_ID_OFFSET + 0xD4)\r
+#define DP_DP500_PERIPHERAL_ID0 (DP_DP500_ID_OFFSET + 0xE0)\r
+#define DP_DP500_PERIPHERAL_ID1 (DP_DP500_ID_OFFSET + 0xE4)\r
+#define DP_DP500_PERIPHERAL_ID2 (DP_DP500_ID_OFFSET + 0xE8)\r
+#define DP_DP500_COMPONENT_ID0 (DP_DP500_ID_OFFSET + 0xF0)\r
+#define DP_DP500_COMPONENT_ID1 (DP_DP500_ID_OFFSET + 0xF4)\r
+#define DP_DP500_COMPONENT_ID2 (DP_DP500_ID_OFFSET + 0xF8)\r
+#define DP_DP500_COMPONENT_ID3 (DP_DP500_ID_OFFSET + 0xFC)\r
+\r
+// Display status configuration mode activation flag\r
+#define DP_DC_STATUS_CM_ACTIVE_FLAG (0x1U << 16)\r
+\r
+// Display core control configuration mode\r
+#define DP_DC_CONTROL_SRST_ACTIVE (0x1U << 18)\r
+#define DP_DC_CONTROL_CRST_ACTIVE (0x1U << 17)\r
+#define DP_DC_CONTROL_CM_ACTIVE (0x1U << 16)\r
+\r
+#define DP_DE_DP500_CONTROL_SOFTRESET_REQ (0x1U << 16)\r
+#define DP_DE_DP500_CONTROL_CONFIG_REQ (0x1U << 17)\r
+\r
+// Display core configuration valid register\r
+#define DP_DC_CONFIG_VALID_CVAL (0x1U)\r
+\r
+// DC_CORE_ID\r
+// Display core version register PRODUCT_ID\r
+#define DP_DC_CORE_ID_SHIFT 16\r
+#define DP_DE_DP500_CORE_ID_SHIFT DP_DC_CORE_ID_SHIFT\r
+\r
+// Timing settings\r
+#define DP_DE_HBACKPORCH_SHIFT 16\r
+#define DP_DE_VBACKPORCH_SHIFT 16\r
+#define DP_DE_VSP_SHIFT 28\r
+#define DP_DE_VSYNCWIDTH_SHIFT 16\r
+#define DP_DE_HSP_SHIFT 13\r
+#define DP_DE_V_ACTIVE_SHIFT 16\r
+\r
+// BACKGROUND_COLOR\r
+#define DP_DE_BG_R_PIXEL_SHIFT 16\r
+#define DP_DE_BG_G_PIXEL_SHIFT 8\r
+\r
+//Graphics layer LG_FORMAT Pixel Format\r
+#define DP_PIXEL_FORMAT_ARGB_8888 0x8\r
+#define DP_PIXEL_FORMAT_ABGR_8888 0x9\r
+#define DP_PIXEL_FORMAT_RGBA_8888 0xA\r
+#define DP_PIXEL_FORMAT_BGRA_8888 0xB\r
+#define DP_PIXEL_FORMAT_XRGB_8888 0x10\r
+#define DP_PIXEL_FORMAT_XBGR_8888 0x11\r
+#define DP_PIXEL_FORMAT_RGBX_8888 0x12\r
+#define DP_PIXEL_FORMAT_BGRX_8888 0x13\r
+#define DP_PIXEL_FORMAT_RGB_888 0x18\r
+#define DP_PIXEL_FORMAT_BGR_888 0x19\r
+\r
+// DP500 format code are different than DP550/DP650\r
+#define DP_PIXEL_FORMAT_DP500_ARGB_8888 0x2\r
+#define DP_PIXEL_FORMAT_DP500_ABGR_8888 0x3\r
+#define DP_PIXEL_FORMAT_DP500_XRGB_8888 0x4\r
+#define DP_PIXEL_FORMAT_DP500_XBGR_8888 0x5\r
+\r
+// Graphics layer LG_PTR_LOW and LG_PTR_HIGH\r
+#define DP_DE_LG_PTR_LOW_MASK 0xFFFFFFFFU\r
+#define DP_DE_LG_PTR_HIGH_SHIFT 32\r
+\r
+// Graphics layer LG_CONTROL register characteristics\r
+#define DP_DE_LG_L_ALPHA_SHIFT 16\r
+#define DP_DE_LG_CHK_SHIFT 15\r
+#define DP_DE_LG_PMUL_SHIFT 14\r
+#define DP_DE_LG_COM_SHIFT 12\r
+#define DP_DE_LG_VFP_SHIFT 11\r
+#define DP_DE_LG_HFP_SHIFT 10\r
+#define DP_DE_LG_ROTATION_SHIFT 8\r
+\r
+#define DP_DE_LG_LAYER_BLEND_NO_BG 0x0U\r
+#define DP_DE_LG_PIXEL_BLEND_NO_BG 0x1U\r
+#define DP_DE_LG_LAYER_BLEND_BG 0x2U\r
+#define DP_DE_LG_PIXEL_BLEND_BG 0x3U\r
+#define DP_DE_LG_ENABLE 0x1U\r
+\r
+// Graphics layer LG_IN_SIZE register characteristics\r
+#define DP_DE_LG_V_IN_SIZE_SHIFT 16\r
+\r
+// Graphics layer LG_CMP_SIZE register characteristics\r
+#define DP_DE_LG_V_CMP_SIZE_SHIFT 16\r
+#define DP_DE_LG_V_OFFSET_SHIFT 16\r
+\r
+// Helper display timing macro functions.\r
+#define H_INTERVALS(Hfp, Hbp) ((Hbp << DP_DE_HBACKPORCH_SHIFT) | Hfp)\r
+#define V_INTERVALS(Vfp, Vbp) ((Vbp << DP_DE_VBACKPORCH_SHIFT) | Vfp)\r
+#define SYNC_WIDTH(Hsw, Vsw) ((Vsw << DP_DE_VSYNCWIDTH_SHIFT) | Hsw)\r
+#define HV_ACTIVE(Hor, Ver) ((Ver << DP_DE_V_ACTIVE_SHIFT) | Hor)\r
+\r
+// Helper layer graphics macros.\r
+#define FRAME_IN_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_IN_SIZE_SHIFT) | Hor)\r
+#define FRAME_CMP_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_CMP_SIZE_SHIFT) | Hor)\r
+\r
+#endif /* ARMMALIDP_H_ */\r
--- /dev/null
+#/** @file\r
+#\r
+# Component description file for ArmMaliDp module\r
+#\r
+# Copyright (c) 2017-2018, Arm Limited. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010019\r
+ BASE_NAME = ArmMaliDp\r
+ FILE_GUID = E724AAF7-19E2-40A3-BAE1-D82A7C8B7A76\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = LcdHwLib\r
+\r
+[Sources.common]\r
+ ArmMaliDp.c\r
+\r
+[Packages]\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ BaseMemoryLib\r
+ DebugLib\r
+ IoLib\r
+ LcdPlatformLib\r
+ UefiLib\r
+\r
+[FixedPcd]\r
+ gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase\r
+\r
projects / mirror_edk2.git / commitdiff