UefiCpuPkg/PiSmmCpuDxeSmm: Add CPUID MCA support check
authorMichael D Kinney <michael.d.kinney@intel.com>
Wed, 16 Aug 2017 23:49:17 +0000 (16:49 -0700)
committerMichael D Kinney <michael.d.kinney@intel.com>
Thu, 17 Aug 2017 17:49:50 +0000 (10:49 -0700)
https://bugzilla.tianocore.org/show_bug.cgi?id=674

Add CPUID check to see if the CPU supports the Machine
Check Architecture before accessing the Machine Check
Architecture related MSRs.

Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c

index 6b66c49..f086b97 100644 (file)
@@ -27,6 +27,7 @@ SMM_CPU_SEMAPHORES                          mSmmCpuSemaphores;
 UINTN                                       mSemaphoreSize;\r
 SPIN_LOCK                                   *mPFLock = NULL;\r
 SMM_CPU_SYNC_MODE                           mCpuSmmSyncMode;\r
+BOOLEAN                                     mMachineCheckSupported = FALSE;\r
 \r
 /**\r
   Performs an atomic compare exchange operation to get semaphore.\r
@@ -264,8 +265,12 @@ SmmWaitForApArrival (
 \r
   ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus);\r
 \r
-  LmceEn = IsLmceOsEnabled ();\r
-  LmceSignal = IsLmceSignaled();\r
+  LmceEn     = FALSE;\r
+  LmceSignal = FALSE;\r
+  if (mMachineCheckSupported) {\r
+    LmceEn     = IsLmceOsEnabled ();\r
+    LmceSignal = IsLmceSignaled();\r
+  }\r
 \r
   //\r
   // Platform implementor should choose a timeout value appropriately:\r
@@ -1366,6 +1371,13 @@ InitializeMpServiceData (
   UINTN                     Index;\r
   UINT8                     *GdtTssTables;\r
   UINTN                     GdtTableStepSize;\r
+  CPUID_VERSION_INFO_EDX    RegEdx;\r
+\r
+  //\r
+  // Determine if this CPU supports machine check\r
+  //\r
+  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx.Uint32);\r
+  mMachineCheckSupported = (BOOLEAN)(RegEdx.Bits.MCA == 1);\r
 \r
   //\r
   // Allocate memory for all locks and semaphores\r