*/
blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
+
+ ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
+ mcr p15, 0, R1, c5, c0, 1 @ Write IFSR
+
+ ldr R1, [SP, #0x44] @ sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
+ mcr p15, 0, R1, c5, c0, 0 @ Write DFSR
ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored
*/
blx CommonCExceptionHandler ; Call exception handler
+ ldr R1, [SP, #0x4c] ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
+ mcr p15, 0, R1, c5, c0, 1 ; Write IFSR
+
+ ldr R1, [SP, #0x44] ; sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
+ mcr p15, 0, R1, c5, c0, 0 ; Write DFSR
+
ldr R1,[SP,#0x3c] ; EFI_SYSTEM_CONTEXT_ARM.PC
str R1,[SP,#0x58] ; Store it back to srsfd stack slot so it can be restored
#define ARM_PAGE_TYPE_SMALL 0x2\r
#define ARM_PAGE_TYPE_SMALL_XN 0x3\r
\r
-#define SMALL_PAGE_TABLE_ENTRY_COUNT (ARM_PAGE_DESC_ENTRY_MVA_SIZE / EFI_PAGE_SIZE)\r
+#define SMALL_PAGE_TABLE_ENTRY_COUNT (ARM_PAGE_DESC_ENTRY_MVA_SIZE / SIZE_4KB)\r
\r
\r
// Translation Table Base 0 fields\r
UINT32 p;\r
UINT32 PageTableIndex;\r
UINT32 PageTableEntry;\r
+ UINT32 CurrentPageTableEntry;\r
+ VOID *Mva;\r
\r
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r
\r
// calculate number of 4KB page table entries to change\r
- NumPageEntries = Length/EFI_PAGE_SIZE;\r
+ NumPageEntries = Length/SIZE_4KB;\r
\r
// iterate for the number of 4KB pages to change\r
Offset = 0;\r
ASSERT (PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);\r
\r
// get the entry\r
- PageTableEntry = PageTable[PageTableIndex];\r
+ CurrentPageTableEntry = PageTable[PageTableIndex];\r
\r
// mask off appropriate fields\r
- PageTableEntry &= ~EntryMask;\r
+ PageTableEntry = CurrentPageTableEntry & ~EntryMask;\r
\r
// mask in new attributes and/or permissions\r
PageTableEntry |= EntryValue;\r
// Make this virtual address point at a physical page\r
PageTableEntry &= ~VirtualMask;\r
}\r
- \r
- // update the entry\r
- PageTable[PageTableIndex] = PageTableEntry; \r
\r
+ if (CurrentPageTableEntry != PageTableEntry) {\r
+ Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << ARM_SECTION_BASE_SHIFT) + (PageTableIndex << ARM_SMALL_PAGE_BASE_SHIFT));\r
+ if ((CurrentPageTableEntry & ARM_PAGE_C) == ARM_PAGE_C) {\r
+ // The current section mapping is cacheable so Clean/Invalidate the MVA of the page\r
+ // Note assumes switch(Attributes), not ARMv7 possibilities\r
+ WriteBackInvalidateDataCacheRange (Mva, SIZE_4KB);\r
+ }\r
+\r
+ // Only need to update if we are changing the entry \r
+ PageTable[PageTableIndex] = PageTableEntry; \r
+ ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);\r
+ }\r
\r
Status = EFI_SUCCESS;\r
- Offset += EFI_PAGE_SIZE;\r
+ Offset += SIZE_4KB;\r
\r
} // end first level translation table loop\r
\r
UINT32 FirstLevelIdx;\r
UINT32 NumSections;\r
UINT32 i;\r
+ UINT32 CurrentDescriptor;\r
UINT32 Descriptor;\r
-\r
+ VOID *Mva;\r
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
\r
// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
switch(Attributes) {\r
case EFI_MEMORY_UC:\r
// modify cacheability attributes\r
- EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+ EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r
// map to strongly ordered\r
EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0\r
break;\r
\r
case EFI_MEMORY_WC:\r
// modify cacheability attributes\r
- EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+ EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r
// map to normal non-cachable\r
EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
break;\r
\r
case EFI_MEMORY_WT:\r
// modify cacheability attributes\r
- EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+ EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r
// write through with no-allocate\r
EntryValue |= ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0\r
break;\r
\r
case EFI_MEMORY_WB:\r
// modify cacheability attributes\r
- EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+ EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r
// write back (with allocate)\r
EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1\r
break;\r
\r
// iterate through each descriptor\r
for(i=0; i<NumSections; i++) {\r
- Descriptor = FirstLevelTable[FirstLevelIdx + i];\r
+ CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];\r
\r
// has this descriptor already been coverted to pages?\r
- if ((Descriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {\r
+ if ((CurrentDescriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {\r
// forward this 1MB range to page table function instead\r
Status = UpdatePageEntries ((FirstLevelIdx + i) << ARM_SECTION_BASE_SHIFT, ARM_PAGE_DESC_ENTRY_MVA_SIZE, Attributes, VirtualMask);\r
} else {\r
// still a section entry\r
\r
// mask off appropriate fields\r
- Descriptor &= ~EntryMask;\r
+ Descriptor = CurrentDescriptor & ~EntryMask;\r
\r
// mask in new attributes and/or permissions\r
Descriptor |= EntryValue;\r
Descriptor &= ~VirtualMask;\r
}\r
\r
- FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r
+ if (CurrentDescriptor != Descriptor) {\r
+ Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << ARM_SECTION_BASE_SHIFT);\r
+ if ((CurrentDescriptor & ARM_SECTION_C) == ARM_SECTION_C) {\r
+ // The current section mapping is cacheable so Clean/Invalidate the MVA of the section\r
+ // Note assumes switch(Attributes), not ARMv7 possabilities\r
+ WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);\r
+ }\r
+\r
+ // Only need to update if we are changing the descriptor \r
+ FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r
+ ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);\r
+ }\r
\r
Status = EFI_SUCCESS;\r
}\r
PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;\r
\r
// write the page table entries out\r
- for (i=0; i<(ARM_PAGE_DESC_ENTRY_MVA_SIZE/EFI_PAGE_SIZE); i++) {\r
+ for (i=0; i<(ARM_PAGE_DESC_ENTRY_MVA_SIZE/SIZE_4KB); i++) {\r
PageTable[i] = ((BaseAddress + (i << 12)) & ARM_SMALL_PAGE_BASE_MASK) | PageDescriptor;\r
}\r
\r
// flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
- InvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, EFI_PAGE_SIZE);\r
+ WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, SIZE_4KB);\r
\r
// formulate page table entry, Domain=0, NS=0\r
PageTableDescriptor = (((UINTN)PageTableAddr) & ARM_PAGE_DESC_BASE_MASK) | ARM_DESC_TYPE_PAGE_TABLE;\r
)\r
{\r
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));\r
- if ( ((BaseAddress & (EFI_PAGE_SIZE-1)) != 0) || ((Length & (EFI_PAGE_SIZE-1)) != 0)){\r
- // minimum granularity is EFI_PAGE_SIZE (4KB on ARM)\r
- DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is EFI_PAGE_SIZE\n", BaseAddress, Length, Attributes));\r
+ if ( ((BaseAddress & (SIZE_4KB-1)) != 0) || ((Length & (SIZE_4KB-1)) != 0)){\r
+ // minimum granularity is SIZE_4KB (4KB on ARM)\r
+ DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is SIZE_4KB\n", BaseAddress, Length, Attributes));\r
return EFI_UNSUPPORTED;\r
}\r
\r
VOID
EFIAPI
ArmUpdateTranslationTableEntry (
- IN UINTN Mva
+ IN VOID *TranslationTableEntry,
+ IN VOID *Mva
);
VOID
VOID
);
+
#endif // __ARM_LIB__
#------------------------------------------------------------------------------
#
-# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+# Copyright (c) 2008-2010 Apple Inc. All rights reserved.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
#
#------------------------------------------------------------------------------
-.text
-.align 2
.globl ASM_PFX(Cp15IdCode)
.globl ASM_PFX(Cp15CacheInfo)
.globl ASM_PFX(ArmEnableInterrupts)
.globl ASM_PFX(ArmSetTranslationTableBaseAddress)
.globl ASM_PFX(ArmGetTranslationTableBaseAddress)
.globl ASM_PFX(ArmSetDomainAccessControl)
+.globl ASM_PFX(ArmUpdateTranslationTableEntry)
.globl ASM_PFX(CPSRMaskInsert)
.globl ASM_PFX(CPSRRead)
.globl ASM_PFX(ReadCCSIDR)
.globl ASM_PFX(ReadCLIDR)
+.text
+.align 2
#------------------------------------------------------------------------------
ASM_PFX(ArmGetFiqState):
mrs R0,CPSR
- tst R0,#0x30 @Check if IRQ is enabled.
+ tst R0,#0x40 @Check if FIQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
ASM_PFX(ArmInvalidateTlb):
mov r0,#0
mcr p15,0,r0,c8,c7,0
+ mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
+ dsb
isb
bx lr
ASM_PFX(ArmGetTranslationTableBaseAddress):
mrc p15,0,r0,c2,c0,0
+ isb
bx lr
isb
bx lr
+//
+//VOID
+//ArmUpdateTranslationTableEntry (
+// IN VOID *TranslationTableEntry // R0
+// IN VOID *MVA // R1
+// );
+ASM_PFX(ArmUpdateTranslationTableEntry):
+ mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
+ dsb
+ mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
+ mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
+ dsb
+ isb
+ bx lr
+
ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
stmfd sp!, {r4-r12, lr} @ save all the banked registers
mov r3, sp @ copy the stack pointer into a non-banked register
and r1, r1, r0 @ clear bits outside the mask in the input
orr r2, r2, r1 @ set field
msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
+ isb
mov sp, r3 @ restore stack pointer
ldmfd sp!, {r4-r12, lr} @ restore registers
bx lr @ return (hopefully thumb-safe!)
mrs r0, cpsr
bx lr
+// UINT32
+// ReadCCSIDR (
+// IN UINT32 CSSELR
+// )
ASM_PFX(ReadCCSIDR):
mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
isb
mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
bx lr
-
+// UINT32
+// ReadCLIDR (
+// IN UINT32 CSSELR
+// )
ASM_PFX(ReadCLIDR):
mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
+ bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
//------------------------------------------------------------------------------
//
-// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+// Copyright (c) 2008-2010 Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
EXPORT ArmSetTranslationTableBaseAddress
EXPORT ArmGetTranslationTableBaseAddress
EXPORT ArmSetDomainAccessControl
+ EXPORT ArmUpdateTranslationTableEntry
EXPORT CPSRMaskInsert
EXPORT CPSRRead
EXPORT ReadCCSIDR
AREA ArmLibSupport, CODE, READONLY
+
+//------------------------------------------------------------------------------
+
Cp15IdCode
mrc p15,0,R0,c0,c0,0
bx LR
bx LR
ArmEnableInterrupts
- CPSIE i
+ cpsie i
bx LR
ArmDisableInterrupts
- CPSID i
+ cpsid i
bx LR
ArmGetInterruptState
moveq R0,#1
movne R0,#0
bx LR
-
+
ArmEnableFiq
- CPSIE f
+ cpsie f
bx LR
ArmDisableFiq
- CPSID f
+ cpsid f
bx LR
ArmGetFiqState
mrs R0,CPSR
- tst R0,#0x40 ;Check if IRQ is enabled.
+ tst R0,#0x40 ;Check if FIQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
ArmInvalidateTlb
mov r0,#0
mcr p15,0,r0,c8,c7,0
- ISB
+ mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp
+ dsb
+ isb
bx lr
ArmSetTranslationTableBaseAddress
mcr p15,0,r0,c2,c0,0
- ISB
+ isb
bx lr
ArmGetTranslationTableBaseAddress
mrc p15,0,r0,c2,c0,0
- ISB
+ isb
bx lr
+
ArmSetDomainAccessControl
mcr p15,0,r0,c3,c0,0
- ISB
+ isb
+ bx lr
+
+//
+//VOID
+//ArmUpdateTranslationTableEntry (
+// IN VOID *TranslationTableEntry // R0
+// IN VOID *MVA // R1
+// );
+ArmUpdateTranslationTableEntry
+ mcr p15,0,R0,c7,c14,1 ; DCCIMVAC Clean data cache by MVA
+ dsb
+ mcr p15,0,R1,c8,c7,1 ; TLBIMVA TLB Invalidate MVA
+ mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp
+ dsb
+ isb
bx lr
CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
and r1, r1, r0 ; clear bits outside the mask in the input
orr r2, r2, r1 ; set field
msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
- ISB
+ isb
mov sp, r3 ; restore stack pointer
ldmfd sp!, {r4-r12, lr} ; restore registers
bx lr ; return (hopefully thumb-safe!)
// IN UINT32 CSSELR
// )
ReadCCSIDR
- MCR p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
- ISB
- MRC p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
- BX lr
+ mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
+ isb
+ mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
+ bx lr
// UINT32
// IN UINT32 CSSELR
// )
ReadCLIDR
- MRC p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
- END
+ mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
+ bx lr
+
+
+END
isb
bx LR
+
ArmEnableDataCache
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
DEBUG ((EFI_D_ERROR, "\n"));\r
ASSERT (FALSE);\r
\r
+ // Clear the error registers that we have already displayed incase some one wants to keep going\r
+ SystemContext.SystemContextArm->DFSR = 0;\r
+ SystemContext.SystemContextArm->IFSR = 0;\r
+\r
// If some one is stepping past the exception handler adjust the PC to point to the next instruction \r
SystemContext.SystemContextArm->PC += PcAdjust;\r
}\r